[J-u-boot.git] / drivers / rtc / ds1337.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001-2008
 * Copyright 2020 NXP
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Keith Outwater, [email protected]`
 */

/*
 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
 * DS1337 Real Time Clock (RTC).
 */

#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
#include <rtc.h>
#include <i2c.h>

/*
 * RTC register addresses
 */
#if defined CONFIG_RTC_DS1337
#define RTC_SEC_REG_ADDR	0x0
#define RTC_MIN_REG_ADDR	0x1
#define RTC_HR_REG_ADDR		0x2
#define RTC_DAY_REG_ADDR	0x3
#define RTC_DATE_REG_ADDR	0x4
#define RTC_MON_REG_ADDR	0x5
#define RTC_YR_REG_ADDR		0x6
#define RTC_CTL_REG_ADDR	0x0e
#define RTC_STAT_REG_ADDR	0x0f
#define RTC_TC_REG_ADDR		0x10
#elif defined CONFIG_RTC_DS1388
#define RTC_SEC_REG_ADDR	0x1
#define RTC_MIN_REG_ADDR	0x2
#define RTC_HR_REG_ADDR		0x3
#define RTC_DAY_REG_ADDR	0x4
#define RTC_DATE_REG_ADDR	0x5
#define RTC_MON_REG_ADDR	0x6
#define RTC_YR_REG_ADDR		0x7
#define RTC_CTL_REG_ADDR	0x0c
#define RTC_STAT_REG_ADDR	0x0b
#define RTC_TC_REG_ADDR		0x0a
#endif

/*
 * RTC control register bits
 */
#define RTC_CTL_BIT_A1IE	0x1	/* Alarm 1 interrupt enable	*/
#define RTC_CTL_BIT_A2IE	0x2	/* Alarm 2 interrupt enable	*/
#define RTC_CTL_BIT_INTCN	0x4	/* Interrupt control		*/
#define RTC_CTL_BIT_RS1		0x8	/* Rate select 1		*/
#define RTC_CTL_BIT_RS2		0x10	/* Rate select 2		*/
#define RTC_CTL_BIT_DOSC	0x80	/* Disable Oscillator		*/

/*
 * RTC status register bits
 */
#define RTC_STAT_BIT_A1F	0x1	/* Alarm 1 flag			*/
#define RTC_STAT_BIT_A2F	0x2	/* Alarm 2 flag			*/
#define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag		*/


#if !CONFIG_IS_ENABLED(DM_RTC)
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);

/*
 * Get the current time from the RTC
 */
int rtc_get (struct rtc_time *tmp)
{
	int rel = 0;
	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;

	control = rtc_read (RTC_CTL_REG_ADDR);
	status = rtc_read (RTC_STAT_REG_ADDR);
	sec = rtc_read (RTC_SEC_REG_ADDR);
	min = rtc_read (RTC_MIN_REG_ADDR);
	hour = rtc_read (RTC_HR_REG_ADDR);
	wday = rtc_read (RTC_DAY_REG_ADDR);
	mday = rtc_read (RTC_DATE_REG_ADDR);
	mon_cent = rtc_read (RTC_MON_REG_ADDR);
	year = rtc_read (RTC_YR_REG_ADDR);

	/* No century bit, assume year 2000 */
#ifdef CONFIG_RTC_DS1388
	mon_cent |= 0x80;
#endif

	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
		year, mon_cent, mday, wday, hour, min, sec, control, status);

	if (status & RTC_STAT_BIT_OSF) {
		printf ("### Warning: RTC oscillator has stopped\n");
		/* clear the OSF flag */
		rtc_write (RTC_STAT_REG_ADDR,
			   rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
		rel = -1;
	}

	tmp->tm_sec  = bcd2bin (sec & 0x7F);
	tmp->tm_min  = bcd2bin (min & 0x7F);
	tmp->tm_hour = bcd2bin (hour & 0x3F);
	tmp->tm_mday = bcd2bin (mday & 0x3F);
	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
	tmp->tm_yday = 0;
	tmp->tm_isdst= 0;

	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return rel;
}


/*
 * Set the RTC
 */
int rtc_set (struct rtc_time *tmp)
{
	uchar century;

	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));

	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);

	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));

	return 0;
}


/*
 * Reset the RTC.  We also enable the oscillator output on the
 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
 * according to the datasheet, turning on the square wave output
 * increases the current drain on the backup battery from about
 * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
 * off the OSC output.
 */

#ifdef CONFIG_RTC_DS1337_NOOSC
 #define RTC_DS1337_RESET_VAL \
	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#else
 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#endif
void rtc_reset (void)
{
#ifdef CONFIG_RTC_DS1337
	rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
#elif defined CONFIG_RTC_DS1388
	rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
#endif
#ifdef CONFIG_RTC_DS1339_TCR_VAL
	rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
#endif
#ifdef CONFIG_RTC_DS1388_TCR_VAL
	rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
#endif
}


/*
 * Helper functions
 */

static
uchar rtc_read (uchar reg)
{
	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}


static void rtc_write (uchar reg, uchar val)
{
	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static uchar rtc_read(struct udevice *dev, uchar reg)
{
	return dm_i2c_reg_read(dev, reg);
}

static void rtc_write(struct udevice *dev, uchar reg, uchar val)
{
	dm_i2c_reg_write(dev, reg, val);
}

static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp)
{
	int rel = 0;
	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;

	control = rtc_read(dev, RTC_CTL_REG_ADDR);
	status = rtc_read(dev, RTC_STAT_REG_ADDR);
	sec = rtc_read(dev, RTC_SEC_REG_ADDR);
	min = rtc_read(dev, RTC_MIN_REG_ADDR);
	hour = rtc_read(dev, RTC_HR_REG_ADDR);
	wday = rtc_read(dev, RTC_DAY_REG_ADDR);
	mday = rtc_read(dev, RTC_DATE_REG_ADDR);
	mon_cent = rtc_read(dev, RTC_MON_REG_ADDR);
	year = rtc_read(dev, RTC_YR_REG_ADDR);

	/* No century bit, assume year 2000 */
#ifdef CONFIG_RTC_DS1388
	mon_cent |= 0x80;
#endif

	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n",
	      year, mon_cent, mday, wday);
	debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
	      hour, min, sec, control, status);

	if (status & RTC_STAT_BIT_OSF) {
		printf("### Warning: RTC oscillator has stopped\n");
		/* clear the OSF flag */
		rtc_write(dev, RTC_STAT_REG_ADDR,
			  rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
		rel = -1;
	}

	tmp->tm_sec = bcd2bin(sec & 0x7F);
	tmp->tm_min = bcd2bin(min & 0x7F);
	tmp->tm_hour = bcd2bin(hour & 0x3F);
	tmp->tm_mday = bcd2bin(mday & 0x3F);
	tmp->tm_mon  = bcd2bin(mon_cent & 0x1F);
	tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900);
	tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
	tmp->tm_yday = 0;
	tmp->tm_isdst = 0;

	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	      tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return rel;
}

static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
{
	uchar century;

	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	      tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));

	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
	rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century);

	rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
	rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
	rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
	rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
	rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));

	return 0;
}

#ifdef CONFIG_RTC_DS1337_NOOSC
 #define RTC_DS1337_RESET_VAL \
	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#else
 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#endif
static int ds1337_rtc_reset(struct udevice *dev)
{
#ifdef CONFIG_RTC_DS1337
	rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
#elif defined CONFIG_RTC_DS1388
	rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */
#endif
#ifdef CONFIG_RTC_DS1339_TCR_VAL
	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
#endif
#ifdef CONFIG_RTC_DS1388_TCR_VAL
	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
#endif
	return 0;
}

static const struct rtc_ops ds1337_rtc_ops = {
	.get = ds1337_rtc_get,
	.set = ds1337_rtc_set,
	.reset = ds1337_rtc_reset,
};

static const struct udevice_id ds1337_rtc_ids[] = {
	{ .compatible = "ds1337" },
	{ .compatible = "ds1338" },
	{ .compatible = "ds1339" },
	{ }
};

U_BOOT_DRIVER(rtc_ds1337) = {
	.name   = "rtc-ds1337",
	.id     = UCLASS_RTC,
	.of_match = ds1337_rtc_ids,
	.ops    = &ds1337_rtc_ops,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5d3207da	2	/*
5b5eb9ca	3	* (C) Copyright 2001-2008
3bebb4f3	4	* Copyright 2020 NXP
5d3207da WD	5	* Wolfgang Denk, DENX Software Engineering, [email protected].
5d3207da WD	6	* Keith Outwater, [email protected]`
5d3207da WD	7	*/
	8
	9	/*
	10	* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
	11	* DS1337 Real Time Clock (RTC).
	12	*/
	13
16a50b66	14	#include <config.h>
5d3207da	15	#include <command.h>
3bebb4f3	16	#include <dm.h>
f7ae49fc	17	#include <log.h>
5d3207da WD	18	#include <rtc.h>
	19	#include <i2c.h>
	20
5d3207da WD	21	/*
	22	* RTC register addresses
	23	*/
8fde2f3a	24	#if defined CONFIG_RTC_DS1337
5d3207da WD	25	#define RTC_SEC_REG_ADDR 0x0
	26	#define RTC_MIN_REG_ADDR 0x1
	27	#define RTC_HR_REG_ADDR 0x2
	28	#define RTC_DAY_REG_ADDR 0x3
	29	#define RTC_DATE_REG_ADDR 0x4
	30	#define RTC_MON_REG_ADDR 0x5
	31	#define RTC_YR_REG_ADDR 0x6
	32	#define RTC_CTL_REG_ADDR 0x0e
	33	#define RTC_STAT_REG_ADDR 0x0f
b0078c87	34	#define RTC_TC_REG_ADDR 0x10
8fde2f3a KE	35	#elif defined CONFIG_RTC_DS1388
	36	#define RTC_SEC_REG_ADDR 0x1
	37	#define RTC_MIN_REG_ADDR 0x2
	38	#define RTC_HR_REG_ADDR 0x3
	39	#define RTC_DAY_REG_ADDR 0x4
	40	#define RTC_DATE_REG_ADDR 0x5
	41	#define RTC_MON_REG_ADDR 0x6
	42	#define RTC_YR_REG_ADDR 0x7
	43	#define RTC_CTL_REG_ADDR 0x0c
	44	#define RTC_STAT_REG_ADDR 0x0b
	45	#define RTC_TC_REG_ADDR 0x0a
	46	#endif
5d3207da WD	47
	48	/*
	49	* RTC control register bits
	50	*/
5b5eb9ca WD	51	#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
	52	#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
	53	#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
	54	#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
	55	#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
	56	#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
5d3207da WD	57
	58	/*
	59	* RTC status register bits
	60	*/
5b5eb9ca WD	61	#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
	62	#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
	63	#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
5d3207da WD	64
5d3207da WD	65
3bebb4f3	66	#if !CONFIG_IS_ENABLED(DM_RTC)
5d3207da WD	67	static uchar rtc_read (uchar reg);
5d3207da WD	68	static void rtc_write (uchar reg, uchar val);
5d3207da WD	69
	70	/*
	71	* Get the current time from the RTC
	72	*/
b73a19e1	73	int rtc_get (struct rtc_time *tmp)
5d3207da	74	{
b73a19e1	75	int rel = 0;
5d3207da WD	76	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
	77
	78	control = rtc_read (RTC_CTL_REG_ADDR);
	79	status = rtc_read (RTC_STAT_REG_ADDR);
	80	sec = rtc_read (RTC_SEC_REG_ADDR);
	81	min = rtc_read (RTC_MIN_REG_ADDR);
	82	hour = rtc_read (RTC_HR_REG_ADDR);
	83	wday = rtc_read (RTC_DAY_REG_ADDR);
	84	mday = rtc_read (RTC_DATE_REG_ADDR);
	85	mon_cent = rtc_read (RTC_MON_REG_ADDR);
	86	year = rtc_read (RTC_YR_REG_ADDR);
	87
8fde2f3a KE	88	/* No century bit, assume year 2000 */
	89	#ifdef CONFIG_RTC_DS1388
	90	mon_cent \|= 0x80;
	91	#endif
	92
88b2533d	93	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
5d3207da WD	94	"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
	95	year, mon_cent, mday, wday, hour, min, sec, control, status);
	96
	97	if (status & RTC_STAT_BIT_OSF) {
	98	printf ("### Warning: RTC oscillator has stopped\n");
	99	/* clear the OSF flag */
	100	rtc_write (RTC_STAT_REG_ADDR,
	101	rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
b73a19e1	102	rel = -1;
5d3207da WD	103	}
	104
	105	tmp->tm_sec = bcd2bin (sec & 0x7F);
	106	tmp->tm_min = bcd2bin (min & 0x7F);
	107	tmp->tm_hour = bcd2bin (hour & 0x3F);
	108	tmp->tm_mday = bcd2bin (mday & 0x3F);
	109	tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
	110	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
	111	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
	112	tmp->tm_yday = 0;
	113	tmp->tm_isdst= 0;
	114
88b2533d	115	debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
5d3207da WD	116	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
5d3207da WD	117	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
b73a19e1 YT	118
b73a19e1 YT	119	return rel;
5d3207da WD	120	}
	121
	122
	123	/*
	124	* Set the RTC
	125	*/
d1e23194	126	int rtc_set (struct rtc_time *tmp)
5d3207da WD	127	{
	128	uchar century;
	129
88b2533d	130	debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
5d3207da WD	131	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	132	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
	133
	134	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
	135
	136	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
	137	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) \| century);
	138
	139	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
	140	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
	141	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
	142	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
	143	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
d1e23194 JCPV	144
d1e23194 JCPV	145	return 0;
5d3207da WD	146	}
	147
	148
	149	/*
	150	* Reset the RTC. We also enable the oscillator output on the
	151	* SQW/INTB* pin and program it for 32,768 Hz output. Note that
	152	* according to the datasheet, turning on the square wave output
	153	* increases the current drain on the backup battery from about
2bd3cab3	154	* 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
da8808df	155	* off the OSC output.
5d3207da	156	*/
8fde2f3a	157
2bd3cab3	158	#ifdef CONFIG_RTC_DS1337_NOOSC
da8808df	159	#define RTC_DS1337_RESET_VAL \
5b5eb9ca	160	(RTC_CTL_BIT_INTCN \| RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
da8808df JT	161	#else
	162	#define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
	163	#endif
5d3207da WD	164	void rtc_reset (void)
5d3207da WD	165	{
2bd3cab3	166	#ifdef CONFIG_RTC_DS1337
da8808df	167	rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
2bd3cab3	168	#elif defined CONFIG_RTC_DS1388
8fde2f3a KE	169	rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
8fde2f3a KE	170	#endif
2bd3cab3 CP	171	#ifdef CONFIG_RTC_DS1339_TCR_VAL
2bd3cab3 CP	172	rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
b0078c87	173	#endif
2bd3cab3 CP	174	#ifdef CONFIG_RTC_DS1388_TCR_VAL
2bd3cab3 CP	175	rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
8fde2f3a	176	#endif
5d3207da WD	177	}
	178
	179
	180	/*
	181	* Helper functions
	182	*/
	183
	184	static
	185	uchar rtc_read (uchar reg)
	186	{
65cc0e2a	187	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
5d3207da WD	188	}
	189
	190
	191	static void rtc_write (uchar reg, uchar val)
	192	{
65cc0e2a	193	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
5d3207da	194	}
3bebb4f3 BL	195	#else
	196	static uchar rtc_read(struct udevice *dev, uchar reg)
	197	{
	198	return dm_i2c_reg_read(dev, reg);
	199	}
	200
	201	static void rtc_write(struct udevice *dev, uchar reg, uchar val)
	202	{
	203	dm_i2c_reg_write(dev, reg, val);
	204	}
	205
	206	static int ds1337_rtc_get(struct udevice dev, struct rtc_time tmp)
	207	{
	208	int rel = 0;
	209	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
	210
	211	control = rtc_read(dev, RTC_CTL_REG_ADDR);
	212	status = rtc_read(dev, RTC_STAT_REG_ADDR);
	213	sec = rtc_read(dev, RTC_SEC_REG_ADDR);
	214	min = rtc_read(dev, RTC_MIN_REG_ADDR);
	215	hour = rtc_read(dev, RTC_HR_REG_ADDR);
	216	wday = rtc_read(dev, RTC_DAY_REG_ADDR);
	217	mday = rtc_read(dev, RTC_DATE_REG_ADDR);
	218	mon_cent = rtc_read(dev, RTC_MON_REG_ADDR);
	219	year = rtc_read(dev, RTC_YR_REG_ADDR);
	220
	221	/* No century bit, assume year 2000 */
	222	#ifdef CONFIG_RTC_DS1388
	223	mon_cent \|= 0x80;
	224	#endif
	225
	226	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n",
	227	year, mon_cent, mday, wday);
	228	debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
	229	hour, min, sec, control, status);
	230
	231	if (status & RTC_STAT_BIT_OSF) {
	232	printf("### Warning: RTC oscillator has stopped\n");
	233	/* clear the OSF flag */
	234	rtc_write(dev, RTC_STAT_REG_ADDR,
	235	rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
	236	rel = -1;
	237	}
	238
	239	tmp->tm_sec = bcd2bin(sec & 0x7F);
	240	tmp->tm_min = bcd2bin(min & 0x7F);
	241	tmp->tm_hour = bcd2bin(hour & 0x3F);
	242	tmp->tm_mday = bcd2bin(mday & 0x3F);
	243	tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
	244	tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900);
	245	tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
	246	tmp->tm_yday = 0;
	247	tmp->tm_isdst = 0;
	248
	249	debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	250	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	251	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
	252
	253	return rel;
	254	}
	255
	256	static int ds1337_rtc_set(struct udevice dev, const struct rtc_time tmp)
	257	{
	258	uchar century;
259
260	debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
261	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
262	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
263
264	rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
265
266	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
267	rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) \| century);
268
269	rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
270	rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
271	rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
272	rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
273	rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
274
275	return 0;
276	}
277
278	#ifdef CONFIG_RTC_DS1337_NOOSC
279	#define RTC_DS1337_RESET_VAL \
280	(RTC_CTL_BIT_INTCN \| RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
281	#else
282	#define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
283	#endif
284	static int ds1337_rtc_reset(struct udevice *dev)
285	{
286	#ifdef CONFIG_RTC_DS1337
287	rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
288	#elif defined CONFIG_RTC_DS1388
289	rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */
290	#endif
291	#ifdef CONFIG_RTC_DS1339_TCR_VAL
292	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
293	#endif
294	#ifdef CONFIG_RTC_DS1388_TCR_VAL
295	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
296	#endif
297	return 0;
298	}
299
300	static const struct rtc_ops ds1337_rtc_ops = {
301	.get = ds1337_rtc_get,
302	.set = ds1337_rtc_set,
303	.reset = ds1337_rtc_reset,
304	};
305
306	static const struct udevice_id ds1337_rtc_ids[] = {
307	{ .compatible = "ds1337" },
308	{ .compatible = "ds1338" },
6f84e809	309	{ .compatible = "ds1339" },
3bebb4f3 BL	310	{ }
	311	};
	312
	313	U_BOOT_DRIVER(rtc_ds1337) = {
	314	.name = "rtc-ds1337",
	315	.id = UCLASS_RTC,
	316	.of_match = ds1337_rtc_ids,
	317	.ops = &ds1337_rtc_ops,
	318	};
	319	#endif