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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
024a26bc WD |
2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Rich Ireland, Enterasys Networks, [email protected]. | |
024a26bc WD |
5 | */ |
6 | ||
53677ef1 | 7 | #include <linux/types.h> /* for ulong typedef */ |
024a26bc WD |
8 | |
9 | #ifndef _FPGA_H_ | |
10 | #define _FPGA_H_ | |
11 | ||
12 | #ifndef CONFIG_MAX_FPGA_DEVICES | |
13 | #define CONFIG_MAX_FPGA_DEVICES 5 | |
14 | #endif | |
15 | ||
024a26bc | 16 | /* fpga_xxxx function return value definitions */ |
53677ef1 | 17 | #define FPGA_SUCCESS 0 |
5a4675a9 | 18 | #define FPGA_FAIL 1 |
024a26bc WD |
19 | |
20 | /* device numbers must be non-negative */ | |
53677ef1 | 21 | #define FPGA_INVALID_DEVICE -1 |
024a26bc | 22 | |
cedd48e2 SDPP |
23 | #define FPGA_ENC_USR_KEY 1 |
24 | #define FPGA_NO_ENC_OR_NO_AUTH 2 | |
25 | ||
024a26bc | 26 | /* root data type defintions */ |
53677ef1 WD |
27 | typedef enum { /* typedef fpga_type */ |
28 | fpga_min_type, /* range check value */ | |
29 | fpga_xilinx, /* Xilinx Family) */ | |
30 | fpga_altera, /* unimplemented */ | |
3b8ac464 | 31 | fpga_lattice, /* Lattice family */ |
53677ef1 WD |
32 | fpga_undefined /* invalid range check value */ |
33 | } fpga_type; /* end, typedef fpga_type */ | |
024a26bc | 34 | |
53677ef1 WD |
35 | typedef struct { /* typedef fpga_desc */ |
36 | fpga_type devtype; /* switch value to select sub-functions */ | |
37 | void *devdesc; /* real device descriptor */ | |
38 | } fpga_desc; /* end, typedef fpga_desc */ | |
024a26bc | 39 | |
1a897668 SDPP |
40 | typedef struct { /* typedef fpga_desc */ |
41 | unsigned int blocksize; | |
42 | char *interface; | |
43 | char *dev_part; | |
3003c445 | 44 | const char *filename; |
1a897668 SDPP |
45 | int fstype; |
46 | } fpga_fs_info; | |
024a26bc | 47 | |
cedd48e2 SDPP |
48 | struct fpga_secure_info { |
49 | u8 *userkey_addr; | |
50 | u8 authflag; | |
51 | u8 encflag; | |
52 | }; | |
53 | ||
7a78bd26 MS |
54 | typedef enum { |
55 | BIT_FULL = 0, | |
67193864 | 56 | BIT_PARTIAL, |
ddbcf8f2 | 57 | BIT_NONE = 0xFF, |
7a78bd26 MS |
58 | } bitstream_type; |
59 | ||
024a26bc | 60 | /* root function definitions */ |
6583505c MS |
61 | void fpga_init(void); |
62 | int fpga_add(fpga_type devtype, void *desc); | |
63 | int fpga_count(void); | |
ebd322de | 64 | const fpga_desc *const fpga_get_desc(int devnum); |
8b93a92f | 65 | int fpga_is_partial_data(int devnum, size_t img_len); |
6583505c MS |
66 | int fpga_load(int devnum, const void *buf, size_t bsize, |
67 | bitstream_type bstype); | |
68 | int fpga_fsload(int devnum, const void *buf, size_t size, | |
69 | fpga_fs_info *fpga_fsinfo); | |
cedd48e2 SDPP |
70 | int fpga_loads(int devnum, const void *buf, size_t size, |
71 | struct fpga_secure_info *fpga_sec_info); | |
6583505c MS |
72 | int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, |
73 | bitstream_type bstype); | |
74 | int fpga_dump(int devnum, const void *buf, size_t bsize); | |
75 | int fpga_info(int devnum); | |
76 | const fpga_desc *const fpga_validate(int devnum, const void *buf, | |
77 | size_t bsize, char *fn); | |
024a26bc WD |
78 | |
79 | #endif /* _FPGA_H_ */ |