[J-u-boot.git] / include / configs / socfpga_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

#include <linux/stringify.h>

/*
 * High level configuration
 */
#define CONFIG_CLOCKS

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * Memory configurations
 */
#define PHYS_SDRAM_1			0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	SOCFPGA_PHYS_OCRAM_SIZE
#define CONFIG_SPL_PAD_TO		0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
#define CONFIG_SPL_PAD_TO		0x40000
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x10000
#endif
#define CONFIG_SYS_INIT_RAM_SIZE	(SOCFPGA_PHYS_OCRAM_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE)
#endif

/*
 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
 * SRAM as bootcounter storage. Make sure to not put the stack directly
 * at this address to not overwrite the bootcounter by checking, if the
 * bootcounter address is located in the internal SRAM.
 */
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&	\
     (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +	\
				   CONFIG_SYS_INIT_RAM_SIZE)))
#define CONFIG_SPL_STACK		CONFIG_SYS_BOOTCOUNT_ADDR
#else
#define CONFIG_SPL_STACK			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif

/*
 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
 * in U-Boot pre-reloc is higher than in SPL.
 */
#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK_R_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
#endif

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * Ethernet on SoC (EMAC)
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_DW_ALTDESCRIPTOR
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
#ifndef CONFIG_TIMER
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifndef CONFIG_SYS_TIMER_RATE
#define CONFIG_SYS_TIMER_RATE		25000000
#endif
#endif

/*
 * L4 Watchdog
 */
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#endif

/*
 * QSPI support
 */
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif

/*
 * USB
 */

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */

/* Environment for SDMMC boot */

/* Environment for QSPI boot */

/*
 * SPL
 *
 * SRAM Memory layout for gen 5:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Global Data
 * 0xFFFF_zzzz ...... Malloc area
 * 0xFFFF_FFFF ...... End of SRAM
 *
 * SRAM Memory layout for Arria 10:
 * 0xFFE0_0000 ...... Start of SRAM (bottom)
 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 * 0xFFEy_yyyy ...... Global Data
 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 * 0xFFE3_FFFF ...... End of SRAM (top)
 */
#ifndef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
#endif

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
#endif
#endif

/* SPL QSPI boot support */

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
#endif
#endif

/* Extra Environment */
#ifndef CONFIG_SPL_BUILD

#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif

#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif

#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif

#define BOOT_TARGET_DEVICES(func) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_PXE(func) \
	BOOT_TARGET_DEVICES_DHCP(func)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	"fdt_addr_r=0x02000000\0" \
	"scriptaddr=0x02100000\0" \
	"pxefile_addr_r=0x02200000\0" \
	"ramdisk_addr_r=0x02300000\0" \
	"socfpga_legacy_reset_compat=1\0" \
	BOOTENV

#endif
#endif

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5095ee08 PM	2	/*
5095ee08 PM	3	* Copyright (C) 2012 Altera Corporation <www.altera.com>
5095ee08	4	*/
48275c96 DN	5	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	6	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	7
1af3c7f4 SG	8	#include <linux/stringify.h>
1af3c7f4 SG	9
5095ee08 PM	10	/*
	11	* High level configuration
	12	*/
5095ee08 PM	13	#define CONFIG_CLOCKS
5095ee08 PM	14
5095ee08 PM	15	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	16
	17	/*
	18	* Memory configurations
	19	*/
5095ee08	20	#define PHYS_SDRAM_1 0x0
1b259403	21	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
5095ee08	22	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
4f17f296	23	#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
53b59290	24	#define CONFIG_SPL_PAD_TO 0x10000
1b259403 LFT	25	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
1b259403 LFT	26	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
53b59290	27	#define CONFIG_SPL_PAD_TO 0x40000
4399e48d SG	28	/* SPL memory allocation configuration, this is for FAT implementation */
	29	#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
	30	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
	31	#endif
4f17f296 LFT	32	#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
4f17f296 LFT	33	CONFIG_SYS_SPL_MALLOC_SIZE)
4399e48d SG	34	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
4399e48d SG	35	CONFIG_SYS_INIT_RAM_SIZE)
1b259403	36	#endif
f457c52e SR	37
	38	/*
	39	* Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
	40	* SRAM as bootcounter storage. Make sure to not put the stack directly
	41	* at this address to not overwrite the bootcounter by checking, if the
	42	* bootcounter address is located in the internal SRAM.
	43	*/
	44	#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
	45	(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
	46	CONFIG_SYS_INIT_RAM_SIZE)))
4399e48d	47	#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
f457c52e	48	#else
4399e48d	49	#define CONFIG_SPL_STACK \
768f23dc	50	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
f457c52e	51	#endif
5095ee08	52
4399e48d SG	53	/*
	54	* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
	55	* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
	56	* in U-Boot pre-reloc is higher than in SPL.
	57	*/
	58	#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
	59	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
	60	#else
	61	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
	62	#endif
	63
5095ee08	64	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
5095ee08 PM	65
	66	/*
	67	* U-Boot general configurations
	68	*/
5095ee08	69	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5095ee08 PM	70	/* Print buffer size */
	71	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	72	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	73	/* Boot argument buffer size */
5095ee08 PM	74
	75	/*
	76	* Cache
	77	*/
5095ee08 PM	78	#define CONFIG_SYS_L2_PL310
	79	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	80
	81	/*
	82	* Ethernet on SoC (EMAC)
	83	*/
f7917328	84	#ifdef CONFIG_CMD_NET
5095ee08	85	#define CONFIG_DW_ALTDESCRIPTOR
5095ee08 PM	86	#endif
	87
	88	/*
	89	* FPGA Driver
	90	*/
	91	#ifdef CONFIG_CMD_FPGA
5095ee08 PM	92	#define CONFIG_FPGA_COUNT 1
5095ee08 PM	93	#endif
9af91b7c	94
5095ee08 PM	95	/*
	96	* L4 OSC1 Timer 0
	97	*/
331c3722	98	#ifndef CONFIG_TIMER
5095ee08 PM	99	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	100	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	101	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
c808ab47	102	#ifndef CONFIG_SYS_TIMER_RATE
5095ee08	103	#define CONFIG_SYS_TIMER_RATE 25000000
331c3722	104	#endif
c808ab47	105	#endif
5095ee08 PM	106
	107	/*
	108	* L4 Watchdog
	109	*/
5095ee08 PM	110	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
5095ee08 PM	111	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
5095ee08 PM	112
	113	/*
	114	* MMC Driver
	115	*/
	116	#ifdef CONFIG_CMD_MMC
5095ee08 PM	117	/* FIXME */
	118	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	119	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	120	#endif
	121
c339ea5b MV	122	/*
	123	* NAND Support
	124	*/
	125	#ifdef CONFIG_NAND_DENALI
85f748ad	126	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
c339ea5b	127	#define CONFIG_SYS_MAX_NAND_DEVICE 1
c339ea5b	128	#define CONFIG_SYS_NAND_ONFI_DETECTION
c339ea5b MV	129	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
c339ea5b MV	130	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
c339ea5b MV	131	#endif
c339ea5b MV	132
7fb0f596 SR	133	/*
	134	* QSPI support
	135	*/
7fb0f596 SR	136	/* QSPI reference clock */
	137	#ifndef __ASSEMBLY__
	138	unsigned int cm_get_qspi_controller_clk_hz(void);
	139	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	140	#endif
7fb0f596	141
20cadbbe MV	142	/*
	143	* USB
	144	*/
20cadbbe	145
0223a95c MV	146	/*
	147	* USB Gadget (DFU, UMS)
	148	*/
	149	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
0223a95c MV	150	#define DFU_DEFAULT_POLL_TIMEOUT 300
	151
	152	/* USB IDs */
e6c0bc06 SP	153	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	154	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	155	#endif
0223a95c MV	156
5095ee08 PM	157	/*
	158	* U-Boot environment
	159	*/
5095ee08	160
79cc48e7	161	/* Environment for SDMMC boot */
79cc48e7	162
ec8b7528	163	/* Environment for QSPI boot */
ec8b7528	164
5095ee08 PM	165	/*
5095ee08 PM	166	* SPL
34584d19	167	*
421a21c5	168	* SRAM Memory layout for gen 5:
34584d19 MV	169	*
	170	* 0xFFFF_0000 ...... Start of SRAM
	171	* 0xFFFF_xxxx ...... Top of stack (grows down)
798baf7c SG	172	* 0xFFFF_yyyy ...... Global Data
	173	* 0xFFFF_zzzz ...... Malloc area
	174	* 0xFFFF_FFFF ...... End of SRAM
421a21c5 TFC	175	*
	176	* SRAM Memory layout for Arria 10:
	177	* 0xFFE0_0000 ...... Start of SRAM (bottom)
	178	* 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
	179	* 0xFFEy_yyyy ...... Global Data
	180	* 0xFFEz_zzzz ...... Malloc area (grows up to top)
	181	* 0xFFE3_FFFF ...... End of SRAM (top)
5095ee08	182	*/
92a47459	183	#ifndef CONFIG_SPL_TEXT_BASE
1b259403	184	#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
92a47459	185	#endif
5095ee08	186
d3f34e75 MV	187	/* SPL SDMMC boot support */
d3f34e75 MV	188	#ifdef CONFIG_SPL_MMC_SUPPORT
f4b40924	189	#if defined(CONFIG_SPL_FS_FAT) \|\| defined(CONFIG_SPL_FS_EXT4)
998f7cb2	190	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
451e8241 DW	191	#endif
	192	#else
	193	#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
	194	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
d3f34e75 MV	195	#endif
d3f34e75 MV	196	#endif
5095ee08	197
346d6f56	198	/* SPL QSPI boot support */
346d6f56	199
c339ea5b MV	200	/* SPL NAND boot support */
c339ea5b MV	201	#ifdef CONFIG_SPL_NAND_SUPPORT
bd6363a7	202	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
c339ea5b	203	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
bd6363a7 MV	204	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	205	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
	206	#endif
c339ea5b MV	207	#endif
c339ea5b MV	208
451e8241 DW	209	/* Extra Environment */
451e8241 DW	210	#ifndef CONFIG_SPL_BUILD
451e8241	211
1c7fa793 SG	212	#ifdef CONFIG_CMD_DHCP
	213	#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
	214	#else
	215	#define BOOT_TARGET_DEVICES_DHCP(func)
	216	#endif
	217
86271b3f	218	#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
451e8241 DW	219	#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
	220	#else
	221	#define BOOT_TARGET_DEVICES_PXE(func)
	222	#endif
	223
	224	#ifdef CONFIG_CMD_MMC
	225	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
	226	#else
	227	#define BOOT_TARGET_DEVICES_MMC(func)
	228	#endif
	229
	230	#define BOOT_TARGET_DEVICES(func) \
	231	BOOT_TARGET_DEVICES_MMC(func) \
	232	BOOT_TARGET_DEVICES_PXE(func) \
1c7fa793	233	BOOT_TARGET_DEVICES_DHCP(func)
451e8241 DW	234
	235	#include <config_distro_bootcmd.h>
	236
	237	#ifndef CONFIG_EXTRA_ENV_SETTINGS
	238	#define CONFIG_EXTRA_ENV_SETTINGS \
	239	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	240	"bootm_size=0xa000000\0" \
	241	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	242	"fdt_addr_r=0x02000000\0" \
	243	"scriptaddr=0x02100000\0" \
	244	"pxefile_addr_r=0x02200000\0" \
	245	"ramdisk_addr_r=0x02300000\0" \
4b2e32ef	246	"socfpga_legacy_reset_compat=1\0" \
451e8241 DW	247	BOOTENV
	248
	249	#endif
	250	#endif
	251
48275c96	252	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */