[J-u-boot.git] / include / configs / imgtec_xilfpga.h

/*
 * Copyright (C) 2016, Imagination Technologies Ltd.
 *
 * Zubair Lutfullah Kakakhel <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Imagination Technologies Ltd. MIPSfpga
 */

#ifndef __XILFPGA_CONFIG_H
#define __XILFPGA_CONFIG_H

/* BootROM + MIG is pretty smart. DDR and Cache initialized */
#define CONFIG_SKIP_LOWLEVEL_INIT

/*--------------------------------------------
 * CPU configuration
 */
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ	50000000

/* Cache Configuration */
#define CONFIG_SYS_MIPS_CACHE_MODE	CONF_CM_CACHABLE_NONCOHERENT

/*----------------------------------------------------------------------
 * Memory Layout
 */

/* SDRAM Configuration (for final code, data, stack, heap) */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 Mbytes */
#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)

#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_LOAD_ADDR		0x80500000 /* default load address */

/*----------------------------------------------------------------------
 * Commands
 */

/*------------------------------------------------------------
 * Console Configuration
 */
#define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size   */

/* -------------------------------------------------
 * Environment
 */
#define CONFIG_ENV_SIZE		0x4000

/* ---------------------------------------------------------------------
 * Board boot configuration
 */
#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

#endif	/* __XILFPGA_CONFIG_H */
Commit	Line	Data
ebf2b9e3 ZLK	1	/*
	2	* Copyright (C) 2016, Imagination Technologies Ltd.
	3	*
	4	* Zubair Lutfullah Kakakhel <[email protected]>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*
	8	* Imagination Technologies Ltd. MIPSfpga
	9	*/
	10
	11	#ifndef __XILFPGA_CONFIG_H
	12	#define __XILFPGA_CONFIG_H
	13
	14	/* BootROM + MIG is pretty smart. DDR and Cache initialized */
	15	#define CONFIG_SKIP_LOWLEVEL_INIT
	16
	17	/*--------------------------------------------
	18	* CPU configuration
	19	*/
	20	/* CPU Timer rate */
	21	#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
	22
	23	/* Cache Configuration */
	24	#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
	25
	26	/*----------------------------------------------------------------------
	27	* Memory Layout
	28	*/
	29
	30	/* SDRAM Configuration (for final code, data, stack, heap) */
	31	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	32	#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
	33	#define CONFIG_SYS_INIT_SP_ADDR \
	34	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
	35
	36	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	37	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	38	#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
	39
	40	/*----------------------------------------------------------------------
	41	* Commands
	42	*/
ebf2b9e3	43
ebf2b9e3 ZLK	44	/*------------------------------------------------------------
	45	* Console Configuration
	46	*/
	47	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
ebf2b9e3 ZLK	48
	49	/* -------------------------------------------------
	50	* Environment
	51	*/
ebf2b9e3 ZLK	52	#define CONFIG_ENV_SIZE 0x4000
	53
	54	/* ---------------------------------------------------------------------
	55	* Board boot configuration
	56	*/
	57	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	58
	59	#endif /* __XILFPGA_CONFIG_H */