[J-u-boot.git] / drivers / fpga / zynqpl.c

/*
 * (C) Copyright 2012-2013, Xilinx, Michal Simek
 *
 * (C) Copyright 2012
 * Joe Hershberger <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <console.h>
#include <asm/io.h>
#include <fs.h>
#include <zynqpl.h>
#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>

#define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK	0x00001000
#define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
#define DEVCFG_ISR_RX_FIFO_OV		0x00040000
#define DEVCFG_ISR_DMA_DONE		0x00002000
#define DEVCFG_ISR_PCFG_DONE		0x00000004
#define DEVCFG_STATUS_DMA_CMD_Q_F	0x80000000
#define DEVCFG_STATUS_DMA_CMD_Q_E	0x40000000
#define DEVCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000
#define DEVCFG_STATUS_PCFG_INIT		0x00000010
#define DEVCFG_MCTRL_PCAP_LPBK		0x00000010
#define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001

#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
#endif

#ifndef CONFIG_SYS_FPGA_PROG_TIME
#define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
#endif

#define DUMMY_WORD	0xffffffff

/* Xilinx binary format header */
static const u32 bin_format[] = {
	DUMMY_WORD, /* Dummy words */
	DUMMY_WORD,
	DUMMY_WORD,
	DUMMY_WORD,
	DUMMY_WORD,
	DUMMY_WORD,
	DUMMY_WORD,
	DUMMY_WORD,
	0x000000bb, /* Sync word */
	0x11220044, /* Sync word */
	DUMMY_WORD,
	DUMMY_WORD,
	0xaa995566, /* Sync word */
};

#define SWAP_NO		1
#define SWAP_DONE	2

/*
 * Load the whole word from unaligned buffer
 * Keep in your mind that it is byte loading on little-endian system
 */
static u32 load_word(const void *buf, u32 swap)
{
	u32 word = 0;
	u8 *bitc = (u8 *)buf;
	int p;

	if (swap == SWAP_NO) {
		for (p = 0; p < 4; p++) {
			word <<= 8;
			word |= bitc[p];
		}
	} else {
		for (p = 3; p >= 0; p--) {
			word <<= 8;
			word |= bitc[p];
		}
	}

	return word;
}

static u32 check_header(const void *buf)
{
	u32 i, pattern;
	int swap = SWAP_NO;
	u32 *test = (u32 *)buf;

	debug("%s: Let's check bitstream header\n", __func__);

	/* Checking that passing bin is not a bitstream */
	for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
		pattern = load_word(&test[i], swap);

		/*
		 * Bitstreams in binary format are swapped
		 * compare to regular bistream.
		 * Do not swap dummy word but if swap is done assume
		 * that parsing buffer is binary format
		 */
		if ((__swab32(pattern) != DUMMY_WORD) &&
		    (__swab32(pattern) == bin_format[i])) {
			pattern = __swab32(pattern);
			swap = SWAP_DONE;
			debug("%s: data swapped - let's swap\n", __func__);
		}

		debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
		      (u32)&test[i], pattern, bin_format[i]);
		if (pattern != bin_format[i]) {
			debug("%s: Bitstream is not recognized\n", __func__);
			return 0;
		}
	}
	debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
	      (u32)buf, swap == SWAP_NO ? "without" : "with");

	return swap;
}

static void *check_data(u8 *buf, size_t bsize, u32 *swap)
{
	u32 word, p = 0; /* possition */

	/* Because buf doesn't need to be aligned let's read it by chars */
	for (p = 0; p < bsize; p++) {
		word = load_word(&buf[p], SWAP_NO);
		debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);

		/* Find the first bitstream dummy word */
		if (word == DUMMY_WORD) {
			debug("%s: Found dummy word at position %x/%x\n",
			      __func__, p, (u32)&buf[p]);
			*swap = check_header(&buf[p]);
			if (*swap) {
				/* FIXME add full bitstream checking here */
				return &buf[p];
			}
		}
		/* Loop can be huge - support CTRL + C */
		if (ctrlc())
			return NULL;
	}
	return NULL;
}

static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
{
	unsigned long ts;
	u32 isr_status;

	/* Set up the transfer */
	writel((u32)srcbuf, &devcfg_base->dma_src_addr);
	writel(dstbuf, &devcfg_base->dma_dst_addr);
	writel(srclen, &devcfg_base->dma_src_len);
	writel(dstlen, &devcfg_base->dma_dst_len);

	isr_status = readl(&devcfg_base->int_sts);

	/* Polling the PCAP_INIT status for Set */
	ts = get_timer(0);
	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
		if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
			debug("%s: Error: isr = 0x%08X\n", __func__,
			      isr_status);
			debug("%s: Write count = 0x%08X\n", __func__,
			      readl(&devcfg_base->write_count));
			debug("%s: Read count = 0x%08X\n", __func__,
			      readl(&devcfg_base->read_count));

			return FPGA_FAIL;
		}
		if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
			printf("%s: Timeout wait for DMA to complete\n",
			       __func__);
			return FPGA_FAIL;
		}
		isr_status = readl(&devcfg_base->int_sts);
	}

	debug("%s: DMA transfer is done\n", __func__);

	/* Clear out the DMA status */
	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);

	return FPGA_SUCCESS;
}

static int zynq_dma_xfer_init(bitstream_type bstype)
{
	u32 status, control, isr_status;
	unsigned long ts;

	/* Clear loopback bit */
	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);

	if (bstype != BIT_PARTIAL) {
		zynq_slcr_devcfg_disable();

		/* Setting PCFG_PROG_B signal to high */
		control = readl(&devcfg_base->ctrl);
		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);

		/*
		 * Delay is required if AES efuse is selected as
		 * key source.
		 */
		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
			mdelay(5);

		/* Setting PCFG_PROG_B signal to low */
		writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);

		/*
		 * Delay is required if AES efuse is selected as
		 * key source.
		 */
		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
			mdelay(5);

		/* Polling the PCAP_INIT status for Reset */
		ts = get_timer(0);
		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
				printf("%s: Timeout wait for INIT to clear\n",
				       __func__);
				return FPGA_FAIL;
			}
		}

		/* Setting PCFG_PROG_B signal to high */
		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);

		/* Polling the PCAP_INIT status for Set */
		ts = get_timer(0);
		while (!(readl(&devcfg_base->status) &
			DEVCFG_STATUS_PCFG_INIT)) {
			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
				printf("%s: Timeout wait for INIT to set\n",
				       __func__);
				return FPGA_FAIL;
			}
		}
	}

	isr_status = readl(&devcfg_base->int_sts);

	/* Clear it all, so if Boot ROM comes back, it can proceed */
	writel(0xFFFFFFFF, &devcfg_base->int_sts);

	if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
		debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);

		/* If RX FIFO overflow, need to flush RX FIFO first */
		if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
			writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
			writel(0xFFFFFFFF, &devcfg_base->int_sts);
		}
		return FPGA_FAIL;
	}

	status = readl(&devcfg_base->status);

	debug("%s: Status = 0x%08X\n", __func__, status);

	if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
		debug("%s: Error: device busy\n", __func__);
		return FPGA_FAIL;
	}

	debug("%s: Device ready\n", __func__);

	if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
		if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
			/* Error state, transfer cannot occur */
			debug("%s: ISR indicates error\n", __func__);
			return FPGA_FAIL;
		} else {
			/* Clear out the status */
			writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
		}
	}

	if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
		/* Clear the count of completed DMA transfers */
		writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
	}

	return FPGA_SUCCESS;
}

static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
{
	u32 *new_buf;
	u32 i;

	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
		new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);

		/*
		 * This might be dangerous but permits to flash if
		 * ARCH_DMA_MINALIGN is greater than header size
		 */
		if (new_buf > buf) {
			debug("%s: Aligned buffer is after buffer start\n",
			      __func__);
			new_buf -= ARCH_DMA_MINALIGN;
		}
		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
		       (u32)buf, (u32)new_buf, swap);

		for (i = 0; i < (len/4); i++)
			new_buf[i] = load_word(&buf[i], swap);

		buf = new_buf;
	} else if (swap != SWAP_DONE) {
		/* For bitstream which are aligned */
		u32 *new_buf = (u32 *)buf;

		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
		       swap);

		for (i = 0; i < (len/4); i++)
			new_buf[i] = load_word(&buf[i], swap);
	}

	return buf;
}

static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
				   size_t bsize, u32 blocksize, u32 *swap,
				   bitstream_type *bstype)
{
	u32 *buf_start;
	u32 diff;

	buf_start = check_data((u8 *)buf, blocksize, swap);

	if (!buf_start)
		return FPGA_FAIL;

	/* Check if data is postpone from start */
	diff = (u32)buf_start - (u32)buf;
	if (diff) {
		printf("%s: Bitstream is not validated yet (diff %x)\n",
		       __func__, diff);
		return FPGA_FAIL;
	}

	if ((u32)buf < SZ_1M) {
		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
		       __func__, (u32)buf);
		return FPGA_FAIL;
	}

	if (zynq_dma_xfer_init(*bstype))
		return FPGA_FAIL;

	return 0;
}

static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
		     bitstream_type bstype)
{
	unsigned long ts; /* Timestamp */
	u32 isr_status, swap;

	/*
	 * send bsize inplace of blocksize as it was not a bitstream
	 * in chunks
	 */
	if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
				    &bstype))
		return FPGA_FAIL;

	buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);

	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
	debug("%s: Size = %zu\n", __func__, bsize);

	/* flush(clean & invalidate) d-cache range buf */
	flush_dcache_range((u32)buf, (u32)buf +
			   roundup(bsize, ARCH_DMA_MINALIGN));

	if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
		return FPGA_FAIL;

	isr_status = readl(&devcfg_base->int_sts);
	/* Check FPGA configuration completion */
	ts = get_timer(0);
	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
			printf("%s: Timeout wait for FPGA to config\n",
			       __func__);
			return FPGA_FAIL;
		}
		isr_status = readl(&devcfg_base->int_sts);
	}

	debug("%s: FPGA config done\n", __func__);

	if (bstype != BIT_PARTIAL)
		zynq_slcr_devcfg_enable();

	return FPGA_SUCCESS;
}

#if defined(CONFIG_CMD_FPGA_LOADFS)
static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
		       fpga_fs_info *fsinfo)
{
	unsigned long ts; /* Timestamp */
	u32 isr_status, swap;
	u32 partialbit = 0;
	loff_t blocksize, actread;
	loff_t pos = 0;
	int fstype;
	char *interface, *dev_part, *filename;

	blocksize = fsinfo->blocksize;
	interface = fsinfo->interface;
	dev_part = fsinfo->dev_part;
	filename = fsinfo->filename;
	fstype = fsinfo->fstype;

	if (fs_set_blk_dev(interface, dev_part, fstype))
		return FPGA_FAIL;

	if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
		return FPGA_FAIL;

	if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
				    &partialbit))
		return FPGA_FAIL;

	dcache_disable();

	do {
		buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);

		if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
				      0xffffffff, 0))
			return FPGA_FAIL;

		bsize -= blocksize;
		pos   += blocksize;

		if (fs_set_blk_dev(interface, dev_part, fstype))
			return FPGA_FAIL;

		if (bsize > blocksize) {
			if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
				return FPGA_FAIL;
		} else {
			if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
				return FPGA_FAIL;
		}
	} while (bsize > blocksize);

	buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);

	if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
		return FPGA_FAIL;

	dcache_enable();

	isr_status = readl(&devcfg_base->int_sts);

	/* Check FPGA configuration completion */
	ts = get_timer(0);
	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
			printf("%s: Timeout wait for FPGA to config\n",
			       __func__);
			return FPGA_FAIL;
		}
		isr_status = readl(&devcfg_base->int_sts);
	}

	debug("%s: FPGA config done\n", __func__);

	if (!partialbit)
		zynq_slcr_devcfg_enable();

	return FPGA_SUCCESS;
}
#endif

struct xilinx_fpga_op zynq_op = {
	.load = zynq_load,
#if defined(CONFIG_CMD_FPGA_LOADFS)
	.loadfs = zynq_loadfs,
#endif
};
Commit	Line	Data
d5dae85f MS	1	/*
	2	* (C) Copyright 2012-2013, Xilinx, Michal Simek
	3	*
	4	* (C) Copyright 2012
	5	* Joe Hershberger <[email protected]>
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
d5dae85f MS	8	*/
	9
	10	#include <common.h>
24b852a7	11	#include <console.h>
d5dae85f	12	#include <asm/io.h>
1a897668	13	#include <fs.h>
d5dae85f	14	#include <zynqpl.h>
1ace4022	15	#include <linux/sizes.h>
d5dae85f MS	16	#include <asm/arch/hardware.h>
	17	#include <asm/arch/sys_proto.h>
	18
	19	#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
71723aae	20	#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
d5dae85f MS	21	#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
	22	#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
	23	#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
	24	#define DEVCFG_ISR_DMA_DONE 0x00002000
	25	#define DEVCFG_ISR_PCFG_DONE 0x00000004
	26	#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
	27	#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
	28	#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
	29	#define DEVCFG_STATUS_PCFG_INIT 0x00000010
5f93227c	30	#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
d5dae85f MS	31	#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
	32	#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
	33
	34	#ifndef CONFIG_SYS_FPGA_WAIT
	35	#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
	36	#endif
	37
	38	#ifndef CONFIG_SYS_FPGA_PROG_TIME
fd2b10b6	39	#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
d5dae85f MS	40	#endif
d5dae85f MS	41
d5dae85f MS	42	#define DUMMY_WORD 0xffffffff
	43
	44	/* Xilinx binary format header */
	45	static const u32 bin_format[] = {
	46	DUMMY_WORD, /* Dummy words */
	47	DUMMY_WORD,
	48	DUMMY_WORD,
	49	DUMMY_WORD,
	50	DUMMY_WORD,
	51	DUMMY_WORD,
	52	DUMMY_WORD,
	53	DUMMY_WORD,
	54	0x000000bb, /* Sync word */
	55	0x11220044, /* Sync word */
	56	DUMMY_WORD,
	57	DUMMY_WORD,
	58	0xaa995566, /* Sync word */
	59	};
	60
	61	#define SWAP_NO 1
	62	#define SWAP_DONE 2
	63
	64	/*
	65	* Load the whole word from unaligned buffer
	66	* Keep in your mind that it is byte loading on little-endian system
	67	*/
	68	static u32 load_word(const void *buf, u32 swap)
	69	{
	70	u32 word = 0;
	71	u8 bitc = (u8 )buf;
	72	int p;
	73
	74	if (swap == SWAP_NO) {
	75	for (p = 0; p < 4; p++) {
	76	word <<= 8;
	77	word \|= bitc[p];
	78	}
	79	} else {
	80	for (p = 3; p >= 0; p--) {
	81	word <<= 8;
	82	word \|= bitc[p];
	83	}
	84	}
	85
	86	return word;
	87	}
	88
	89	static u32 check_header(const void *buf)
	90	{
	91	u32 i, pattern;
	92	int swap = SWAP_NO;
	93	u32 test = (u32 )buf;
	94
	95	debug("%s: Let's check bitstream header\n", __func__);
	96
	97	/* Checking that passing bin is not a bitstream */
	98	for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
	99	pattern = load_word(&test[i], swap);
	100
	101	/*
	102	* Bitstreams in binary format are swapped
	103	* compare to regular bistream.
	104	* Do not swap dummy word but if swap is done assume
	105	* that parsing buffer is binary format
106	*/
107	if ((__swab32(pattern) != DUMMY_WORD) &&
108	(__swab32(pattern) == bin_format[i])) {
109	pattern = __swab32(pattern);
110	swap = SWAP_DONE;
111	debug("%s: data swapped - let's swap\n", __func__);
112	}
113
114	debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
115	(u32)&test[i], pattern, bin_format[i]);
116	if (pattern != bin_format[i]) {
117	debug("%s: Bitstream is not recognized\n", __func__);
118	return 0;
119	}
120	}
121	debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
122	(u32)buf, swap == SWAP_NO ? "without" : "with");
123
124	return swap;
125	}
126
127	static void check_data(u8 buf, size_t bsize, u32 *swap)
128	{
129	u32 word, p = 0; /* possition */
130
131	/* Because buf doesn't need to be aligned let's read it by chars */
132	for (p = 0; p < bsize; p++) {
133	word = load_word(&buf[p], SWAP_NO);
134	debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
135
136	/* Find the first bitstream dummy word */
137	if (word == DUMMY_WORD) {
138	debug("%s: Found dummy word at position %x/%x\n",
139	__func__, p, (u32)&buf[p]);
140	*swap = check_header(&buf[p]);
141	if (*swap) {
142	/* FIXME add full bitstream checking here */
143	return &buf[p];
144	}
145	}
146	/* Loop can be huge - support CTRL + C */
147	if (ctrlc())
42a74a08	148	return NULL;
d5dae85f	149	}
42a74a08	150	return NULL;
d5dae85f MS	151	}
d5dae85f MS	152
a0735a34	153	static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
d5dae85f	154	{
a0735a34 SDPP	155	unsigned long ts;
a0735a34 SDPP	156	u32 isr_status;
d5dae85f	157
a0735a34 SDPP	158	/* Set up the transfer */
	159	writel((u32)srcbuf, &devcfg_base->dma_src_addr);
	160	writel(dstbuf, &devcfg_base->dma_dst_addr);
	161	writel(srclen, &devcfg_base->dma_src_len);
	162	writel(dstlen, &devcfg_base->dma_dst_len);
d5dae85f	163
a0735a34	164	isr_status = readl(&devcfg_base->int_sts);
b129e8cf	165
a0735a34 SDPP	166	/* Polling the PCAP_INIT status for Set */
	167	ts = get_timer(0);
	168	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
	169	if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
	170	debug("%s: Error: isr = 0x%08X\n", __func__,
	171	isr_status);
	172	debug("%s: Write count = 0x%08X\n", __func__,
	173	readl(&devcfg_base->write_count));
	174	debug("%s: Read count = 0x%08X\n", __func__,
	175	readl(&devcfg_base->read_count));
d5dae85f	176
a0735a34	177	return FPGA_FAIL;
c83a35f6	178	}
a0735a34 SDPP	179	if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
	180	printf("%s: Timeout wait for DMA to complete\n",
	181	__func__);
	182	return FPGA_FAIL;
	183	}
	184	isr_status = readl(&devcfg_base->int_sts);
	185	}
c83a35f6	186
a0735a34	187	debug("%s: DMA transfer is done\n", __func__);
d5dae85f	188
a0735a34 SDPP	189	/* Clear out the DMA status */
a0735a34 SDPP	190	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
d5dae85f	191
a0735a34 SDPP	192	return FPGA_SUCCESS;
a0735a34 SDPP	193	}
d5dae85f	194
5b815c9c	195	static int zynq_dma_xfer_init(bitstream_type bstype)
a0735a34 SDPP	196	{
	197	u32 status, control, isr_status;
	198	unsigned long ts;
d5dae85f	199
5f93227c SB	200	/* Clear loopback bit */
	201	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
	202
5b815c9c	203	if (bstype != BIT_PARTIAL) {
d5dae85f MS	204	zynq_slcr_devcfg_disable();
	205
	206	/* Setting PCFG_PROG_B signal to high */
	207	control = readl(&devcfg_base->ctrl);
	208	writel(control \| DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
71723aae SDPP	209
	210	/*
	211	* Delay is required if AES efuse is selected as
	212	* key source.
	213	*/
	214	if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
	215	mdelay(5);
	216
d5dae85f MS	217	/* Setting PCFG_PROG_B signal to low */
	218	writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
	219
71723aae SDPP	220	/*
	221	* Delay is required if AES efuse is selected as
	222	* key source.
	223	*/
	224	if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
	225	mdelay(5);
	226
d5dae85f MS	227	/* Polling the PCAP_INIT status for Reset */
	228	ts = get_timer(0);
	229	while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
	230	if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
	231	printf("%s: Timeout wait for INIT to clear\n",
	232	__func__);
	233	return FPGA_FAIL;
	234	}
	235	}
	236
	237	/* Setting PCFG_PROG_B signal to high */
	238	writel(control \| DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
	239
	240	/* Polling the PCAP_INIT status for Set */
	241	ts = get_timer(0);
	242	while (!(readl(&devcfg_base->status) &
	243	DEVCFG_STATUS_PCFG_INIT)) {
	244	if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
	245	printf("%s: Timeout wait for INIT to set\n",
	246	__func__);
	247	return FPGA_FAIL;
	248	}
	249	}
	250	}
	251
	252	isr_status = readl(&devcfg_base->int_sts);
	253
	254	/* Clear it all, so if Boot ROM comes back, it can proceed */
	255	writel(0xFFFFFFFF, &devcfg_base->int_sts);
	256
	257	if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
	258	debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
	259
	260	/* If RX FIFO overflow, need to flush RX FIFO first */
	261	if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
	262	writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
	263	writel(0xFFFFFFFF, &devcfg_base->int_sts);
	264	}
	265	return FPGA_FAIL;
	266	}
	267
	268	status = readl(&devcfg_base->status);
	269
	270	debug("%s: Status = 0x%08X\n", __func__, status);
	271
	272	if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
	273	debug("%s: Error: device busy\n", __func__);
	274	return FPGA_FAIL;
	275	}
	276
	277	debug("%s: Device ready\n", __func__);
	278
	279	if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
	280	if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
	281	/* Error state, transfer cannot occur */
	282	debug("%s: ISR indicates error\n", __func__);
	283	return FPGA_FAIL;
	284	} else {
	285	/* Clear out the status */
	286	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
	287	}
	288	}
	289
	290	if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
291	/* Clear the count of completed DMA transfers */
292	writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
293	}
294
a0735a34 SDPP	295	return FPGA_SUCCESS;
	296	}
	297
	298	static u32 zynq_align_dma_buffer(u32 buf, u32 len, u32 swap)
	299	{
	300	u32 *new_buf;
	301	u32 i;
	302
	303	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
	304	new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
	305
	306	/*
	307	* This might be dangerous but permits to flash if
	308	* ARCH_DMA_MINALIGN is greater than header size
	309	*/
	310	if (new_buf > buf) {
	311	debug("%s: Aligned buffer is after buffer start\n",
	312	__func__);
	313	new_buf -= ARCH_DMA_MINALIGN;
	314	}
	315	printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
	316	(u32)buf, (u32)new_buf, swap);
	317
	318	for (i = 0; i < (len/4); i++)
	319	new_buf[i] = load_word(&buf[i], swap);
	320
	321	buf = new_buf;
	322	} else if (swap != SWAP_DONE) {
	323	/* For bitstream which are aligned */
	324	u32 new_buf = (u32 )buf;
	325
	326	printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
	327	swap);
	328
	329	for (i = 0; i < (len/4); i++)
	330	new_buf[i] = load_word(&buf[i], swap);
	331	}
	332
	333	return buf;
	334	}
	335
31081859 SDPP	336	static int zynq_validate_bitstream(xilinx_desc desc, const void buf,
31081859 SDPP	337	size_t bsize, u32 blocksize, u32 *swap,
5b815c9c	338	bitstream_type *bstype)
a0735a34	339	{
a0735a34	340	u32 *buf_start;
31081859	341	u32 diff;
a0735a34	342
31081859	343	buf_start = check_data((u8 *)buf, blocksize, swap);
a0735a34	344
a0735a34 SDPP	345	if (!buf_start)
	346	return FPGA_FAIL;
	347
	348	/* Check if data is postpone from start */
	349	diff = (u32)buf_start - (u32)buf;
	350	if (diff) {
	351	printf("%s: Bitstream is not validated yet (diff %x)\n",
	352	__func__, diff);
	353	return FPGA_FAIL;
	354	}
	355
	356	if ((u32)buf < SZ_1M) {
	357	printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
	358	__func__, (u32)buf);
	359	return FPGA_FAIL;
	360	}
	361
5b815c9c	362	if (zynq_dma_xfer_init(*bstype))
31081859 SDPP	363	return FPGA_FAIL;
	364
	365	return 0;
	366	}
	367
7a78bd26 MS	368	static int zynq_load(xilinx_desc desc, const void buf, size_t bsize,
7a78bd26 MS	369	bitstream_type bstype)
31081859 SDPP	370	{
31081859 SDPP	371	unsigned long ts; /* Timestamp */
31081859 SDPP	372	u32 isr_status, swap;
	373
	374	/*
	375	* send bsize inplace of blocksize as it was not a bitstream
	376	* in chunks
	377	*/
	378	if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
5b815c9c	379	&bstype))
a0735a34 SDPP	380	return FPGA_FAIL;
	381
	382	buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
	383
d5dae85f MS	384	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
	385	debug("%s: Size = %zu\n", __func__, bsize);
	386
ec4b73f0 JT	387	/* flush(clean & invalidate) d-cache range buf */
	388	flush_dcache_range((u32)buf, (u32)buf +
	389	roundup(bsize, ARCH_DMA_MINALIGN));
	390
a0735a34 SDPP	391	if (zynq_dma_transfer((u32)buf \| 1, bsize >> 2, 0xffffffff, 0))
a0735a34 SDPP	392	return FPGA_FAIL;
d5dae85f MS	393
d5dae85f MS	394	isr_status = readl(&devcfg_base->int_sts);
d5dae85f MS	395	/* Check FPGA configuration completion */
	396	ts = get_timer(0);
	397	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
	398	if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
	399	printf("%s: Timeout wait for FPGA to config\n",
	400	__func__);
	401	return FPGA_FAIL;
	402	}
	403	isr_status = readl(&devcfg_base->int_sts);
	404	}
	405
	406	debug("%s: FPGA config done\n", __func__);
	407
5b815c9c	408	if (bstype != BIT_PARTIAL)
d5dae85f MS	409	zynq_slcr_devcfg_enable();
	410
	411	return FPGA_SUCCESS;
	412	}
	413
1a897668 SDPP	414	#if defined(CONFIG_CMD_FPGA_LOADFS)
	415	static int zynq_loadfs(xilinx_desc desc, const void buf, size_t bsize,
	416	fpga_fs_info *fsinfo)
	417	{
	418	unsigned long ts; /* Timestamp */
	419	u32 isr_status, swap;
	420	u32 partialbit = 0;
d455d878 SR	421	loff_t blocksize, actread;
d455d878 SR	422	loff_t pos = 0;
1a897668 SDPP	423	int fstype;
	424	char interface, dev_part, *filename;
	425
	426	blocksize = fsinfo->blocksize;
	427	interface = fsinfo->interface;
	428	dev_part = fsinfo->dev_part;
	429	filename = fsinfo->filename;
	430	fstype = fsinfo->fstype;
	431
	432	if (fs_set_blk_dev(interface, dev_part, fstype))
	433	return FPGA_FAIL;
	434
d455d878	435	if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
1a897668 SDPP	436	return FPGA_FAIL;
	437
	438	if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
	439	&partialbit))
	440	return FPGA_FAIL;
	441
	442	dcache_disable();
	443
	444	do {
	445	buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
	446
	447	if (zynq_dma_transfer((u32)buf \| 1, blocksize >> 2,
	448	0xffffffff, 0))
	449	return FPGA_FAIL;
	450
	451	bsize -= blocksize;
	452	pos += blocksize;
	453
	454	if (fs_set_blk_dev(interface, dev_part, fstype))
	455	return FPGA_FAIL;
	456
	457	if (bsize > blocksize) {
d455d878	458	if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
1a897668 SDPP	459	return FPGA_FAIL;
1a897668 SDPP	460	} else {
d455d878	461	if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
1a897668 SDPP	462	return FPGA_FAIL;
	463	}
	464	} while (bsize > blocksize);
	465
	466	buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
	467
	468	if (zynq_dma_transfer((u32)buf \| 1, bsize >> 2, 0xffffffff, 0))
	469	return FPGA_FAIL;
	470
	471	dcache_enable();
	472
	473	isr_status = readl(&devcfg_base->int_sts);
	474
	475	/* Check FPGA configuration completion */
	476	ts = get_timer(0);
	477	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
	478	if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
	479	printf("%s: Timeout wait for FPGA to config\n",
	480	__func__);
	481	return FPGA_FAIL;
	482	}
	483	isr_status = readl(&devcfg_base->int_sts);
	484	}
	485
	486	debug("%s: FPGA config done\n", __func__);
	487
	488	if (!partialbit)
	489	zynq_slcr_devcfg_enable();
	490
	491	return FPGA_SUCCESS;
	492	}
	493	#endif
	494
14cfc4f3 MS	495	struct xilinx_fpga_op zynq_op = {
14cfc4f3 MS	496	.load = zynq_load,
1a897668 SDPP	497	#if defined(CONFIG_CMD_FPGA_LOADFS)
	498	.loadfs = zynq_loadfs,
	499	#endif
14cfc4f3	500	};