[J-u-boot.git] / drivers / net / dc2114x.c

// SPDX-License-Identifier: GPL-2.0+

#include <common.h>
#include <env.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <pci.h>

#undef DEBUG_SROM
#undef DEBUG_SROM2

#undef UPDATE_SROM

/* PCI Registers.
 */
#define PCI_CFDA_PSM		0x43

#define CFRV_RN		0x000000f0	/* Revision Number */

#define WAKEUP		0x00		/* Power Saving Wakeup */
#define SLEEP		0x80		/* Power Saving Sleep Mode */

#define DC2114x_BRK	0x0020		/* CFRV break between DC21142 & DC21143 */

/* Ethernet chip registers.
 */
#define DE4X5_BMR	0x000		/* Bus Mode Register */
#define DE4X5_TPD	0x008		/* Transmit Poll Demand Reg */
#define DE4X5_RRBA	0x018		/* RX Ring Base Address Reg */
#define DE4X5_TRBA	0x020		/* TX Ring Base Address Reg */
#define DE4X5_STS	0x028		/* Status Register */
#define DE4X5_OMR	0x030		/* Operation Mode Register */
#define DE4X5_SICR	0x068		/* SIA Connectivity Register */
#define DE4X5_APROM	0x048		/* Ethernet Address PROM */

/* Register bits.
 */
#define BMR_SWR		0x00000001	/* Software Reset */
#define STS_TS		0x00700000	/* Transmit Process State */
#define STS_RS		0x000e0000	/* Receive Process State */
#define OMR_ST		0x00002000	/* Start/Stop Transmission Command */
#define OMR_SR		0x00000002	/* Start/Stop Receive */
#define OMR_PS		0x00040000	/* Port Select */
#define OMR_SDP		0x02000000	/* SD Polarity - MUST BE ASSERTED */
#define OMR_PM		0x00000080	/* Pass All Multicast */

/* Descriptor bits.
 */
#define R_OWN		0x80000000	/* Own Bit */
#define RD_RER		0x02000000	/* Receive End Of Ring */
#define RD_LS		0x00000100	/* Last Descriptor */
#define RD_ES		0x00008000	/* Error Summary */
#define TD_TER		0x02000000	/* Transmit End Of Ring */
#define T_OWN		0x80000000	/* Own Bit */
#define TD_LS		0x40000000	/* Last Segment */
#define TD_FS		0x20000000	/* First Segment */
#define TD_ES		0x00008000	/* Error Summary */
#define TD_SET		0x08000000	/* Setup Packet */

/* The EEPROM commands include the alway-set leading bit. */
#define SROM_WRITE_CMD	5
#define SROM_READ_CMD	6
#define SROM_ERASE_CMD	7

#define SROM_HWADD	    0x0014	/* Hardware Address offset in SROM */
#define SROM_RD		0x00004000	/* Read from Boot ROM */
#define EE_DATA_WRITE	      0x04	/* EEPROM chip data in. */
#define EE_WRITE_0	    0x4801
#define EE_WRITE_1	    0x4805
#define EE_DATA_READ	      0x08	/* EEPROM chip data out. */
#define SROM_SR		0x00000800	/* Select Serial ROM when set */

#define DT_IN		0x00000004	/* Serial Data In */
#define DT_CLK		0x00000002	/* Serial ROM Clock */
#define DT_CS		0x00000001	/* Serial ROM Chip Select */

#define POLL_DEMAND	1

#define RESET_DE4X5(dev) {\
    int i;\
    i=INL(dev, DE4X5_BMR);\
    udelay(1000);\
    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
    udelay(1000);\
    OUTL(dev, i, DE4X5_BMR);\
    udelay(1000);\
    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
    udelay(1000);\
}

#define START_DE4X5(dev) {\
    s32 omr; \
    omr = INL(dev, DE4X5_OMR);\
    omr |= OMR_ST | OMR_SR;\
    OUTL(dev, omr, DE4X5_OMR);		/* Enable the TX and/or RX */\
}

#define STOP_DE4X5(dev) {\
    s32 omr; \
    omr = INL(dev, DE4X5_OMR);\
    omr &= ~(OMR_ST|OMR_SR);\
    OUTL(dev, omr, DE4X5_OMR);		/* Disable the TX and/or RX */ \
}

#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1			/* Number of TX descriptors   */
#define RX_BUFF_SZ  PKTSIZE_ALIGN

#define TOUT_LOOP   1000000

#define SETUP_FRAME_LEN 192

struct de4x5_desc {
	volatile s32 status;
	u32 des1;
	u32 buf;
	u32 next;
};

static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring         */
static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring         */
static int rx_new;                             /* RX descriptor ring pointer */
static int tx_new;                             /* TX descriptor ring pointer */

static char rxRingSize;
static char txRingSize;

static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);
static int   getfrom_srom(struct eth_device* dev, u_long addr);
static int   do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
static int   do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
#ifdef UPDATE_SROM
static int   write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
static void  update_srom(struct eth_device *dev, bd_t *bis);
#endif
static int   read_srom(struct eth_device *dev, u_long ioaddr, int index);
static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
static void  send_setup_frame(struct eth_device* dev, bd_t * bis);

static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
static int   dc21x4x_send(struct eth_device *dev, void *packet, int length);
static int   dc21x4x_recv(struct eth_device* dev);
static void  dc21x4x_halt(struct eth_device* dev);

#if defined(CONFIG_E500)
#define phys_to_bus(a) (a)
#else
#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif

static int INL(struct eth_device* dev, u_long addr)
{
	return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
}

static void OUTL(struct eth_device* dev, int command, u_long addr)
{
	*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
}

static struct pci_device_id supported[] = {
	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
	{ }
};

int dc21x4x_initialize(bd_t *bis)
{
	struct eth_device *dev;
	unsigned short status;
	unsigned char timer;
	unsigned int iobase;
	int card_number = 0;
	pci_dev_t devbusfn;
	unsigned int cfrv;
	int idx = 0;

	while (1) {
		devbusfn = pci_find_devices(supported, idx++);
		if (devbusfn == -1)
			break;

		/* Get the chip configuration revision register. */
		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);

		if ((cfrv & CFRV_RN) < DC2114x_BRK) {
			printf("Error: The chip is not DC21143.\n");
			continue;
		}

		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
		status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
		pci_write_config_word(devbusfn, PCI_COMMAND, status);

		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
		if (!(status & PCI_COMMAND_MEMORY)) {
			printf("Error: Can not enable MEMORY access.\n");
			continue;
		}

		if (!(status & PCI_COMMAND_MASTER)) {
			printf("Error: Can not enable Bus Mastering.\n");
			continue;
		}

		/* Check the latency timer for values >= 0x60. */
		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);

		if (timer < 0x60) {
			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
					      0x60);
		}

		/* read BAR for memory space access */
		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
		debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);

		dev = (struct eth_device *)malloc(sizeof(*dev));
		if (!dev) {
			printf("Can not allocalte memory of dc21x4x\n");
			break;
		}

		memset(dev, 0, sizeof(*dev));

		sprintf(dev->name, "dc21x4x#%d", card_number);

		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
		dev->priv = (void *)devbusfn;
		dev->init = dc21x4x_init;
		dev->halt = dc21x4x_halt;
		dev->send = dc21x4x_send;
		dev->recv = dc21x4x_recv;

		/* Ensure we're not sleeping. */
		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);

		udelay(10 * 1000);

		read_hw_addr(dev, bis);

		eth_register(dev);

		card_number++;
	}

	return card_number;
}

static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
{
	int i;
	int devbusfn = (int)dev->priv;

	/* Ensure we're not sleeping. */
	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);

	RESET_DE4X5(dev);

	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
		printf("Error: Cannot reset ethernet controller.\n");
		return -1;
	}

	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);

	for (i = 0; i < NUM_RX_DESC; i++) {
		rx_ring[i].status = cpu_to_le32(R_OWN);
		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
		rx_ring[i].buf =
			cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
		rx_ring[i].next = 0;
	}

	for (i = 0; i < NUM_TX_DESC; i++) {
		tx_ring[i].status = 0;
		tx_ring[i].des1 = 0;
		tx_ring[i].buf = 0;
		tx_ring[i].next = 0;
	}

	rxRingSize = NUM_RX_DESC;
	txRingSize = NUM_TX_DESC;

	/* Write the end of list marker to the descriptor lists. */
	rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);

	/* Tell the adapter where the TX/RX rings are located. */
	OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
	OUTL(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);

	START_DE4X5(dev);

	tx_new = 0;
	rx_new = 0;

	send_setup_frame(dev, bis);

	return 0;
}

static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
{
	int status = -1;
	int i;

	if (length <= 0) {
		printf("%s: bad packet size: %d\n", dev->name, length);
		goto done;
	}

	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i < TOUT_LOOP)
			continue;

		printf("%s: tx error buffer not ready\n", dev->name);
		goto done;
	}

	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
	tx_ring[tx_new].status = cpu_to_le32(T_OWN);

	OUTL(dev, POLL_DEMAND, DE4X5_TPD);

	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i < TOUT_LOOP)
			continue;

		printf(".%s: tx buffer not ready\n", dev->name);
		goto done;
	}

	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
		tx_ring[tx_new].status = 0x0;
		goto done;
	}

	status = length;

done:
	tx_new = (tx_new + 1) % NUM_TX_DESC;
	return status;
}

static int dc21x4x_recv(struct eth_device* dev)
{
	s32		status;
	int		length    = 0;

	for ( ; ; ) {
		status = (s32)le32_to_cpu(rx_ring[rx_new].status);

		if (status & R_OWN) {
			break;
		}

		if (status & RD_LS) {
			/* Valid frame status.
			 */
			if (status & RD_ES) {

				/* There was an error.
				 */
				printf("RX error status = 0x%08X\n", status);
			} else {
				/* A valid frame received.
				 */
				length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);

				/* Pass the packet up to the protocol
				 * layers.
				 */
				net_process_received_packet(
					net_rx_packets[rx_new], length - 4);
			}

			/* Change buffer ownership for this frame, back
			 * to the adapter.
			 */
			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
		}

		/* Update entry information.
		 */
		rx_new = (rx_new + 1) % rxRingSize;
	}

	return length;
}

static void dc21x4x_halt(struct eth_device* dev)
{
	int		devbusfn = (int) dev->priv;

	STOP_DE4X5(dev);
	OUTL(dev, 0, DE4X5_SICR);

	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
}

static void send_setup_frame(struct eth_device* dev, bd_t *bis)
{
	int		i;
	char	setup_frame[SETUP_FRAME_LEN];
	char	*pa = &setup_frame[0];

	memset(pa, 0xff, SETUP_FRAME_LEN);

	for (i = 0; i < ETH_ALEN; i++) {
		*(pa + (i & 1)) = dev->enetaddr[i];
		if (i & 0x01) {
			pa += 4;
		}
	}

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf("%s: tx error buffer not ready\n", dev->name);
			goto Done;
		}
	}

	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
	tx_ring[tx_new].status = cpu_to_le32(T_OWN);

	OUTL(dev, POLL_DEMAND, DE4X5_TPD);

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf("%s: tx buffer not ready\n", dev->name);
			goto Done;
		}
	}

	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
	}
	tx_new = (tx_new+1) % NUM_TX_DESC;

Done:
	return;
}

/* SROM Read and write routines. */
static void
sendto_srom(struct eth_device* dev, u_int command, u_long addr)
{
	OUTL(dev, command, addr);
	udelay(1);
}

static int
getfrom_srom(struct eth_device* dev, u_long addr)
{
	s32 tmp;

	tmp = INL(dev, addr);
	udelay(1);

	return tmp;
}

/* Note: this routine returns extra data bits for size detection. */
static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
{
	int i;
	unsigned retval = 0;
	int read_cmd = location | (SROM_READ_CMD << addr_len);

	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);

#ifdef DEBUG_SROM
	printf(" EEPROM read at %d ", location);
#endif

	/* Shift the read command bits out. */
	for (i = 4 + addr_len; i >= 0; i--) {
		short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
		udelay(10);
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
		udelay(10);
#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
	}

	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);

#ifdef DEBUG_SROM2
	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
#endif

	for (i = 16; i > 0; i--) {
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
		udelay(10);
#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
		udelay(10);
	}

	/* Terminate the EEPROM access. */
	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);

#ifdef DEBUG_SROM2
	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
#endif

	return retval;
}

/*
 * This executes a generic EEPROM command, typically a write or write
 * enable. It returns the data output from the EEPROM, and thus may
 * also be used for reads.
 */
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
{
	unsigned retval = 0;

#ifdef DEBUG_SROM
	printf(" EEPROM op 0x%x: ", cmd);
#endif

	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);

	/* Shift the command bits out. */
	do {
		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
		sendto_srom(dev,dataval, ioaddr);
		udelay(10);

#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev,ioaddr) & 15);
#endif

		sendto_srom(dev,dataval | DT_CLK, ioaddr);
		udelay(10);
		retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
	} while (--cmd_len >= 0);
	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);

	/* Terminate the EEPROM access. */
	sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);

#ifdef DEBUG_SROM
	printf(" EEPROM result is 0x%5.5x.\n", retval);
#endif

	return retval;
}

static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
{
	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;

	return do_eeprom_cmd(dev, ioaddr,
			     (((SROM_READ_CMD << ee_addr_size) | index) << 16)
			     | 0xffff, 3 + ee_addr_size + 16);
}

#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
{
	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
	int i;
	unsigned short newval;

	udelay(10*1000); /* test-only */

#ifdef DEBUG_SROM
	printf("ee_addr_size=%d.\n", ee_addr_size);
	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
#endif

	/* Enable programming modes. */
	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);

	/* Do the actual write. */
	do_eeprom_cmd(dev, ioaddr,
		      (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
		      3 + ee_addr_size + 16);

	/* Poll for write finished. */
	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
		if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
			break;

#ifdef DEBUG_SROM
	printf(" Write finished after %d ticks.\n", i);
#endif

	/* Disable programming. */
	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);

	/* And read the result. */
	newval = do_eeprom_cmd(dev, ioaddr,
			       (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
			       | 0xffff, 3 + ee_addr_size + 16);
#ifdef DEBUG_SROM
	printf("  New value at offset %d is %4.4x.\n", index, newval);
#endif
	return 1;
}
#endif

static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
	int i, j = 0;

	for (i = 0; i < (ETH_ALEN >> 1); i++) {
		tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
		*p = le16_to_cpu(tmp);
		j += *p++;
	}

	if ((j == 0) || (j == 0x2fffd)) {
		memset (dev->enetaddr, 0, ETH_ALEN);
		debug ("Warning: can't read HW address from SROM.\n");
		goto Done;
	}

	return;

Done:
#ifdef UPDATE_SROM
	update_srom(dev, bis);
#endif
	return;
}

#ifdef UPDATE_SROM
static void update_srom(struct eth_device *dev, bd_t *bis)
{
	int i;
	static unsigned short eeprom[0x40] = {
		0x140b, 0x6610, 0x0000, 0x0000,	/* 00 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 04 */
		0x00a3, 0x0103, 0x0000, 0x0000,	/* 08 */
		0x0000, 0x1f00, 0x0000, 0x0000,	/* 0c */
		0x0108, 0x038d, 0x0000, 0x0000,	/* 10 */
		0xe078, 0x0001, 0x0040, 0x0018,	/* 14 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 18 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 1c */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 20 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 24 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 28 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 2c */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 30 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 34 */
		0x0000, 0x0000, 0x0000, 0x0000,	/* 38 */
		0x0000, 0x0000, 0x0000, 0x4e07,	/* 3c */
	};
	uchar enetaddr[6];

	/* Ethernet Addr... */
	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
		return;
	eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
	eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
	eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];

	for (i=0; i<0x40; i++) {
		write_srom(dev, DE4X5_APROM, i, eeprom[i]);
	}
}
#endif	/* UPDATE_SROM */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2
c609719b WD	3	#include <common.h>
7b51b576	4	#include <env.h>
c609719b WD	5	#include <malloc.h>
c609719b WD	6	#include <net.h>
8ca0b3f9	7	#include <netdev.h>
c609719b WD	8	#include <pci.h>
c609719b WD	9
c609719b WD	10	#undef DEBUG_SROM
	11	#undef DEBUG_SROM2
	12
	13	#undef UPDATE_SROM
	14
	15	/* PCI Registers.
	16	*/
	17	#define PCI_CFDA_PSM 0x43
	18
	19	#define CFRV_RN 0x000000f0 /* Revision Number */
	20
	21	#define WAKEUP 0x00 /* Power Saving Wakeup */
	22	#define SLEEP 0x80 /* Power Saving Sleep Mode */
	23
	24	#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
	25
	26	/* Ethernet chip registers.
	27	*/
	28	#define DE4X5_BMR 0x000 /* Bus Mode Register */
	29	#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
	30	#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
	31	#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
	32	#define DE4X5_STS 0x028 /* Status Register */
	33	#define DE4X5_OMR 0x030 /* Operation Mode Register */
	34	#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
	35	#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
	36
	37	/* Register bits.
	38	*/
	39	#define BMR_SWR 0x00000001 /* Software Reset */
	40	#define STS_TS 0x00700000 /* Transmit Process State */
	41	#define STS_RS 0x000e0000 /* Receive Process State */
	42	#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
	43	#define OMR_SR 0x00000002 /* Start/Stop Receive */
	44	#define OMR_PS 0x00040000 /* Port Select */
	45	#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
	46	#define OMR_PM 0x00000080 /* Pass All Multicast */
	47
	48	/* Descriptor bits.
	49	*/
	50	#define R_OWN 0x80000000 /* Own Bit */
	51	#define RD_RER 0x02000000 /* Receive End Of Ring */
	52	#define RD_LS 0x00000100 /* Last Descriptor */
	53	#define RD_ES 0x00008000 /* Error Summary */
	54	#define TD_TER 0x02000000 /* Transmit End Of Ring */
	55	#define T_OWN 0x80000000 /* Own Bit */
	56	#define TD_LS 0x40000000 /* Last Segment */
	57	#define TD_FS 0x20000000 /* First Segment */
	58	#define TD_ES 0x00008000 /* Error Summary */
	59	#define TD_SET 0x08000000 /* Setup Packet */
	60
	61	/* The EEPROM commands include the alway-set leading bit. */
	62	#define SROM_WRITE_CMD 5
	63	#define SROM_READ_CMD 6
	64	#define SROM_ERASE_CMD 7
	65
	66	#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
	67	#define SROM_RD 0x00004000 /* Read from Boot ROM */
c935d3bd WD	68	#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
	69	#define EE_WRITE_0 0x4801
	70	#define EE_WRITE_1 0x4805
	71	#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
c609719b WD	72	#define SROM_SR 0x00000800 /* Select Serial ROM when set */
	73
	74	#define DT_IN 0x00000004 /* Serial Data In */
	75	#define DT_CLK 0x00000002 /* Serial ROM Clock */
	76	#define DT_CS 0x00000001 /* Serial ROM Chip Select */
	77
	78	#define POLL_DEMAND 1
	79
	80	#define RESET_DE4X5(dev) {\
	81	int i;\
	82	i=INL(dev, DE4X5_BMR);\
	83	udelay(1000);\
	84	OUTL(dev, i \| BMR_SWR, DE4X5_BMR);\
	85	udelay(1000);\
	86	OUTL(dev, i, DE4X5_BMR);\
	87	udelay(1000);\
	88	for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
	89	udelay(1000);\
	90	}
	91
	92	#define START_DE4X5(dev) {\
	93	s32 omr; \
	94	omr = INL(dev, DE4X5_OMR);\
	95	omr \|= OMR_ST \| OMR_SR;\
	96	OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
	97	}
	98
	99	#define STOP_DE4X5(dev) {\
	100	s32 omr; \
	101	omr = INL(dev, DE4X5_OMR);\
	102	omr &= ~(OMR_ST\|OMR_SR);\
	103	OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
	104	}
	105
	106	#define NUM_RX_DESC PKTBUFSRX
171f5e58	107	#define NUM_TX_DESC 1 /* Number of TX descriptors */
c609719b WD	108	#define RX_BUFF_SZ PKTSIZE_ALIGN
	109
	110	#define TOUT_LOOP 1000000
	111
	112	#define SETUP_FRAME_LEN 192
c609719b	113
c609719b WD	114	struct de4x5_desc {
	115	volatile s32 status;
	116	u32 des1;
	117	u32 buf;
	118	u32 next;
	119	};
	120
63f34912 WD	121	static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
63f34912 WD	122	static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
c609719b WD	123	static int rx_new; /* RX descriptor ring pointer */
	124	static int tx_new; /* TX descriptor ring pointer */
	125
	126	static char rxRingSize;
	127	static char txRingSize;
	128
	129	static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
	130	static int getfrom_srom(struct eth_device* dev, u_long addr);
c935d3bd WD	131	static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
c935d3bd WD	132	static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
c609719b WD	133	#ifdef UPDATE_SROM
	134	static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
	135	static void update_srom(struct eth_device dev, bd_t bis);
	136	#endif
c935d3bd	137	static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
c609719b WD	138	static void read_hw_addr(struct eth_device* dev, bd_t * bis);
	139	static void send_setup_frame(struct eth_device* dev, bd_t * bis);
	140
	141	static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
6636c701	142	static int dc21x4x_send(struct eth_device dev, void packet, int length);
c609719b WD	143	static int dc21x4x_recv(struct eth_device* dev);
c609719b WD	144	static void dc21x4x_halt(struct eth_device* dev);
c609719b	145
42d1f039 WD	146	#if defined(CONFIG_E500)
	147	#define phys_to_bus(a) (a)
	148	#else
c609719b	149	#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
42d1f039	150	#endif
c609719b WD	151
	152	static int INL(struct eth_device* dev, u_long addr)
	153	{
	154	return le32_to_cpu((volatile u_long )(addr + dev->iobase));
	155	}
	156
	157	static void OUTL(struct eth_device* dev, int command, u_long addr)
	158	{
	159	(volatile u_long )(addr + dev->iobase) = cpu_to_le32(command);
	160	}
	161
	162	static struct pci_device_id supported[] = {
	163	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
	164	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
	165	{ }
	166	};
	167
	168	int dc21x4x_initialize(bd_t *bis)
	169	{
ca5cb04b MV	170	struct eth_device *dev;
	171	unsigned short status;
	172	unsigned char timer;
	173	unsigned int iobase;
	174	int card_number = 0;
	175	pci_dev_t devbusfn;
	176	unsigned int cfrv;
	177	int idx = 0;
	178
	179	while (1) {
	180	devbusfn = pci_find_devices(supported, idx++);
	181	if (devbusfn == -1)
c609719b	182	break;
c609719b WD	183
	184	/* Get the chip configuration revision register. */
	185	pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
	186
ca5cb04b	187	if ((cfrv & CFRV_RN) < DC2114x_BRK) {
c609719b WD	188	printf("Error: The chip is not DC21143.\n");
	189	continue;
	190	}
	191
	192	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
ca5cb04b	193	status \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
c609719b WD	194	pci_write_config_word(devbusfn, PCI_COMMAND, status);
	195
	196	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
df6a36fb LW	197	if (!(status & PCI_COMMAND_MEMORY)) {
df6a36fb LW	198	printf("Error: Can not enable MEMORY access.\n");
c609719b WD	199	continue;
	200	}
	201
	202	if (!(status & PCI_COMMAND_MASTER)) {
	203	printf("Error: Can not enable Bus Mastering.\n");
	204	continue;
	205	}
	206
	207	/* Check the latency timer for values >= 0x60. */
	208	pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
	209
	210	if (timer < 0x60) {
ca5cb04b MV	211	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
ca5cb04b MV	212	0x60);
c609719b WD	213	}
c609719b WD	214
c609719b WD	215	/* read BAR for memory space access */
	216	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
	217	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
ca5cb04b	218	debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
c609719b	219
ca5cb04b	220	dev = (struct eth_device )malloc(sizeof(dev));
be44f758 NI	221	if (!dev) {
	222	printf("Can not allocalte memory of dc21x4x\n");
	223	break;
	224	}
ca5cb04b	225
be44f758 NI	226	memset(dev, 0, sizeof(*dev));
be44f758 NI	227
c935d3bd	228	sprintf(dev->name, "dc21x4x#%d", card_number);
63f34912	229
c609719b	230	dev->iobase = pci_mem_to_phys(devbusfn, iobase);
ca5cb04b MV	231	dev->priv = (void *)devbusfn;
	232	dev->init = dc21x4x_init;
	233	dev->halt = dc21x4x_halt;
	234	dev->send = dc21x4x_send;
	235	dev->recv = dc21x4x_recv;
c609719b WD	236
	237	/* Ensure we're not sleeping. */
	238	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
	239
	240	udelay(10 * 1000);
	241
c935d3bd	242	read_hw_addr(dev, bis);
171f5e58	243
c609719b WD	244	eth_register(dev);
	245
	246	card_number++;
	247	}
	248
	249	return card_number;
	250	}
	251
ca5cb04b	252	static int dc21x4x_init(struct eth_device dev, bd_t bis)
c609719b	253	{
ca5cb04b MV	254	int i;
ca5cb04b MV	255	int devbusfn = (int)dev->priv;
c609719b WD	256
	257	/* Ensure we're not sleeping. */
	258	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
	259
	260	RESET_DE4X5(dev);
	261
	262	if ((INL(dev, DE4X5_STS) & (STS_TS \| STS_RS)) != 0) {
	263	printf("Error: Cannot reset ethernet controller.\n");
422b1a01	264	return -1;
c609719b WD	265	}
c609719b WD	266
c609719b	267	OUTL(dev, OMR_SDP \| OMR_PS \| OMR_PM, DE4X5_OMR);
c609719b WD	268
	269	for (i = 0; i < NUM_RX_DESC; i++) {
	270	rx_ring[i].status = cpu_to_le32(R_OWN);
	271	rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
ca5cb04b MV	272	rx_ring[i].buf =
ca5cb04b MV	273	cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
c609719b WD	274	rx_ring[i].next = 0;
	275	}
	276
ca5cb04b	277	for (i = 0; i < NUM_TX_DESC; i++) {
c609719b WD	278	tx_ring[i].status = 0;
	279	tx_ring[i].des1 = 0;
	280	tx_ring[i].buf = 0;
	281	tx_ring[i].next = 0;
	282	}
	283
	284	rxRingSize = NUM_RX_DESC;
	285	txRingSize = NUM_TX_DESC;
	286
	287	/* Write the end of list marker to the descriptor lists. */
	288	rx_ring[rxRingSize - 1].des1 \|= cpu_to_le32(RD_RER);
	289	tx_ring[txRingSize - 1].des1 \|= cpu_to_le32(TD_TER);
	290
	291	/* Tell the adapter where the TX/RX rings are located. */
ca5cb04b MV	292	OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
ca5cb04b MV	293	OUTL(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
c609719b WD	294
	295	START_DE4X5(dev);
	296
	297	tx_new = 0;
	298	rx_new = 0;
	299
	300	send_setup_frame(dev, bis);
	301
422b1a01	302	return 0;
c609719b WD	303	}
c609719b WD	304
6636c701	305	static int dc21x4x_send(struct eth_device dev, void packet, int length)
c609719b	306	{
7c53e336 MV	307	int status = -1;
7c53e336 MV	308	int i;
c609719b WD	309
	310	if (length <= 0) {
	311	printf("%s: bad packet size: %d\n", dev->name, length);
7c53e336	312	goto done;
c609719b WD	313	}
c609719b WD	314
7c53e336 MV	315	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
	316	if (i < TOUT_LOOP)
	317	continue;
	318
	319	printf("%s: tx error buffer not ready\n", dev->name);
	320	goto done;
c609719b WD	321	}
c609719b WD	322
7c53e336 MV	323	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
7c53e336 MV	324	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER \| TD_LS \| TD_FS \| length);
c609719b WD	325	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
	326
	327	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
	328
7c53e336 MV	329	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
	330	if (i < TOUT_LOOP)
	331	continue;
	332
	333	printf(".%s: tx buffer not ready\n", dev->name);
	334	goto done;
c609719b WD	335	}
	336
	337	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
63f34912	338	tx_ring[tx_new].status = 0x0;
7c53e336	339	goto done;
c609719b WD	340	}
	341
	342	status = length;
	343
7c53e336 MV	344	done:
7c53e336 MV	345	tx_new = (tx_new + 1) % NUM_TX_DESC;
c609719b WD	346	return status;
	347	}
	348
	349	static int dc21x4x_recv(struct eth_device* dev)
	350	{
	351	s32 status;
	352	int length = 0;
	353
	354	for ( ; ; ) {
	355	status = (s32)le32_to_cpu(rx_ring[rx_new].status);
	356
	357	if (status & R_OWN) {
	358	break;
	359	}
	360
	361	if (status & RD_LS) {
	362	/* Valid frame status.
	363	*/
	364	if (status & RD_ES) {
	365
	366	/* There was an error.
	367	*/
	368	printf("RX error status = 0x%08X\n", status);
	369	} else {
	370	/* A valid frame received.
	371	*/
	372	length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
	373
	374	/* Pass the packet up to the protocol
	375	* layers.
	376	*/
1fd92db8 JH	377	net_process_received_packet(
1fd92db8 JH	378	net_rx_packets[rx_new], length - 4);
c609719b WD	379	}
	380
	381	/* Change buffer ownership for this frame, back
	382	* to the adapter.
	383	*/
	384	rx_ring[rx_new].status = cpu_to_le32(R_OWN);
	385	}
	386
	387	/* Update entry information.
	388	*/
	389	rx_new = (rx_new + 1) % rxRingSize;
	390	}
	391
	392	return length;
	393	}
	394
	395	static void dc21x4x_halt(struct eth_device* dev)
	396	{
	397	int devbusfn = (int) dev->priv;
	398
	399	STOP_DE4X5(dev);
	400	OUTL(dev, 0, DE4X5_SICR);
	401
	402	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
	403	}
	404
	405	static void send_setup_frame(struct eth_device* dev, bd_t *bis)
	406	{
	407	int i;
	408	char setup_frame[SETUP_FRAME_LEN];
53677ef1	409	char *pa = &setup_frame[0];
c609719b WD	410
	411	memset(pa, 0xff, SETUP_FRAME_LEN);
	412
	413	for (i = 0; i < ETH_ALEN; i++) {
	414	*(pa + (i & 1)) = dev->enetaddr[i];
	415	if (i & 0x01) {
	416	pa += 4;
	417	}
	418	}
	419
	420	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
	421	if (i >= TOUT_LOOP) {
	422	printf("%s: tx error buffer not ready\n", dev->name);
	423	goto Done;
	424	}
	425	}
	426
	427	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
	428	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER \| TD_SET\| SETUP_FRAME_LEN);
	429	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
	430
	431	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
	432
	433	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
	434	if (i >= TOUT_LOOP) {
	435	printf("%s: tx buffer not ready\n", dev->name);
	436	goto Done;
	437	}
	438	}
	439
	440	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
	441	printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
	442	}
63f34912 WD	443	tx_new = (tx_new+1) % NUM_TX_DESC;
63f34912 WD	444
c609719b WD	445	Done:
	446	return;
	447	}
	448
171f5e58	449	/* SROM Read and write routines. */
c609719b WD	450	static void
	451	sendto_srom(struct eth_device* dev, u_int command, u_long addr)
	452	{
	453	OUTL(dev, command, addr);
	454	udelay(1);
	455	}
	456
	457	static int
	458	getfrom_srom(struct eth_device* dev, u_long addr)
	459	{
	460	s32 tmp;
	461
	462	tmp = INL(dev, addr);
	463	udelay(1);
	464
	465	return tmp;
	466	}
	467
	468	/* Note: this routine returns extra data bits for size detection. */
	469	static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
	470	{
	471	int i;
	472	unsigned retval = 0;
	473	int read_cmd = location \| (SROM_READ_CMD << addr_len);
	474
	475	sendto_srom(dev, SROM_RD \| SROM_SR, ioaddr);
	476	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
	477
	478	#ifdef DEBUG_SROM
	479	printf(" EEPROM read at %d ", location);
	480	#endif
	481
	482	/* Shift the read command bits out. */
	483	for (i = 4 + addr_len; i >= 0; i--) {
	484	short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
	485	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| dataval, ioaddr);
	486	udelay(10);
	487	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| dataval \| DT_CLK, ioaddr);
	488	udelay(10);
	489	#ifdef DEBUG_SROM2
	490	printf("%X", getfrom_srom(dev, ioaddr) & 15);
	491	#endif
	492	retval = (retval << 1) \| ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
	493	}
	494
	495	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
	496
	497	#ifdef DEBUG_SROM2
	498	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
	499	#endif
	500
	501	for (i = 16; i > 0; i--) {
	502	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| DT_CLK, ioaddr);
	503	udelay(10);
	504	#ifdef DEBUG_SROM2
	505	printf("%X", getfrom_srom(dev, ioaddr) & 15);
	506	#endif
	507	retval = (retval << 1) \| ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
	508	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
	509	udelay(10);
	510	}
	511
	512	/* Terminate the EEPROM access. */
	513	sendto_srom(dev, SROM_RD \| SROM_SR, ioaddr);
514
515	#ifdef DEBUG_SROM2
516	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
517	#endif
518
519	return retval;
520	}
521
171f5e58 MV	522	/*
171f5e58 MV	523	* This executes a generic EEPROM command, typically a write or write
c935d3bd WD	524	* enable. It returns the data output from the EEPROM, and thus may
	525	* also be used for reads.
	526	*/
c609719b WD	527	static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
	528	{
	529	unsigned retval = 0;
	530
	531	#ifdef DEBUG_SROM
	532	printf(" EEPROM op 0x%x: ", cmd);
	533	#endif
	534
	535	sendto_srom(dev,SROM_RD \| SROM_SR \| DT_CS \| DT_CLK, ioaddr);
	536
	537	/* Shift the command bits out. */
	538	do {
	539	short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
	540	sendto_srom(dev,dataval, ioaddr);
	541	udelay(10);
	542
	543	#ifdef DEBUG_SROM2
	544	printf("%X", getfrom_srom(dev,ioaddr) & 15);
	545	#endif
	546
	547	sendto_srom(dev,dataval \| DT_CLK, ioaddr);
	548	udelay(10);
	549	retval = (retval << 1) \| ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
	550	} while (--cmd_len >= 0);
	551	sendto_srom(dev,SROM_RD \| SROM_SR \| DT_CS, ioaddr);
	552
	553	/* Terminate the EEPROM access. */
	554	sendto_srom(dev,SROM_RD \| SROM_SR, ioaddr);
	555
	556	#ifdef DEBUG_SROM
	557	printf(" EEPROM result is 0x%5.5x.\n", retval);
	558	#endif
	559
	560	return retval;
	561	}
	562
	563	static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
	564	{
	565	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
	566
	567	return do_eeprom_cmd(dev, ioaddr,
	568	(((SROM_READ_CMD << ee_addr_size) \| index) << 16)
	569	\| 0xffff, 3 + ee_addr_size + 16);
	570	}
	571
	572	#ifdef UPDATE_SROM
	573	static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
	574	{
	575	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
	576	int i;
	577	unsigned short newval;
	578
	579	udelay(101000); / test-only */
	580
	581	#ifdef DEBUG_SROM
	582	printf("ee_addr_size=%d.\n", ee_addr_size);
	583	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
	584	#endif
	585
	586	/* Enable programming modes. */
	587	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
	588
	589	/* Do the actual write. */
	590	do_eeprom_cmd(dev, ioaddr,
591	(((SROM_WRITE_CMD<<ee_addr_size)\|index) << 16) \| new_value,
592	3 + ee_addr_size + 16);
593
594	/* Poll for write finished. */
595	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
596	for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
597	if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
598	break;
599
600	#ifdef DEBUG_SROM
601	printf(" Write finished after %d ticks.\n", i);
602	#endif
603
604	/* Disable programming. */
605	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
606
607	/* And read the result. */
608	newval = do_eeprom_cmd(dev, ioaddr,
609	(((SROM_READ_CMD<<ee_addr_size)\|index) << 16)
610	\| 0xffff, 3 + ee_addr_size + 16);
611	#ifdef DEBUG_SROM
612	printf(" New value at offset %d is %4.4x.\n", index, newval);
613	#endif
614	return 1;
615	}
616	#endif
617
618	static void read_hw_addr(struct eth_device dev, bd_t bis)
619	{
77ddac94	620	u_short tmp, p = (u_short )(&dev->enetaddr[0]);
c609719b WD	621	int i, j = 0;
	622
	623	for (i = 0; i < (ETH_ALEN >> 1); i++) {
	624	tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
	625	*p = le16_to_cpu(tmp);
	626	j += *p++;
	627	}
	628
	629	if ((j == 0) \|\| (j == 0x2fffd)) {
	630	memset (dev->enetaddr, 0, ETH_ALEN);
c935d3bd	631	debug ("Warning: can't read HW address from SROM.\n");
c609719b WD	632	goto Done;
	633	}
	634
	635	return;
	636
	637	Done:
	638	#ifdef UPDATE_SROM
	639	update_srom(dev, bis);
	640	#endif
	641	return;
	642	}
	643
	644	#ifdef UPDATE_SROM
	645	static void update_srom(struct eth_device dev, bd_t bis)
	646	{
	647	int i;
	648	static unsigned short eeprom[0x40] = {
53677ef1 WD	649	0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
	650	0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
	651	0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
	652	0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
	653	0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
	654	0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
	655	0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
	656	0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
	657	0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
	658	0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
	659	0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
	660	0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
	661	0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
	662	0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
	663	0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
	664	0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
c609719b	665	};
d3f87148	666	uchar enetaddr[6];
c609719b WD	667
c609719b WD	668	/* Ethernet Addr... */
35affd7a	669	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
d3f87148 MF	670	return;
	671	eeprom[0x0a] = (enetaddr[1] << 8) \| enetaddr[0];
	672	eeprom[0x0b] = (enetaddr[3] << 8) \| enetaddr[2];
	673	eeprom[0x0c] = (enetaddr[5] << 8) \| enetaddr[4];
c609719b	674
53677ef1	675	for (i=0; i<0x40; i++) {
c609719b WD	676	write_srom(dev, DE4X5_APROM, i, eeprom[i]);
	677	}
	678	}
c935d3bd	679	#endif /* UPDATE_SROM */