projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 65458987 AL |
1 | /* |
| 2 | * U-boot - Configuration file for BF561 EZKIT board | |
| 3 | */ | |
| 4 | ||
| cf6f469e MF |
5 | #ifndef __CONFIG_BF561_EZKIT_H__ |
| 6 | #define __CONFIG_BF561_EZKIT_H__ | |
| 65458987 | 7 | |
| f348ab85 | 8 | #include <asm/config-pre.h> |
| f7ce12cb | 9 | |
| 65458987 | 10 | |
| 65458987 | 11 | /* |
| cf6f469e | 12 | * Processor Settings |
| 65458987 | 13 | */ |
| fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf561-0.3 |
| cf6f469e | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
| 65458987 | 16 | |
| 65458987 AL |
17 | |
| 18 | /* | |
| cf6f469e MF |
19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
| 65458987 | 22 | */ |
| cf6f469e MF |
23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 30000000 | |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
| 26 | /* 1 = CLKIN / 2 */ | |
| 27 | #define CONFIG_CLKIN_HALF 0 | |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
| 29 | /* 1 = bypass PLL */ | |
| 30 | #define CONFIG_PLL_BYPASS 0 | |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ | |
| 33 | #define CONFIG_VCO_MULT 20 | |
| 34 | /* CCLK_DIV controls the core clock divider */ | |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
| 36 | #define CONFIG_CCLK_DIV 1 | |
| 37 | /* SCLK_DIV controls the system clock divider */ | |
| 38 | /* Values can range from 1-15 */ | |
| 39 | #define CONFIG_SCLK_DIV 6 | |
| 65458987 | 40 | |
| 65458987 AL |
41 | |
| 42 | /* | |
| cf6f469e | 43 | * Memory Settings |
| 65458987 | 44 | */ |
| cf6f469e MF |
45 | #define CONFIG_MEM_ADD_WDTH 9 |
| 46 | #define CONFIG_MEM_SIZE 64 | |
| 65458987 | 47 | |
| cf6f469e MF |
48 | #define CONFIG_EBIU_SDRRC_VAL 0x306 |
| 49 | #define CONFIG_EBIU_SDGCTL_VAL 0x91114d | |
| 65458987 | 50 | |
| cf6f469e MF |
51 | #define CONFIG_EBIU_AMGCTL_VAL 0x3F |
| 52 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 | |
| 53 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 | |
| 65458987 | 54 | |
| cf6f469e MF |
55 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 56 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) | |
| 65458987 | 57 | |
| 65458987 AL |
58 | |
| 59 | /* | |
| cf6f469e | 60 | * Network Settings |
| 65458987 | 61 | */ |
| cf6f469e | 62 | #define ADI_CMDS_NETWORK 1 |
| 7194ab80 | 63 | #define CONFIG_SMC91111 1 |
| cf6f469e MF |
64 | #define CONFIG_SMC91111_BASE 0x2C010300 |
| 65 | #define CONFIG_SMC_USE_32_BIT 1 | |
| 66 | #define CONFIG_HOSTNAME bf561-ezkit | |
| 65458987 | 67 | |
| 079a136c | 68 | |
| ba2351f9 | 69 | /* |
| cf6f469e | 70 | * Flash Settings |
| ba2351f9 | 71 | */ |
| cf6f469e MF |
72 | #define CONFIG_SYS_FLASH_CFI |
| 73 | #define CONFIG_FLASH_CFI_DRIVER | |
| 74 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
| 75 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
| 76 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 77 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
| 78 | /* The BF561-EZKIT uses a top boot flash */ | |
| 79 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 1b48f126 | 80 | #define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE) |
| d2ab733c | 81 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| 1b48f126 MF |
82 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
| 83 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
| ba2351f9 | 84 | |
| cf6f469e | 85 | |
| 65458987 | 86 | /* |
| cf6f469e | 87 | * I2C Settings |
| 65458987 | 88 | */ |
| ea818dbb HS |
89 | #define CONFIG_SYS_I2C_SOFT |
| 90 | #ifdef CONFIG_SYS_I2C_SOFT | |
| fa88d88f | 91 | #define CONFIG_SYS_I2C |
| beb60e77 MF |
92 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 |
| 93 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 | |
| ea818dbb HS |
94 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 95 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
| 96 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
| 97 | #endif | |
| 65458987 AL |
98 | |
| 99 | /* | |
| cf6f469e | 100 | * Misc Settings |
| 65458987 | 101 | */ |
| cf6f469e MF |
102 | #define CONFIG_UART_CONSOLE 0 |
| 103 | ||
| f4d80384 SZ |
104 | /* |
| 105 | * Run core 1 from L1 SRAM start address when init uboot on core 0 | |
| 106 | */ | |
| 107 | /* #define CONFIG_CORE1_RUN 1 */ | |
| 108 | ||
| 65458987 AL |
109 | |
| 110 | /* | |
| cf6f469e | 111 | * Pull in common ADI header for remaining command/environment setup |
| 65458987 | 112 | */ |
| cf6f469e | 113 | #include <configs/bfin_adi_common.h> |
| 65458987 | 114 | |
| f348ab85 | 115 | #endif |