[J-u-boot.git] / include / configs / MPC8349EMDS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2006-2010
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 */

/*
 * mpc8349emds board configuration file
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/

/*
 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
 * unselect it to use old spd_sdram.c
 */
#define CONFIG_SYS_SPD_BUS_NUM	0
#define SPD_EEPROM_ADDRESS1	0x52
#define SPD_EEPROM_ADDRESS2	0x51
#define CONFIG_DIMM_SLOTS_PER_CTLR	2
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef  CONFIG_DDR_2T_TIMING

/*
 * DDRCDR - DDR Control Driver Register
 */
#define CONFIG_SYS_DDRCDR_VALUE	0x80080001

#if defined(CONFIG_SPD_EEPROM)
/*
 * Determine DDR configuration from I2C interface.
 */
#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
#else
/*
 * Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		256		/* MB */
#if defined(CONFIG_DDR_II)
#define CONFIG_SYS_DDRCDR		0x80080001
#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
#define CONFIG_SYS_DDR_TIMING_0		0x00220802
#define CONFIG_SYS_DDR_TIMING_1		0x38357322
#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
#define CONFIG_SYS_DDR_TIMING_3		0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
#define CONFIG_SYS_DDR_MODE		0x47d00432
#define CONFIG_SYS_DDR_MODE2		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#else
#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1	0x36332321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */

#if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */
				/* DLL,normal,seq,4/2.5, 8 burst len */
#define CONFIG_SYS_DDR_MODE	0x00000023
#else
/* the default burst length is 4 - for 64-bit data path */
				/* DLL,normal,seq,4/2.5, 4 burst len */
#define CONFIG_SYS_DDR_MODE	0x00000022
#endif
#endif
#endif

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */


#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/*
 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 */
#define CONFIG_SYS_BCSR			0xE2400000
					/* Access window base at BCSR base */


#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* SPI */
#undef CONFIG_SOFT_SPI			/* SPI bit-banged */

/* GPIOs.  Used as SPI chip selects */
#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/* USB */
#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_83XX_PCI_STREAMING


#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_GMII		1	/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
/* Address and size of Redundant Environment Sector	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

/*
 * System performance
 */
#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_HOSTNAME		"mpc8349emds"
#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=mpc8349emds\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
	"update=protect off fe000000 fe03ffff; "			\
		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc834x_mds.dtb\0"					\
	""

#define NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
991425fe	2	/*
2ae18241	3	* (C) Copyright 2006-2010
991425fe	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
991425fe MB	5	*/
	6
	7	/*
	8	* mpc8349emds board configuration file
	9	*
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
991425fe MB	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 Family */
991425fe	19
32795eca	20	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
991425fe MB	21
	22	/*
	23	* DDR Setup
	24	*/
8d172c0f	25	#define CONFIG_DDR_ECC /* support DDR ECC function */
d326f4a2	26	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
991425fe MB	27	#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
991425fe MB	28
d4b91066	29	/*
d26e34c4 YS	30	* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
d26e34c4 YS	31	* unselect it to use old spd_sdram.c
d4b91066	32	*/
d4b91066 YS	33	#define CONFIG_SYS_SPD_BUS_NUM 0
	34	#define SPD_EEPROM_ADDRESS1 0x52
	35	#define SPD_EEPROM_ADDRESS2 0x51
d4b91066 YS	36	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	37	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	38	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	39	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
d4b91066	40
dc9e499c RJ	41	/*
dc9e499c RJ	42	* 32-bit data path mode.
cf48eb9a	43	*
dc9e499c RJ	44	* Please note that using this mode for devices with the real density of 64-bit
	45	* effectively reduces the amount of available memory due to the effect of
	46	* wrapping around while translating address to row/columns, for example in the
	47	* 256MB module the upper 128MB get aliased with contents of the lower
	48	* 128MB); normally this define should be used for devices with real 32-bit
cf48eb9a	49	* data path.
dc9e499c RJ	50	*/
	51	#undef CONFIG_DDR_32BIT
	52
8a81bfd2	53	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
32795eca JH	54	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
32795eca JH	55	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
991425fe MB	56	#undef CONFIG_DDR_2T_TIMING
991425fe MB	57
8d172c0f XX	58	/*
	59	* DDRCDR - DDR Control Driver Register
	60	*/
6d0f6bcf	61	#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
8d172c0f	62
991425fe	63	#if defined(CONFIG_SPD_EEPROM)
dc9e499c RJ	64	/*
	65	* Determine DDR configuration from I2C interface.
	66	*/
	67	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
991425fe	68	#else
dc9e499c RJ	69	/*
	70	* Manually set up DDR parameters
	71	*/
6d0f6bcf	72	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
8d172c0f	73	#if defined(CONFIG_DDR_II)
6d0f6bcf	74	#define CONFIG_SYS_DDRCDR 0x80080001
32795eca	75	#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
6d0f6bcf	76	#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
32795eca JH	77	#define CONFIG_SYS_DDR_TIMING_0 0x00220802
	78	#define CONFIG_SYS_DDR_TIMING_1 0x38357322
	79	#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
	80	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	81	#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
6d0f6bcf JCPV	82	#define CONFIG_SYS_DDR_MODE 0x47d00432
6d0f6bcf JCPV	83	#define CONFIG_SYS_DDR_MODE2 0x8000c000
32795eca	84	#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
6d0f6bcf JCPV	85	#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
6d0f6bcf JCPV	86	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
8d172c0f	87	#else
2e651b24	88	#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
32795eca JH	89	\| CSCONFIG_ROW_BIT_13 \
32795eca JH	90	\| CSCONFIG_COL_BIT_10)
6d0f6bcf JCPV	91	#define CONFIG_SYS_DDR_TIMING_1 0x36332321
6d0f6bcf JCPV	92	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
32795eca	93	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
6d0f6bcf	94	#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
dc9e499c RJ	95
	96	#if defined(CONFIG_DDR_32BIT)
	97	/* set burst length to 8 for 32-bit data path */
32795eca JH	98	/* DLL,normal,seq,4/2.5, 8 burst len */
32795eca JH	99	#define CONFIG_SYS_DDR_MODE 0x00000023
dc9e499c RJ	100	#else
dc9e499c RJ	101	/* the default burst length is 4 - for 64-bit data path */
32795eca JH	102	/* DLL,normal,seq,4/2.5, 4 burst len */
32795eca JH	103	#define CONFIG_SYS_DDR_MODE 0x00000022
dc9e499c	104	#endif
991425fe	105	#endif
8d172c0f	106	#endif
991425fe MB	107
	108	/*
	109	* SDRAM on the Local Bus
	110	*/
6d0f6bcf JCPV	111	#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	112	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
991425fe MB	113
	114	/*
	115	* FLASH on the Local Bus
	116	*/
6d0f6bcf	117	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
32795eca	118	#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
991425fe	119
7d6a0982	120
32795eca JH	121	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
32795eca JH	122	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
991425fe	123
6d0f6bcf JCPV	124	#undef CONFIG_SYS_FLASH_CHECKSUM
	125	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	126	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
991425fe	127
14d0a02a	128	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
991425fe	129
6d0f6bcf JCPV	130	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	131	#define CONFIG_SYS_RAMBOOT
991425fe	132	#else
6d0f6bcf	133	#undef CONFIG_SYS_RAMBOOT
991425fe MB	134	#endif
	135
	136	/*
	137	* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
	138	*/
32795eca JH	139	#define CONFIG_SYS_BCSR 0xE2400000
32795eca JH	140	/* Access window base at BCSR base */
a8f97539	141
991425fe	142
6d0f6bcf	143	#define CONFIG_SYS_INIT_RAM_LOCK 1
32795eca JH	144	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
32795eca JH	145	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
991425fe	146
32795eca JH	147	#define CONFIG_SYS_GBL_DATA_OFFSET \
32795eca JH	148	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	149	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
991425fe	150
16c8c170	151	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
c8a90646	152	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
991425fe	153
991425fe MB	154	/*
	155	* Serial Port
	156	*/
6d0f6bcf JCPV	157	#define CONFIG_SYS_NS16550_SERIAL
	158	#define CONFIG_SYS_NS16550_REG_SIZE 1
	159	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
991425fe	160
6d0f6bcf	161	#define CONFIG_SYS_BAUDRATE_TABLE \
32795eca	162	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
991425fe	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	165	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
991425fe	166
991425fe	167	/* I2C */
00f792e0	168	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
991425fe	169
80ddd226	170	/* SPI */
80ddd226	171	#undef CONFIG_SOFT_SPI /* SPI bit-banged */
80ddd226 BW	172
80ddd226 BW	173	/* GPIOs. Used as SPI chip selects */
6d0f6bcf JCPV	174	#define CONFIG_SYS_GPIO1_PRELIM
	175	#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
	176	#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
80ddd226	177
991425fe	178	/* TSEC */
6d0f6bcf	179	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
32795eca	180	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	181	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
32795eca	182	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
991425fe	183
8fe9bf61	184	/* USB */
6d0f6bcf	185	#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
991425fe MB	186
	187	/*
	188	* General PCI
	189	* Addresses are mapped 1-1.
	190	*/
6d0f6bcf JCPV	191	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	192	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	193	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	194	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	195	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	196	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
32795eca JH	197	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	198	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	199	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
6d0f6bcf JCPV	200
	201	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
	202	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	203	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
	204	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
	205	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
	206	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
32795eca JH	207	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	208	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
	209	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
991425fe MB	210
	211	#if defined(CONFIG_PCI)
	212
162338e1	213	#define CONFIG_83XX_PCI_STREAMING
991425fe	214
991425fe MB	215
	216	#if !defined(CONFIG_PCI_PNP)
	217	#define PCI_ENET0_IOADDR 0xFIXME
	218	#define PCI_ENET0_MEMADDR 0xFIXME
53677ef1	219	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
991425fe MB	220	#endif
	221
	222	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
991425fe MB	223
	224	#endif /* CONFIG_PCI */
	225
	226	/*
	227	* TSEC configuration
	228	*/
991425fe MB	229
991425fe MB	230	#if defined(CONFIG_TSEC_ENET)
991425fe MB	231
991425fe MB	232	#define CONFIG_GMII 1 /* MII PHY management */
32795eca	233	#define CONFIG_TSEC1 1
255a3577	234	#define CONFIG_TSEC1_NAME "TSEC0"
32795eca	235	#define CONFIG_TSEC2 1
255a3577	236	#define CONFIG_TSEC2_NAME "TSEC1"
991425fe MB	237	#define TSEC1_PHY_ADDR 0
	238	#define TSEC2_PHY_ADDR 1
	239	#define TSEC1_PHYIDX 0
	240	#define TSEC2_PHYIDX 0
3a79013e AF	241	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	242	#define TSEC2_FLAGS TSEC_GIGABIT
991425fe MB	243
	244	/* Options are: TSEC[0-1] */
	245	#define CONFIG_ETHPRIME "TSEC0"
	246
	247	#endif /* CONFIG_TSEC_ENET */
	248
	249	/*
	250	* Configure on-board RTC
	251	*/
32795eca JH	252	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
32795eca JH	253	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
991425fe MB	254
	255	/*
	256	* Environment
	257	*/
6d0f6bcf	258	#ifndef CONFIG_SYS_RAMBOOT
991425fe	259	/* Address and size of Redundant Environment Sector */
991425fe MB	260	#endif
	261
	262	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	263	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
991425fe	264
659e2f67 JL	265	/*
	266	* BOOTP options
	267	*/
	268	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	269
991425fe MB	270	#undef CONFIG_WATCHDOG /* watchdog disabled */
	271
	272	/*
	273	* Miscellaneous configurable options
	274	*/
6d0f6bcf	275	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
991425fe	276
991425fe MB	277	/*
991425fe MB	278	* For booting Linux, the board info and command line data
9f530d59	279	* have to be in the first 256 MB of memory, since this is
991425fe MB	280	* the maximum mapped by the Linux kernel during initialization.
991425fe MB	281	*/
32795eca JH	282	/* Initial Memory map for Linux*/
32795eca JH	283	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	284	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
991425fe	285
6d0f6bcf	286	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
991425fe	287
a5fe514e LN	288	/*
	289	* System performance
	290	*/
6d0f6bcf JCPV	291	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
6d0f6bcf JCPV	292	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
a5fe514e	293
991425fe	294	/* System IO Config */
3c9b1ee1	295	#define CONFIG_SYS_SICRH 0
6d0f6bcf	296	#define CONFIG_SYS_SICRL SICRL_LDP_A
991425fe	297
991425fe	298	#ifdef CONFIG_PCI
842033e6	299	#define CONFIG_PCI_INDIRECT_BRIDGE
991425fe MB	300	#endif
991425fe MB	301
8ea5499a	302	#if defined(CONFIG_CMD_KGDB)
991425fe	303	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
991425fe MB	304	#endif
	305
	306	/*
	307	* Environment Configuration
	308	*/
991425fe MB	309
991425fe MB	310	#if defined(CONFIG_TSEC_ENET)
991425fe	311	#define CONFIG_HAS_ETH1
10327dc5	312	#define CONFIG_HAS_ETH0
991425fe MB	313	#endif
991425fe MB	314
5bc0543d	315	#define CONFIG_HOSTNAME "mpc8349emds"
8b3637c6	316	#define CONFIG_ROOTPATH "/nfsroot/rootfs"
b3f44c21	317	#define CONFIG_BOOTFILE "uImage"
991425fe	318
32795eca	319	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
991425fe	320
991425fe MB	321	#define CONFIG_EXTRA_ENV_SETTINGS \
	322	"netdev=eth0\0" \
	323	"hostname=mpc8349emds\0" \
	324	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	325	"nfsroot=${serverip}:${rootpath}\0" \
	326	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	327	"addip=setenv bootargs ${bootargs} " \
	328	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	329	":${hostname}:${netdev}:off panic=1\0" \
	330	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	331	"flash_nfs=run nfsargs addip addtty;" \
	332	"bootm ${kernel_addr}\0" \
	333	"flash_self=run ramargs addip addtty;" \
	334	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	335	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	336	"bootm\0" \
991425fe MB	337	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
991425fe MB	338	"update=protect off fe000000 fe03ffff; " \
32795eca	339	"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
d8ab58b2	340	"upd=run load update\0" \
79f516bc	341	"fdtaddr=780000\0" \
cc861f71	342	"fdtfile=mpc834x_mds.dtb\0" \
991425fe MB	343	""
991425fe MB	344
7ae1b080	345	#define NFSBOOTCOMMAND \
32795eca JH	346	"setenv bootargs root=/dev/nfs rw " \
	347	"nfsroot=$serverip:$rootpath " \
	348	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	349	"$netdev:off " \
	350	"console=$consoledev,$baudrate $othbootargs;" \
	351	"tftp $loadaddr $bootfile;" \
	352	"tftp $fdtaddr $fdtfile;" \
	353	"bootm $loadaddr - $fdtaddr"
bf0b542d	354
7ae1b080	355	#define RAMBOOTCOMMAND \
32795eca JH	356	"setenv bootargs root=/dev/ram rw " \
	357	"console=$consoledev,$baudrate $othbootargs;" \
	358	"tftp $ramdiskaddr $ramdiskfile;" \
	359	"tftp $loadaddr $bootfile;" \
	360	"tftp $fdtaddr $fdtfile;" \
	361	"bootm $loadaddr $ramdiskaddr $fdtaddr"
bf0b542d	362
991425fe MB	363	#define CONFIG_BOOTCOMMAND "run flash_self"
	364
	365	#endif /* __CONFIG_H */