[J-u-boot.git] / include / configs / ASH405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef  CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */

#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200
#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */

#define CFG_NAND_LEGACY

#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#define SECTORSIZE 512

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1

#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */

#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
					/* have only 8kB, 16kB is save here	*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CFG_EBC_PB0AP		0x92015480
/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
#define CFG_NAND_BASE	0xF4000000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CFG_GPIO0_OSRH		0x40000550
#define CFG_GPIO0_OSRL		0x00000110
#define CFG_GPIO0_ISR1H		0x00000000
#define CFG_GPIO0_ISR1L		0x15555445
#define CFG_GPIO0_TSRH		0x00000000
#define CFG_GPIO0_TSRL		0x00000000
#define CFG_GPIO0_TCR		0xF7FE0014

#define CFG_DUART_RST		(0x80000000 >> 14)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
#endif
#if 1
#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c93f7096 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_ASH405 1 /* ...on a ASH405 board */
c93f7096	39
c837dcb1 WD	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c93f7096	42
a20b27a3	43	#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
c93f7096 SR	44
	45	#define CONFIG_BAUDRATE 9600
	46	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47
	48	#undef CONFIG_BOOTARGS
a20b27a3 SR	49	#undef CONFIG_BOOTCOMMAND
	50
	51	#define CONFIG_PREBOOT /* enable preboot variable */
c93f7096 SR	52
	53	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	54	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	55
	56	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	57	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3 SR	58	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
	59
	60	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
c93f7096	61
498ff9a2	62
11799434 JL	63	/*
	64	* BOOTP options
	65	*/
	66	#define CONFIG_BOOTP_BOOTFILESIZE
	67	#define CONFIG_BOOTP_BOOTPATH
	68	#define CONFIG_BOOTP_GATEWAY
	69	#define CONFIG_BOOTP_HOSTNAME
	70
	71
498ff9a2 JL	72	/*
	73	* Command line configuration.
	74	*/
	75	#include <config_cmd_default.h>
	76
	77	#define CONFIG_CMD_DHCP
	78	#define CONFIG_CMD_IRQ
	79	#define CONFIG_CMD_ELF
	80	#define CONFIG_CMD_NAND
	81	#define CONFIG_CMD_DATE
	82	#define CONFIG_CMD_I2C
	83	#define CONFIG_CMD_MII
	84	#define CONFIG_CMD_PING
	85	#define CONFIG_CMD_EEPROM
	86
c93f7096	87
c837dcb1	88	#undef CONFIG_WATCHDOG /* watchdog disabled */
c93f7096	89
c837dcb1 WD	90	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
c837dcb1 WD	91	#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
c93f7096	92
c837dcb1	93	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c93f7096 SR	94
	95	/*
	96	* Miscellaneous configurable options
	97	*/
	98	#define CFG_LONGHELP /* undef to save memory */
	99	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	100
	101	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	102	#ifdef CFG_HUSH_PARSER
c837dcb1	103	#define CFG_PROMPT_HUSH_PS2 "> "
c93f7096 SR	104	#endif
c93f7096 SR	105
498ff9a2	106	#if defined(CONFIG_CMD_KGDB)
c837dcb1	107	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c93f7096	108	#else
c837dcb1	109	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c93f7096 SR	110	#endif
	111	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	112	#define CFG_MAXARGS 16 /* max number of command args */
	113	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	114
c837dcb1	115	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
c93f7096	116
c837dcb1	117	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c93f7096 SR	118
	119	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	120	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	121
c837dcb1 WD	122	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	123	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	124	#define CFG_BASE_BAUD 691200
	125	#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
c93f7096 SR	126
c93f7096 SR	127	/* The following table includes the supported baudrates */
c837dcb1	128	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	129	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	130	57600, 115200, 230400, 460800, 921600 }
c93f7096 SR	131
	132	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	133	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	134
c837dcb1	135	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c93f7096 SR	136
	137	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	138
c837dcb1	139	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
53cf9435	140
c837dcb1	141	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	142
c93f7096 SR	143	/*-----------------------------------------------------------------------
	144	* NAND-FLASH stuff
	145	*-----------------------------------------------------------------------
	146	*/
addb2e16 BS	147
	148	#define CFG_NAND_LEGACY
	149
c93f7096 SR	150	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	151	#define SECTORSIZE 512
	152
	153	#define ADDR_COLUMN 1
	154	#define ADDR_PAGE 2
	155	#define ADDR_COLUMN_PAGE 3
	156
c837dcb1	157	#define NAND_ChipID_UNKNOWN 0x00
c93f7096 SR	158	#define NAND_MAX_FLOORS 1
	159	#define NAND_MAX_CHIPS 1
	160
c837dcb1 WD	161	#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	162	#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	163	#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
	164	#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
c93f7096 SR	165
	166	#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_CE);} while(0)
	167	#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
	168	#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
	169	#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_ALE);} while(0)
	170	#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
	171	#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_CLE);} while(0)
	172	#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
	173
	174	#define WRITE_NAND_COMMAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)(d); } while(0)
	175	#define WRITE_NAND_ADDRESS(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)(d); } while(0)
	176	#define WRITE_NAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)d; } while(0)
	177	#define READ_NAND(adr) ((volatile unsigned char)((volatile __u8 )(unsigned long)adr))
	178
a20b27a3 SR	179	#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
	180	#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
	181
c93f7096 SR	182	/*-----------------------------------------------------------------------
	183	* PCI stuff
	184	*-----------------------------------------------------------------------
	185	*/
c837dcb1 WD	186	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	187	#define PCI_HOST_FORCE 1 /* configure as pci host */
	188	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	189
	190	#define CONFIG_PCI /* include pci support */
	191	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	192	#undef CONFIG_PCI_PNP /* do pci plug-and-play */
	193	/* resource configuration */
	194
	195	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	196
	197	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	198	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	199	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	200	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	201	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	202	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	203	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	204	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	205	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c93f7096 SR	206
	207	/*-----------------------------------------------------------------------
	208	* Start addresses for the final memory configuration
	209	* (Set up by the startup code)
	210	* Please note that CFG_SDRAM_BASE _must_ start at 0
	211	*/
	212	#define CFG_SDRAM_BASE 0x00000000
	213	#define CFG_FLASH_BASE 0xFFFC0000
	214	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	215	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	216	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	217
	218	/*
	219	* For booting Linux, the board info and command line data
	220	* have to be in the first 8 MB of memory, since this is
	221	* the maximum mapped by the Linux kernel during initialization.
	222	*/
	223	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	224	/*-----------------------------------------------------------------------
	225	* FLASH organization
	226	*/
	227	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	228	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	229
	230	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	231	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
	232
c837dcb1 WD	233	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	234	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	235	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c93f7096 SR	236	/*
	237	* The following defines are added for buggy IOP480 byte interface.
	238	* All other boards should use the standard values (CPCI405 etc.)
	239	*/
c837dcb1 WD	240	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	241	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	242	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c93f7096	243
c837dcb1	244	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c93f7096 SR	245
c93f7096 SR	246	#if 0 /* test-only */
c837dcb1 WD	247	#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
c837dcb1 WD	248	#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
c93f7096 SR	249	#endif
	250
	251	/*-----------------------------------------------------------------------
	252	* Environment Variable setup
	253	*/
c837dcb1 WD	254	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	255	#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
	256	#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
8bde7f77	257	/* total size of a CAT24WC16 is 2048 bytes */
c93f7096 SR	258
c93f7096 SR	259	#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
c837dcb1	260	#define CFG_NVRAM_SIZE 242 /* NVRAM size */
c93f7096 SR	261
	262	/*-----------------------------------------------------------------------
	263	* I2C EEPROM (CAT24WC16) for environment
	264	*/
	265	#define CONFIG_HARD_I2C /* I2c with hardware support */
	266	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	267	#define CFG_I2C_SLAVE 0x7F
	268
	269	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	270	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	271	/* mask of address bits that overflow into the "EEPROM chip address" */
c93f7096 SR	272	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	273	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	274	/* 16 byte page write mode using*/
c837dcb1	275	/* last 4 bits of the address */
c93f7096 SR	276	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	277	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	278
	279	/*-----------------------------------------------------------------------
	280	* Cache Configuration
	281	*/
0c8721a4	282	#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
c837dcb1	283	/* have only 8kB, 16kB is save here */
c93f7096	284	#define CFG_CACHELINE_SIZE 32 /* ... */
498ff9a2	285	#if defined(CONFIG_CMD_KGDB)
c93f7096 SR	286	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	287	#endif
	288
	289	/*
	290	* Init Memory Controller:
	291	*
	292	* BR0/1 and OR0/1 (FLASH)
	293	*/
	294
	295	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	296
	297	/*-----------------------------------------------------------------------
	298	* External Bus Controller (EBC) Setup
	299	*/
	300
c837dcb1 WD	301	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	302	#define CFG_EBC_PB0AP 0x92015480
	303	/#define CFG_EBC_PB0AP 0x08055880 /XXX TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
	304	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c93f7096	305
c837dcb1 WD	306	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
	307	#define CFG_EBC_PB1AP 0x92015480
	308	#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
c93f7096	309
c837dcb1 WD	310	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	311	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	312	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c93f7096	313
c837dcb1 WD	314	/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
	315	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	316	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c93f7096	317
c837dcb1 WD	318	#define CAN_BA 0xF0000000 /* CAN Base Address */
	319	#define DUART0_BA 0xF0000400 /* DUART Base Address */
	320	#define DUART1_BA 0xF0000408 /* DUART Base Address */
	321	#define DUART2_BA 0xF0000410 /* DUART Base Address */
	322	#define DUART3_BA 0xF0000418 /* DUART Base Address */
	323	#define RTC_BA 0xF0000500 /* RTC Base Address */
	324	#define CFG_NAND_BASE 0xF4000000
c93f7096 SR	325
	326	/*-----------------------------------------------------------------------
	327	* FPGA stuff
	328	*/
c837dcb1 WD	329	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	330	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S50E*/
c93f7096 SR	331
c93f7096 SR	332	/* FPGA program pin configuration */
c837dcb1 WD	333	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	334	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	335	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	336	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	337	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
c93f7096 SR	338
	339	/*-----------------------------------------------------------------------
	340	* Definitions for initial stack pointer and data area (in data cache)
	341	*/
	342	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	343	#define CFG_TEMP_STACK_OCM 1
c93f7096 SR	344
	345	/* On Chip Memory location */
	346	#define CFG_OCM_DATA_ADDR 0xF8000000
	347	#define CFG_OCM_DATA_SIZE 0x1000
	348	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	349	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	350
	351	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	352	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	353	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
c93f7096 SR	354
	355	/*-----------------------------------------------------------------------
	356	* Definitions for GPIO setup (PPC405EP specific)
	357	*
c837dcb1 WD	358	* GPIO0[0] - External Bus Controller BLAST output
c837dcb1 WD	359	* GPIO0[1-9] - Instruction trace outputs -> GPIO
c93f7096 SR	360	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	361	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	362	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	363	* GPIO0[24-27] - UART0 control signal inputs/outputs
	364	* GPIO0[28-29] - UART1 data signal input/output
	365	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	366	*/
c837dcb1 WD	367	#define CFG_GPIO0_OSRH 0x40000550
	368	#define CFG_GPIO0_OSRL 0x00000110
	369	#define CFG_GPIO0_ISR1H 0x00000000
	370	#define CFG_GPIO0_ISR1L 0x15555445
	371	#define CFG_GPIO0_TSRH 0x00000000
	372	#define CFG_GPIO0_TSRL 0x00000000
	373	#define CFG_GPIO0_TCR 0xF7FE0014
c93f7096	374
c837dcb1	375	#define CFG_DUART_RST (0x80000000 >> 14)
c93f7096 SR	376
	377	/*
	378	* Internal Definitions
	379	*
	380	* Boot Flags
	381	*/
	382	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	383	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	384
	385	/*
	386	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	387	* This value will be set if iic boot eprom is disabled.
	388	*/
	389	#if 0
c837dcb1 WD	390	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
c837dcb1 WD	391	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
c93f7096 SR	392	#endif
c93f7096 SR	393	#if 1
c837dcb1 WD	394	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
c837dcb1 WD	395	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
c93f7096 SR	396	#endif
c93f7096 SR	397	#if 0
c837dcb1 WD	398	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
c837dcb1 WD	399	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
c93f7096 SR	400	#endif
	401
	402	#endif /* __CONFIG_H */