[J-u-boot.git] / include / configs / bf537-pnav.h

/*
 * U-boot - Configuration file for BF537 PNAV board
 */

#ifndef __CONFIG_BF537_PNAV_H__
#define __CONFIG_BF537_PNAV_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			24576000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x3b7
#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB033B0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#endif
#define CONFIG_HOSTNAME		bf537-pnav

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_STMICRO


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#else
#define ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x20004000
#define CONFIG_ENV_OFFSET	0x4000
#endif
#define CONFIG_ENV_SIZE		0x1000
#define CONFIG_ENV_SECT_SIZE	0x2000
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * NAND Settings
 */
#define CONFIG_NAND_PLAT

#define CONFIG_SYS_NAND_BASE		0x20100000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12


/*
 * I2C settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI


/*
 * Misc Settings
 */
#define CONFIG_BAUDRATE		115200
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* JFFS Partition offset set  */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	15

#define CONFIG_BOOTCOMMAND	"run nandboot"
#define CONFIG_BOOTARGS_ROOT	"/dev/mtdblock1 rw rootfstype=yaffs"


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
cb4b5e87 MF	1	/*
	2	* U-boot - Configuration file for BF537 PNAV board
	3	*/
	4
	5	#ifndef __CONFIG_BF537_PNAV_H__
	6	#define __CONFIG_BF537_PNAV_H__
	7
f348ab85	8	#include <asm/config-pre.h>
cb4b5e87 MF	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf537-0.2
cb4b5e87 MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 24576000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 20
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 4
	40
	41
	42	/*
	43	* Memory Settings
	44	*/
	45	#define CONFIG_MEM_ADD_WDTH 10
	46	#define CONFIG_MEM_SIZE 64
	47
	48	#define CONFIG_EBIU_SDRRC_VAL 0x3b7
	49	#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	52	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
	53	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	54
4c95ff64	55	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
cb4b5e87 MF	56	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	57
	58
	59	/*
	60	* Network Settings
	61	*/
	62	#ifndef __ADSPBF534__
	63	#define ADI_CMDS_NETWORK 1
	64	#define CONFIG_BFIN_MAC
	65	#define CONFIG_RMII
cb4b5e87 MF	66	#endif
cb4b5e87 MF	67	#define CONFIG_HOSTNAME bf537-pnav
cb4b5e87 MF	68
	69	/*
	70	* Flash Settings
	71	*/
	72	#define CONFIG_FLASH_CFI_DRIVER
	73	#define CONFIG_SYS_FLASH_BASE 0x20000000
	74	#define CONFIG_SYS_FLASH_CFI
	75	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	76	#define CONFIG_SYS_MAX_FLASH_SECT 71
	77
	78
	79	/*
	80	* SPI Settings
	81	*/
	82	#define CONFIG_BFIN_SPI
	83	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	84	#define CONFIG_SF_DEFAULT_SPEED 30000000
cb4b5e87 MF	85	#define CONFIG_SPI_FLASH_STMICRO
	86
	87
	88	/*
	89	* Env Storage Settings
	90	*/
	91	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
76d82187	92	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
cb4b5e87 MF	93	#define CONFIG_ENV_IS_IN_SPI_FLASH
	94	#define CONFIG_ENV_OFFSET 0x4000
	95	#else
	96	#define ENV_IS_EMBEDDED
	97	#define CONFIG_ENV_IS_IN_FLASH 1
	98	#define CONFIG_ENV_ADDR 0x20004000
	99	#define CONFIG_ENV_OFFSET 0x4000
	100	#endif
	101	#define CONFIG_ENV_SIZE 0x1000
	102	#define CONFIG_ENV_SECT_SIZE 0x2000
9ff67e5e MF	103	#ifdef ENV_IS_EMBEDDED
	104	/* WARNING - the following is hand-optimized to fit within
	105	* the sector before the environment sector. If it throws
	106	* an error during compilation remove an object here to get
	107	* it linked after the configuration sector.
	108	*/
	109	# define LDS_BOARD_TEXT \
e2906a59 MY	110	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	111	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	112	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	113	common/env_embedded.o (.text*);
9ff67e5e	114	#endif
cb4b5e87 MF	115
	116
	117	/*
	118	* NAND Settings
	119	*/
	120	#define CONFIG_NAND_PLAT
	121
	122	#define CONFIG_SYS_NAND_BASE 0x20100000
	123	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	124
	125	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	126	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
cb4b5e87 MF	127	#define BFIN_NAND_WRITE(addr, cmd) \
	128	do { \
	129	bfin_write8(addr, cmd); \
	130	SSYNC(); \
	131	} while (0)
	132
	133	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
	134	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
67ceefa7	135	#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
cb4b5e87 MF	136
	137
	138	/*
	139	* I2C settings
	140	*/
c469703b	141	#define CONFIG_SYS_I2C
fea9b69a	142	#define CONFIG_SYS_I2C_ADI
cb4b5e87 MF	143
	144
	145	/*
	146	* Misc Settings
	147	*/
	148	#define CONFIG_BAUDRATE 115200
cb4b5e87 MF	149	#define CONFIG_RTC_BFIN
	150	#define CONFIG_UART_CONSOLE 0
	151
	152	/* JFFS Partition offset set */
	153	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	154	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	155	/* 512k reserved for u-boot */
	156	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
	157
	158	#define CONFIG_BOOTCOMMAND "run nandboot"
	159	#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
	160
	161
	162	/*
	163	* Pull in common ADI header for remaining command/environment setup
	164	*/
	165	#include <configs/bfin_adi_common.h>
	166
cb4b5e87	167	#endif