projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 14bc66bd HN |
2 | /* |
| 3 | * (C) Copyright 2012 Henrik Nordstrom <[email protected]> | |
| 14bc66bd HN |
4 | */ |
| 5 | ||
| 048447ce OS |
6 | #include <linux/bitops.h> |
| 7 | ||
| 940382fe PK |
8 | enum axp209_reg { |
| 9 | AXP209_POWER_STATUS = 0x00, | |
| 10 | AXP209_CHIP_VERSION = 0x03, | |
| beba401f | 11 | AXP209_OUTPUT_CTRL = 0x12, |
| 940382fe | 12 | AXP209_DCDC2_VOLTAGE = 0x23, |
| 61436d50 | 13 | AXP209_VRC_DCDC2_LDO3 = 0x25, |
| 940382fe PK |
14 | AXP209_DCDC3_VOLTAGE = 0x27, |
| 15 | AXP209_LDO24_VOLTAGE = 0x28, | |
| 16 | AXP209_LDO3_VOLTAGE = 0x29, | |
| 17 | AXP209_IRQ_ENABLE1 = 0x40, | |
| 18 | AXP209_IRQ_ENABLE2 = 0x41, | |
| 19 | AXP209_IRQ_ENABLE3 = 0x42, | |
| 20 | AXP209_IRQ_ENABLE4 = 0x43, | |
| 21 | AXP209_IRQ_ENABLE5 = 0x44, | |
| 22 | AXP209_IRQ_STATUS5 = 0x4c, | |
| 23 | AXP209_SHUTDOWN = 0x32, | |
| 940382fe PK |
24 | }; |
| 25 | ||
| 048447ce OS |
26 | #define AXP209_POWER_STATUS_ON_BY_DC BIT(0) |
| 27 | #define AXP209_POWER_STATUS_VBUS_USABLE BIT(4) | |
| 940382fe | 28 | |
| f5eebc79 OS |
29 | #define AXP209_CHIP_VERSION_MASK 0x0f |
| 30 | ||
| 048447ce OS |
31 | #define AXP209_OUTPUT_CTRL_EXTEN BIT(0) |
| 32 | #define AXP209_OUTPUT_CTRL_DCDC3 BIT(1) | |
| 33 | #define AXP209_OUTPUT_CTRL_LDO2 BIT(2) | |
| 34 | #define AXP209_OUTPUT_CTRL_LDO4 BIT(3) | |
| 35 | #define AXP209_OUTPUT_CTRL_DCDC2 BIT(4) | |
| 36 | #define AXP209_OUTPUT_CTRL_LDO3 BIT(6) | |
| beba401f | 37 | |
| 61436d50 OS |
38 | /* |
| 39 | * AXP209 datasheet contains wrong information about LDO3 VRC: | |
| 40 | * - VRC is actually enabled when BIT(1) is True | |
| 41 | * - VRC is actually not enabled by default (BIT(3) = 0 after reset) | |
| 42 | */ | |
| 43 | #define AXP209_VRC_LDO3_EN BIT(3) | |
| 44 | #define AXP209_VRC_DCDC2_EN BIT(2) | |
| 45 | #define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN) | |
| 46 | #define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN | |
| 47 | #define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN) | |
| 48 | #define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN | |
| 49 | #define AXP209_VRC_LDO3_MASK 0xa | |
| 50 | #define AXP209_VRC_DCDC2_MASK 0x5 | |
| 51 | #define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \ | |
| 52 | (((reg) & ~AXP209_VRC_DCDC2_MASK) | \ | |
| 53 | ((cfg) & AXP209_VRC_DCDC2_MASK)) | |
| 54 | #define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \ | |
| 55 | (((reg) & ~AXP209_VRC_LDO3_MASK) | \ | |
| 56 | ((cfg) & AXP209_VRC_LDO3_MASK)) | |
| 57 | ||
| 3f7d76a7 OS |
58 | #define AXP209_LDO24_LDO2_MASK 0xf0 |
| 59 | #define AXP209_LDO24_LDO4_MASK 0x0f | |
| 60 | #define AXP209_LDO24_LDO2_SET(reg, cfg) \ | |
| 61 | (((reg) & ~AXP209_LDO24_LDO2_MASK) | \ | |
| 62 | (((cfg) << 4) & AXP209_LDO24_LDO2_MASK)) | |
| 63 | #define AXP209_LDO24_LDO4_SET(reg, cfg) \ | |
| 64 | (((reg) & ~AXP209_LDO24_LDO4_MASK) | \ | |
| 65 | (((cfg) << 0) & AXP209_LDO24_LDO4_MASK)) | |
| 66 | ||
| 67 | #define AXP209_LDO3_VOLTAGE_FROM_LDO3IN BIT(7) | |
| 68 | #define AXP209_LDO3_VOLTAGE_MASK 0x7f | |
| 69 | #define AXP209_LDO3_VOLTAGE_SET(x) ((x) & AXP209_LDO3_VOLTAGE_MASK) | |
| 70 | ||
| 048447ce OS |
71 | #define AXP209_IRQ5_PEK_UP BIT(6) |
| 72 | #define AXP209_IRQ5_PEK_DOWN BIT(5) | |
| 940382fe | 73 | |
| 048447ce | 74 | #define AXP209_POWEROFF BIT(7) |
| 940382fe | 75 | |
| 2fcf033d | 76 | /* For axp_gpio.c */ |
| 344df3ca | 77 | #ifdef CONFIG_AXP209_POWER |
| 2fcf033d | 78 | #define AXP_POWER_STATUS 0x00 |
| 78592c09 | 79 | #define AXP_POWER_STATUS_ALDO_IN BIT(0) |
| 2fcf033d HG |
80 | #define AXP_GPIO0_CTRL 0x90 |
| 81 | #define AXP_GPIO1_CTRL 0x92 | |
| 82 | #define AXP_GPIO2_CTRL 0x93 | |
| 048447ce OS |
83 | #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ |
| 84 | #define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ | |
| 85 | #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ | |
| 2fcf033d | 86 | #define AXP_GPIO_STATE 0x94 |
| 048447ce | 87 | #define AXP_GPIO_STATE_OFFSET 4 |
| 344df3ca | 88 | #endif |