[J-u-boot.git] / include / configs / C29XPCIE.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * C29XPCIE board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO

#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifdef CONFIG_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE		(128 << 10)
#define CONFIG_SPL_TEXT_BASE		0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE		0xff800000
#define CONFIG_SPL_MAX_SIZE		8192
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
#endif
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_TPL_PAD_TO		0x20000
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE		0x11001000
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0xeff40000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

/* High Level Configuration Options */
#define CONFIG_BOOKE			/* BOOKE */
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_FSL_IFC			/* Enable IFC Support */
#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */

#define CONFIG_PCI			/* Enable PCI/PCIE */
#ifdef CONFIG_PCI
#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_CMD_PCI


/*
 * PCI Windows
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif

#define CONFIG_FSL_LAW			/* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

#define CONFIG_DDR_CLK_FREQ	100000000
#define CONFIG_SYS_CLK_FREQ	66666666

#define CONFIG_HWCONFIG

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_ADDR_MAP			1
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */

#define CONFIG_SYS_MEMTEST_START	0x00200000
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_PANIC_HANG

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM		0
#define SPD_EEPROM_ADDRESS		0x50
#define CONFIG_SYS_DDR_RAW_TIMING

/* DDR ECC Setup*/
#define CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

#define CONFIG_SYS_SDRAM_SIZE		512
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* Platform SRAM setting  */
#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NO_FLASH
#endif

/*
 * IFC Definitions
 */
/* NOR Flash on IFC */
#define CONFIG_SYS_FLASH_BASE		0xec000000
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */

#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */

/* 16Bit NOR Flash - S29GL512S10TFI01 */
#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

/* CFI for NOR Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)

/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_NAND \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
				FTIM0_NAND_TWP(0x0c)   | \
				FTIM0_NAND_TWCHT(0x08) | \
				FTIM0_NAND_TWH(0x06))
#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
				FTIM1_NAND_TWBE(0x1d)  | \
				FTIM1_NAND_TRR(0x08)   | \
				FTIM1_NAND_TRP(0x0c))
#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
				FTIM2_NAND_TREH(0x0a) | \
				FTIM2_NAND_TWHRE(0x18))
#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))

#define CONFIG_SYS_NAND_DDR_LAW		11

/* Set up IFC registers for boot location NOR/NAND */
#ifdef CONFIG_NAND
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
					| CONFIG_SYS_CPLD_BASE)

#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2	0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
				FTIM0_GPCM_TEADC(0x0e) | \
				FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
				FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
				FTIM2_GPCM_TCH(0x8) | \
				FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3	0x0

#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#endif

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
#define CONFIG_SYS_INIT_RAM_END		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
						- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)

/*
 * Config the L2 Cache as L2 SRAM
 */
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#endif
#endif
#endif

/* Serial Port */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C EEPROM */
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_CMD_I2C

/* eSPI - Enhanced SPI */
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII			/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

/* Default mode is RGMII mode */
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		2

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_SIZE		0x2000
#endif
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
#endif
#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Command line configuration.
 */
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */

#define CONFIG_BAUDRATE		115200

#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"loadaddr=1000000\0"				\
	"consoledev=ttyS0\0"				\
	"ramdiskaddr=2000000\0"				\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
	"fdtaddr=c00000\0"				\
	"fdtfile=name/of/device-tree.dtb\0"			\
	"othbootargs=ramdisk_size=600000\0"		\

#define CONFIG_RAMBOOTCOMMAND			\
	"setenv bootargs root=/dev/ram rw "	\
	"console=$consoledev,$baudrate $othbootargs; "	\
	"tftp $ramdiskaddr $ramdiskfile;"	\
	"tftp $loadaddr $bootfile;"		\
	"tftp $fdtaddr $fdtfile;"		\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
a8d9758d MH	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
3aab0cd8	4	* SPDX-License-Identifier: GPL-2.0+
a8d9758d MH	5	*/
	6
	7	/*
	8	* C29XPCIE board configuration file
	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	#define CONFIG_PHYS_64BIT
9a7eeb9c	15	#define CONFIG_DISPLAY_BOARDINFO
a8d9758d MH	16
	17	#ifdef CONFIG_C29XPCIE
	18	#define CONFIG_PPC_C29X
	19	#endif
	20
	21	#ifdef CONFIG_SPIFLASH
	22	#define CONFIG_RAMBOOT_SPIFLASH
	23	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	24	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
a8d9758d MH	25	#endif
a8d9758d MH	26
eb6b458c	27	#ifdef CONFIG_NAND
eb6b458c PL	28	#ifdef CONFIG_TPL_BUILD
	29	#define CONFIG_SPL_NAND_BOOT
	30	#define CONFIG_SPL_FLUSH_IMAGE
	31	#define CONFIG_SPL_ENV_SUPPORT
	32	#define CONFIG_SPL_NAND_INIT
	33	#define CONFIG_SPL_SERIAL_SUPPORT
	34	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	35	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	36	#define CONFIG_SPL_I2C_SUPPORT
	37	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	38	#define CONFIG_SPL_NAND_SUPPORT
	39	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	40	#define CONFIG_SPL_COMMON_INIT_DDR
	41	#define CONFIG_SPL_MAX_SIZE (128 << 10)
	42	#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	43	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
e222b1f3	44	#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
eb6b458c PL	45	#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
	46	#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
	47	#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
	48	#elif defined(CONFIG_SPL_BUILD)
	49	#define CONFIG_SPL_INIT_MINIMAL
	50	#define CONFIG_SPL_SERIAL_SUPPORT
	51	#define CONFIG_SPL_NAND_SUPPORT
	52	#define CONFIG_SPL_NAND_MINIMAL
	53	#define CONFIG_SPL_FLUSH_IMAGE
	54	#define CONFIG_SPL_TEXT_BASE 0xff800000
	55	#define CONFIG_SPL_MAX_SIZE 8192
	56	#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
	57	#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
	58	#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
	59	#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
	60	#endif
	61	#define CONFIG_SPL_PAD_TO 0x20000
	62	#define CONFIG_TPL_PAD_TO 0x20000
	63	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	64	#define CONFIG_SYS_TEXT_BASE 0x11001000
	65	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	66	#endif
	67
a8d9758d	68	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	69	#define CONFIG_SYS_TEXT_BASE 0xeff40000
a8d9758d MH	70	#endif
	71
	72	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	73	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	74	#endif
	75
eb6b458c PL	76	#ifdef CONFIG_SPL_BUILD
	77	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	78	#else
	79	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	80	#endif
	81
	82	#ifdef CONFIG_SPL_BUILD
	83	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
a8d9758d MH	84	#endif
	85
	86	/* High Level Configuration Options */
	87	#define CONFIG_BOOKE /* BOOKE */
	88	#define CONFIG_E500 /* BOOKE e500 family */
a8d9758d	89	#define CONFIG_FSL_IFC /* Enable IFC Support */
737537ef	90	#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
a8d9758d MH	91	#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
	92
	93	#define CONFIG_PCI /* Enable PCI/PCIE */
	94	#ifdef CONFIG_PCI
	95	#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
	96	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	97	#define CONFIG_PCI_INDIRECT_BRIDGE
	98	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	99	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	100
a8d9758d MH	101	#define CONFIG_CMD_PCI
a8d9758d MH	102
a8d9758d MH	103
	104	/*
	105	* PCI Windows
	106	* Memory space is mapped 1-1, but I/O space must start from 0.
	107	*/
	108	/* controller 1, Slot 1, tgtid 1, Base address a000 */
	109	#define CONFIG_SYS_PCIE1_NAME "Slot 1"
	110	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	111	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	112	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	113	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
	114	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	115	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	116	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	117	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
	118
	119	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	120
	121	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	122	#define CONFIG_DOS_PARTITION
	123	#endif
	124
	125	#define CONFIG_FSL_LAW /* Use common FSL init code */
	126	#define CONFIG_TSEC_ENET
	127	#define CONFIG_ENV_OVERWRITE
	128
	129	#define CONFIG_DDR_CLK_FREQ 100000000
	130	#define CONFIG_SYS_CLK_FREQ 66666666
	131
	132	#define CONFIG_HWCONFIG
	133
	134	/*
	135	* These can be toggled for performance analysis, otherwise use default.
	136	*/
	137	#define CONFIG_L2_CACHE /* toggle L2 cache */
	138	#define CONFIG_BTB /* toggle branch predition */
	139
	140	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	141
	142	#define CONFIG_ENABLE_36BIT_PHYS
	143
	144	#define CONFIG_ADDR_MAP 1
	145	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	146
	147	#define CONFIG_SYS_MEMTEST_START 0x00200000
	148	#define CONFIG_SYS_MEMTEST_END 0x00400000
	149	#define CONFIG_PANIC_HANG
	150
	151	/* DDR Setup */
5614e71b	152	#define CONFIG_SYS_FSL_DDR3
a8d9758d MH	153	#define CONFIG_DDR_SPD
	154	#define CONFIG_SYS_SPD_BUS_NUM 0
	155	#define SPD_EEPROM_ADDRESS 0x50
	156	#define CONFIG_SYS_DDR_RAW_TIMING
	157
	158	/* DDR ECC Setup*/
	159	#define CONFIG_DDR_ECC
	160	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	161	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	162
	163	#define CONFIG_SYS_SDRAM_SIZE 512
	164	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	165	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	166
	167	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	168	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	169
	170	#define CONFIG_SYS_CCSRBAR 0xffe00000
	171	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	172
	173	/* Platform SRAM setting */
	174	#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
	175	#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
	176	(0xf00000000ull \| CONFIG_SYS_PLATFORM_SRAM_BASE)
	177	#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
	178
eb6b458c PL	179	#ifdef CONFIG_SPL_BUILD
	180	#define CONFIG_SYS_NO_FLASH
	181	#endif
	182
a8d9758d MH	183	/*
	184	* IFC Definitions
	185	*/
	186	/* NOR Flash on IFC */
	187	#define CONFIG_SYS_FLASH_BASE 0xec000000
	188	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	189
	190	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	191
	192	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	193	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	194
	195	#define CONFIG_SYS_FLASH_QUIET_TEST
	196	#define CONFIG_FLASH_SHOW_PROGRESS 45
	197	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
	198	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
	199
	200	/* 16Bit NOR Flash - S29GL512S10TFI01 */
	201	#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	202	CSPR_PORT_SIZE_16 \| \
	203	CSPR_MSEL_NOR \| \
	204	CSPR_V)
	205	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(6410241024)
	206	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
ac2785c6	207
a8d9758d MH	208	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	209	FTIM0_NOR_TEADC(0x5) \| \
	210	FTIM0_NOR_TEAHC(0x5))
ac2785c6 PL	211	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	212	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	213	FTIM1_NOR_TSEQRAD_NOR(0x13))
a8d9758d MH	214	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
a8d9758d MH	215	FTIM2_NOR_TCH(0x4) \| \
ac2785c6	216	FTIM2_NOR_TWPH(0x0E) \| \
a8d9758d MH	217	FTIM2_NOR_TWP(0x1c))
	218	#define CONFIG_SYS_NOR_FTIM3 0x0
	219
	220	/* CFI for NOR Flash */
	221	#define CONFIG_FLASH_CFI_DRIVER
	222	#define CONFIG_SYS_FLASH_CFI
	223	#define CONFIG_SYS_FLASH_EMPTY_INFO
	224	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	225
	226	/* NAND Flash on IFC */
	227	#define CONFIG_NAND_FSL_IFC
	228	#define CONFIG_SYS_NAND_BASE 0xff800000
	229	#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
	230
	231	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	232
	233	#define CONFIG_SYS_MAX_NAND_DEVICE 1
a8d9758d	234	#define CONFIG_CMD_NAND
eb6b458c	235	#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
a8d9758d MH	236
	237	/* 8Bit NAND Flash - K9F1G08U0B */
	238	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	239	\| CSPR_PORT_SIZE_8 \
	240	\| CSPR_MSEL_NAND \
	241	\| CSPR_V)
	242	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
affd520f	243	#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
a8d9758d MH	244	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	245	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	246	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
affd520f PK	247	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	248	\| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
	249	\| CSOR_NAND_SPRZ_CSOR_EXT /oob in csor_ext/\
	250	\| CSOR_NAND_PB(128)) /128 Pages Per Block/
a8d9758d MH	251	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) \| \
	252	FTIM0_NAND_TWP(0x0c) \| \
	253	FTIM0_NAND_TWCHT(0x08) \| \
	254	FTIM0_NAND_TWH(0x06))
	255	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) \| \
	256	FTIM1_NAND_TWBE(0x1d) \| \
	257	FTIM1_NAND_TRR(0x08) \| \
	258	FTIM1_NAND_TRP(0x0c))
	259	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) \| \
	260	FTIM2_NAND_TREH(0x0a) \| \
	261	FTIM2_NAND_TWHRE(0x18))
	262	#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
	263
	264	#define CONFIG_SYS_NAND_DDR_LAW 11
	265
	266	/* Set up IFC registers for boot location NOR/NAND */
eb6b458c PL	267	#ifdef CONFIG_NAND
	268	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	269	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	270	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	271	#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
	272	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	273	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	274	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	275	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	276	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	277	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	278	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	279	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	280	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	281	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	282	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	283	#else
a8d9758d MH	284	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	285	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	286	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	287	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	288	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	289	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	290	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	291	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	292	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	293	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
affd520f	294	#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
a8d9758d MH	295	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	296	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	297	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	298	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
eb6b458c	299	#endif
a8d9758d MH	300
	301	/* CPLD on IFC, selected by CS2 */
	302	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	303	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
	304	\| CONFIG_SYS_CPLD_BASE)
	305
	306	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
	307	\| CSPR_PORT_SIZE_8 \
	308	\| CSPR_MSEL_GPCM \
	309	\| CSPR_V)
	310	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	311	#define CONFIG_SYS_CSOR2 0x0
	312	/* CPLD Timing parameters for IFC CS2 */
	313	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	314	FTIM0_GPCM_TEADC(0x0e) \| \
	315	FTIM0_GPCM_TEAHC(0x0e))
	316	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	317	FTIM1_GPCM_TRAD(0x1f))
	318	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
de519163	319	FTIM2_GPCM_TCH(0x8) \| \
a8d9758d MH	320	FTIM2_GPCM_TWP(0x1f))
	321	#define CONFIG_SYS_CS2_FTIM3 0x0
	322
	323	#if defined(CONFIG_RAMBOOT_SPIFLASH)
	324	#define CONFIG_SYS_RAMBOOT
	325	#define CONFIG_SYS_EXTRA_ENV_RELOC
	326	#endif
	327
	328	#define CONFIG_BOARD_EARLY_INIT_R
	329
	330	#define CONFIG_SYS_INIT_RAM_LOCK
	331	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
	332	#define CONFIG_SYS_INIT_RAM_END 0x00004000
	333
	334	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
	335	- GENERATED_GBL_DATA_SIZE)
	336	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	337
9307cbab	338	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
eb6b458c PL	339	#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
	340
	341	/*
	342	* Config the L2 Cache as L2 SRAM
	343	*/
	344	#if defined(CONFIG_SPL_BUILD)
	345	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	346	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	347	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	348	#define CONFIG_SYS_L2_SIZE (256 << 10)
	349	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	350	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	351	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
	352	#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
	353	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
	354	#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
	355	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
	356	#elif defined(CONFIG_NAND)
	357	#ifdef CONFIG_TPL_BUILD
	358	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	359	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	360	#define CONFIG_SYS_L2_SIZE (256 << 10)
	361	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	362	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	363	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
	364	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
	365	#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
	366	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
	367	#else
	368	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	369	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	370	#define CONFIG_SYS_L2_SIZE (256 << 10)
	371	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	372	#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
	373	#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
	374	#endif
	375	#endif
	376	#endif
a8d9758d MH	377
	378	/* Serial Port */
	379	#define CONFIG_CONS_INDEX 1
a8d9758d MH	380	#define CONFIG_SYS_NS16550_SERIAL
	381	#define CONFIG_SYS_NS16550_REG_SIZE 1
	382	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	383
eb6b458c PL	384	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
	385	#define CONFIG_NS16550_MIN_FUNCTIONS
	386	#endif
	387
a8d9758d MH	388	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	389
	390	#define CONFIG_SYS_BAUDRATE_TABLE \
	391	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	392
	393	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	394	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	395
	396	/* Use the HUSH parser */
	397	#define CONFIG_SYS_HUSH_PARSER
	398
a8d9758d MH	399	#define CONFIG_SYS_I2C
	400	#define CONFIG_SYS_I2C_FSL
	401	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	402	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	403	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	404	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	405	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	406	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	407
	408	/* I2C EEPROM */
	409	/* enable read and write access to EEPROM */
	410	#define CONFIG_CMD_EEPROM
a8d9758d MH	411	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	412	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	413	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	414
	415	#define CONFIG_CMD_I2C
	416
	417	/* eSPI - Enhanced SPI */
a8d9758d MH	418	#define CONFIG_CMD_SF
	419	#define CONFIG_SF_DEFAULT_SPEED 10000000
	420	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	421
	422	#ifdef CONFIG_TSEC_ENET
a8d9758d MH	423	#define CONFIG_MII /* MII PHY management */
	424	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	425	#define CONFIG_TSEC1 1
	426	#define CONFIG_TSEC1_NAME "eTSEC1"
	427	#define CONFIG_TSEC2 1
	428	#define CONFIG_TSEC2_NAME "eTSEC2"
	429
	430	/* Default mode is RGMII mode */
	431	#define TSEC1_PHY_ADDR 0
	432	#define TSEC2_PHY_ADDR 2
	433
	434	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	435	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	436
	437	#define CONFIG_ETHPRIME "eTSEC1"
	438
	439	#define CONFIG_PHY_GIGE
	440	#endif /* CONFIG_TSEC_ENET */
	441
	442	/*
	443	* Environment
	444	*/
	445	#if defined(CONFIG_SYS_RAMBOOT)
	446	#if defined(CONFIG_RAMBOOT_SPIFLASH)
	447	#define CONFIG_ENV_IS_IN_SPI_FLASH
	448	#define CONFIG_ENV_SPI_BUS 0
	449	#define CONFIG_ENV_SPI_CS 0
	450	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	451	#define CONFIG_ENV_SPI_MODE 0
	452	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	453	#define CONFIG_ENV_SECT_SIZE 0x10000
	454	#define CONFIG_ENV_SIZE 0x2000
	455	#endif
eb6b458c PL	456	#elif defined(CONFIG_NAND)
	457	#define CONFIG_ENV_IS_IN_NAND
	458	#ifdef CONFIG_TPL_BUILD
	459	#define CONFIG_ENV_SIZE 0x2000
	460	#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	461	#else
	462	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	463	#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
	464	#endif
	465	#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
a8d9758d MH	466	#else
a8d9758d MH	467	#define CONFIG_ENV_IS_IN_FLASH
a8d9758d	468	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
a8d9758d MH	469	#define CONFIG_ENV_SIZE 0x2000
	470	#define CONFIG_ENV_SECT_SIZE 0x20000
	471	#endif
	472
	473	#define CONFIG_LOADS_ECHO
	474	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	475
	476	/*
	477	* Command line configuration.
	478	*/
a8d9758d	479	#define CONFIG_CMD_ERRATA
a8d9758d MH	480	#define CONFIG_CMD_IRQ
	481	#define CONFIG_CMD_MII
	482	#define CONFIG_CMD_PING
a8d9758d MH	483	#define CONFIG_CMD_REGINFO
a8d9758d MH	484
737537ef RG	485	/* Hash command with SHA acceleration supported in hardware */
	486	#ifdef CONFIG_FSL_CAAM
	487	#define CONFIG_CMD_HASH
	488	#define CONFIG_SHA_HW_ACCEL
	489	#endif
	490
a8d9758d MH	491	/*
	492	* Miscellaneous configurable options
	493	*/
	494	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	495	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	496	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	497	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
a8d9758d MH	498
	499	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	500	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	501	/* Print Buffer Size */
	502	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	503	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
a8d9758d MH	504
	505	/*
	506	* For booting Linux, the board info and command line data
	507	* have to be in the first 64 MB of memory, since this is
	508	* the maximum mapped by the Linux kernel during initialization.
	509	*/
	510	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
	511	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	512
	513	/*
	514	* Environment Configuration
	515	*/
	516
	517	#ifdef CONFIG_TSEC_ENET
	518	#define CONFIG_HAS_ETH0
	519	#define CONFIG_HAS_ETH1
	520	#endif
	521
	522	#define CONFIG_ROOTPATH "/opt/nfsroot"
	523	#define CONFIG_BOOTFILE "uImage"
	524	#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
	525
	526	/* default location for tftp and bootm */
	527	#define CONFIG_LOADADDR 1000000
	528
	529	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
	530
	531	#define CONFIG_BAUDRATE 115200
	532
9c25ee6d PL	533	#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
9c25ee6d PL	534
a8d9758d MH	535	#define CONFIG_EXTRA_ENV_SETTINGS \
	536	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
	537	"netdev=eth0\0" \
	538	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	539	"loadaddr=1000000\0" \
	540	"consoledev=ttyS0\0" \
	541	"ramdiskaddr=2000000\0" \
	542	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	543	"fdtaddr=c00000\0" \
	544	"fdtfile=name/of/device-tree.dtb\0" \
	545	"othbootargs=ramdisk_size=600000\0" \
	546
	547	#define CONFIG_RAMBOOTCOMMAND \
	548	"setenv bootargs root=/dev/ram rw " \
	549	"console=$consoledev,$baudrate $othbootargs; " \
	550	"tftp $ramdiskaddr $ramdiskfile;" \
	551	"tftp $loadaddr $bootfile;" \
	552	"tftp $fdtaddr $fdtfile;" \
	553	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	554
	555	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	556
3ca49c42 PL	557	#include <asm/fsl_secure_boot.h>
3ca49c42 PL	558
a8d9758d	559	#endif /* __CONFIG_H */