projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 06fd66a4 | 2 | /* |
| 3 | * Sysam AMCORE board configuration | |
| 4 | * | |
| 9deff607 | 5 | * (C) Copyright 2016 Angelo Dureghello <[email protected]> |
| 06fd66a4 | 6 | */ |
| 7 | ||
| 8 | #ifndef __AMCORE_CONFIG_H | |
| 9 | #define __AMCORE_CONFIG_H | |
| 10 | ||
| 5bc0543d | 11 | #define CONFIG_HOSTNAME "AMCORE" |
| 06fd66a4 | 12 | |
| 06fd66a4 | 13 | #define CONFIG_MCFTMR |
| 14 | #define CONFIG_MCFUART | |
| 15 | #define CONFIG_SYS_UART_PORT 0 | |
| 06fd66a4 | 16 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 17 | ||
| 06fd66a4 | 18 | #define CONFIG_BOOTCOMMAND "bootm ffc20000" |
| 9deff607 AD |
19 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 20 | "upgrade_uboot=loady; " \ | |
| 21 | "protect off 0xffc00000 0xffc1ffff; " \ | |
| 22 | "erase 0xffc00000 0xffc1ffff; " \ | |
| 23 | "cp.b 0x20000 0xffc00000 ${filesize}\0" \ | |
| 24 | "upgrade_kernel=loady; " \ | |
| 25 | "erase 0xffc20000 0xffefffff; " \ | |
| 26 | "cp.b 0x20000 0xffc20000 ${filesize}\0" \ | |
| 27 | "upgrade_jffs2=loady; " \ | |
| 28 | "erase 0xfff00000 0xffffffff; " \ | |
| 29 | "cp.b 0x20000 0xfff00000 ${filesize}\0" | |
| 06fd66a4 | 30 | |
| 06fd66a4 | 31 | /* undef to save memory */ |
| 06fd66a4 | 32 | |
| 06fd66a4 | 33 | #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ |
| 34 | ||
| 06fd66a4 | 35 | #define CONFIG_SYS_HZ 1000 |
| 36 | ||
| 37 | #define CONFIG_SYS_CLK 45000000 | |
| 38 | #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) | |
| 39 | /* Register Base Addrs */ | |
| 40 | #define CONFIG_SYS_MBAR 0x10000000 | |
| 41 | /* Definitions for initial stack pointer and data area (in DPRAM) */ | |
| 42 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 | |
| 43 | /* size of internal SRAM */ | |
| 44 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 | |
| 45 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 46 | GENERATED_GBL_DATA_SIZE) | |
| 47 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 48 | ||
| 49 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| 50 | #define CONFIG_SYS_SDRAM_SIZE 0x1000000 | |
| 51 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 | |
| 52 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 53 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 | |
| 54 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
| 55 | ||
| 06fd66a4 | 56 | /* amcore design has flash data bytes wired swapped */ |
| 57 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
| 58 | /* reserve 128-4KB */ | |
| 59 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
| 60 | #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) | |
| 61 | #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) | |
| 62 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) | |
| 63 | ||
| 5296cb1d | 64 | #define LDS_BOARD_TEXT \ |
| 0649cd0d SG |
65 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 66 | env/embedded.o(.text*); | |
| 5296cb1d | 67 | |
| 06fd66a4 | 68 | /* memory map space for linux boot data */ |
| 69 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
| 70 | ||
| 71 | /* | |
| 72 | * Cache Configuration | |
| 73 | * | |
| 74 | * Special 8K version 3 core cache. | |
| 75 | * This is a single unified instruction/data cache. | |
| 76 | * sdram - single region - no masks | |
| 77 | */ | |
| 78 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
| 79 | ||
| 80 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
| 81 | CONFIG_SYS_INIT_RAM_SIZE - 8) | |
| 82 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
| 83 | CONFIG_SYS_INIT_RAM_SIZE - 4) | |
| 84 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) | |
| 85 | #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ | |
| 86 | CF_ACR_EN) | |
| 87 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ | |
| 88 | CF_CACR_EC) | |
| 89 | ||
| 90 | /* CS0 - AMD Flash, address 0xffc00000 */ | |
| 91 | #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) | |
| 92 | /* 4MB, AA=0,V=1 C/I BIT for errata */ | |
| 93 | #define CONFIG_SYS_CS0_MASK 0x003f0001 | |
| 94 | /* WS=10, AA=1, PS=16bit (10) */ | |
| 95 | #define CONFIG_SYS_CS0_CTRL 0x1980 | |
| 96 | /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ | |
| 97 | #define CONFIG_SYS_CS1_BASE 0x3000 | |
| 98 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
| 99 | #define CONFIG_SYS_CS1_CTRL 0x0100 | |
| 100 | ||
| 101 | #endif /* __AMCORE_CONFIG_H */ | |
| 102 |