[J-u-boot.git] / include / configs / snapper9260.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Bluewater Systems Snapper 9260 and 9G20 modules
 *
 * (C) Copyright 2011 Bluewater Systems
 *   Author: Andre Renaud <[email protected]>
 *   Author: Ryan Mallon <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
#include <linux/sizes.h>

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

/* CPU */
#define CONFIG_ARCH_CPU_INIT

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 - \
					 GENERATED_GBL_DATA_SIZE)

/* Mem test settings */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))

/* NAND Flash */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
#define CONFIG_TFTP_TSIZE

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

/* GPIOs and IO expander */
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP		1
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR	0x28
#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x28, 16} }

/* UARTs/Serial console */
#define CONFIG_ATMEL_USART
#ifndef CONFIG_DM_SERIAL
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS
#endif

/* I2C - Bit-bashed */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	100000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define I2C_INIT do {							\
		at91_set_gpio_output(AT91_PIN_PA23, 1);			\
		at91_set_gpio_output(AT91_PIN_PA24, 1);			\
		at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1);	\
		at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1);	\
	} while (0)
#define I2C_SOFT_DECLARATIONS
#define I2C_ACTIVE
#define I2C_TRISTATE	at91_set_gpio_input(AT91_PIN_PA23, 1);
#define I2C_READ	at91_get_gpio_value(AT91_PIN_PA23);
#define I2C_SDA(bit) do {						\
		if (bit) {						\
			at91_set_gpio_input(AT91_PIN_PA23, 1);		\
		} else {						\
			at91_set_gpio_output(AT91_PIN_PA23, 1);		\
			at91_set_gpio_value(AT91_PIN_PA23, bit);	\
		}							\
	} while (0)
#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_DELAY	udelay(2)

/* Boot options */
#define CONFIG_SYS_LOAD_ADDR		0x23000000

#define CONFIG_BOOTP_BOOTFILESIZE

/* Environment settings */
#define CONFIG_ENV_OFFSET		(512 << 10)
#define CONFIG_ENV_SIZE			(256 << 10)
#define CONFIG_ENV_OVERWRITE

/* Console settings */

/* U-Boot memory settings */
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
b8d41dda RM	2	/*
	3	* Bluewater Systems Snapper 9260 and 9G20 modules
	4	*
	5	* (C) Copyright 2011 Bluewater Systems
	6	* Author: Andre Renaud <[email protected]>
	7	* Author: Ryan Mallon <[email protected]>
b8d41dda RM	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/* SoC type is defined in boards.cfg */
	14	#include <asm/hardware.h>
1ace4022	15	#include <linux/sizes.h>
b8d41dda	16
b8d41dda RM	17	/* ARM asynchronous clock */
	18	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
	19	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
b8d41dda RM	20
	21	/* CPU */
	22	#define CONFIG_ARCH_CPU_INIT
b8d41dda RM	23
	24	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	25	#define CONFIG_SETUP_MEMORY_TAGS
	26	#define CONFIG_INITRD_TAG
	27	#define CONFIG_SKIP_LOWLEVEL_INIT
b8d41dda RM	28
b8d41dda RM	29	/* SDRAM */
b8d41dda RM	30	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	31	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
	32	#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
	33	GENERATED_GBL_DATA_SIZE)
	34
	35	/* Mem test settings */
	36	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	37	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
	38
	39	/* NAND Flash */
b8d41dda RM	40	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	41	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	42	#define CONFIG_SYS_NAND_DBW_8
	43	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
	44	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
	45	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	46	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
	47
	48	/* Ethernet */
	49	#define CONFIG_MACB
	50	#define CONFIG_RMII
b8d41dda RM	51	#define CONFIG_NET_RETRY_COUNT 20
b8d41dda RM	52	#define CONFIG_RESET_PHY_R
4535a24c	53	#define CONFIG_AT91_WANTS_COMMON_PHY
b8d41dda RM	54	#define CONFIG_TFTP_PORT
	55	#define CONFIG_TFTP_TSIZE
	56
	57	/* USB */
	58	#define CONFIG_USB_ATMEL
dcd2f1a0	59	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
b8d41dda	60	#define CONFIG_USB_OHCI_NEW
b8d41dda RM	61	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	62	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
	63	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
	64	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
b8d41dda RM	65
b8d41dda RM	66	/* GPIOs and IO expander */
b8d41dda RM	67	#define CONFIG_ATMEL_LEGACY
	68	#define CONFIG_AT91_GPIO
	69	#define CONFIG_AT91_GPIO_PULLUP 1
	70	#define CONFIG_PCA953X
	71	#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
	72	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
	73
	74	/* UARTs/Serial console */
	75	#define CONFIG_ATMEL_USART
1a1927f3	76	#ifndef CONFIG_DM_SERIAL
b8d41dda RM	77	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
b8d41dda RM	78	#define CONFIG_USART_ID ATMEL_ID_SYS
1a1927f3	79	#endif
b8d41dda RM	80
b8d41dda RM	81	/* I2C - Bit-bashed */
ea818dbb HS	82	#define CONFIG_SYS_I2C
	83	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	84	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
	85	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
b8d41dda	86	#define CONFIG_SOFT_I2C_READ_REPEATED_START
b8d41dda RM	87	#define I2C_INIT do { \
	88	at91_set_gpio_output(AT91_PIN_PA23, 1); \
	89	at91_set_gpio_output(AT91_PIN_PA24, 1); \
	90	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	91	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
	92	} while (0)
	93	#define I2C_SOFT_DECLARATIONS
	94	#define I2C_ACTIVE
	95	#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
	96	#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
	97	#define I2C_SDA(bit) do { \
	98	if (bit) { \
	99	at91_set_gpio_input(AT91_PIN_PA23, 1); \
	100	} else { \
	101	at91_set_gpio_output(AT91_PIN_PA23, 1); \
	102	at91_set_gpio_value(AT91_PIN_PA23, bit); \
	103	} \
	104	} while (0)
	105	#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
	106	#define I2C_DELAY udelay(2)
	107
	108	/* Boot options */
	109	#define CONFIG_SYS_LOAD_ADDR 0x23000000
b8d41dda RM	110
b8d41dda RM	111	#define CONFIG_BOOTP_BOOTFILESIZE
b8d41dda RM	112
b8d41dda RM	113	/* Environment settings */
b8d41dda RM	114	#define CONFIG_ENV_OFFSET (512 << 10)
	115	#define CONFIG_ENV_SIZE (256 << 10)
	116	#define CONFIG_ENV_OVERWRITE
b8d41dda RM	117
b8d41dda RM	118	/* Console settings */
b8d41dda RM	119
	120	/* U-Boot memory settings */
	121	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
b8d41dda	122
b8d41dda	123	#endif /* __CONFIG_H */