[J-u-boot.git] / include / configs / km8360.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2012
 * Holger Brunck, Keymile GmbH Hannover, <[email protected]>
 * Christian Herzig, Keymile AG Switzerland, <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* KMBEC FPGA (PRIO) */
#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE	64

#if defined CONFIG_KMETER1
#define CONFIG_HOSTNAME		"kmeter1"
#define CONFIG_KM_BOARD_NAME   "kmeter1"
#define CONFIG_KM_DEF_NETDEV	"netdev=eth2\0"
#elif defined CONFIG_KMCOGE5NE
#define CONFIG_HOSTNAME		"kmcoge5ne"
#define CONFIG_KM_BOARD_NAME	"kmcoge5ne"
#define CONFIG_KM_DEF_NETDEV	"netdev=eth1\0"
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define NAND_MAX_CHIPS				1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */

#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
#else
#error ("Board not supported")
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_QE			/* Has QE */

/* include common defines/options for all 83xx Keymile boards */
#include "km83xx-common.h"

/*
 * System IO Setup
 */
#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)

/*
 * Hardware Reset Configuration Word
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_CSB_TO_CLKIN_4X1 | \
	HRCWL_CORE_TO_CSB_2X1 | \
	HRCWL_CE_PLL_VCO_DIV_2 | \
	HRCWL_CE_TO_PLL_1X6)

#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_CORE_ENABLE | \
	HRCWH_FROM_0X00000100 | \
	HRCWH_BOOTSEQ_DISABLE | \
	HRCWH_SW_WATCHDOG_DISABLE | \
	HRCWH_ROM_LOC_LOCAL_16BIT | \
	HRCWH_BIG_ENDIAN | \
	HRCWH_LALE_EARLY | \
	HRCWH_LDP_CLEAR)

/**
 * DDR RAM settings
 */
#define CONFIG_SYS_DDR_SDRAM_CFG (\
	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
	SDRAM_CFG_SREN | \
	SDRAM_CFG_HSE)

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000

#ifdef CONFIG_KMCOGE5NE
/**
 * KMCOGE5NE has 512 MB RAM
 */
#define CONFIG_SYS_DDR_CS0_CONFIG (\
	CSCONFIG_EN | \
	CSCONFIG_AP | \
	CSCONFIG_ODT_WR_ONLY_CURRENT | \
	CSCONFIG_BANK_BIT_3 | \
	CSCONFIG_ROW_BIT_13 | \
	CSCONFIG_COL_BIT_10)
#else
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
					 CSCONFIG_ROW_BIT_13 | \
					 CSCONFIG_COL_BIT_10 | \
					 CSCONFIG_ODT_WR_ONLY_CURRENT)
#endif

#define CONFIG_SYS_DDR_CLK_CNTL (\
	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CONFIG_SYS_DDR_INTERVAL (\
	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))

#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f

#define CONFIG_SYS_DDRCDR (\
	DDRCDR_EN | \
	DDRCDR_Q_DRN)
#define CONFIG_SYS_DDR_MODE		0x47860452
#define CONFIG_SYS_DDR_MODE2		0x8080c000

#define CONFIG_SYS_DDR_TIMING_0 (\
	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
	(0 << TIMING_CFG0_WWT_SHIFT) | \
	(0 << TIMING_CFG0_RRT_SHIFT) | \
	(0 << TIMING_CFG0_WRT_SHIFT) | \
	(0 << TIMING_CFG0_RWT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
				 (3 << TIMING_CFG1_PRETOACT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_2 (\
	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
	(5 << TIMING_CFG2_CPO_SHIFT) | \
	(0 << TIMING_CFG2_ADD_LAT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_3			0x00000000

/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_2
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4

/*
 * PAXE on the local bus CS3
 */
#define CONFIG_SYS_PAXE_BASE		0xA0000000
#define CONFIG_SYS_PAXE_SIZE		256

#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE

#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */

#define CONFIG_SYS_BR3_PRELIM (\
	CONFIG_SYS_PAXE_BASE | \
	(1 << BR_PS_SHIFT) | \
	BR_V)

#define CONFIG_SYS_OR3_PRELIM (\
	MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
	OR_GPCM_CSNT | \
	OR_GPCM_ACS_DIV2 | \
	OR_GPCM_SCY_2 | \
	OR_GPCM_TRLX | \
	OR_GPCM_EAD)

#ifdef CONFIG_KMCOGE5NE
/*
 * BFTIC3 on the local bus CS4
 */
#define CONFIG_SYS_BFTIC3_BASE			0xB0000000
#define CONFIG_SYS_BFTIC3_SIZE			256

#define CONFIG_SYS_BR4_PRELIM (\
	CONFIG_SYS_BFTIC3_BASE |\
	(1 << BR_PS_SHIFT) | \
	BR_V)

#define CONFIG_SYS_OR4_PRELIM (\
	MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
	OR_GPCM_CSNT | \
	OR_GPCM_ACS_DIV2 |\
	OR_GPCM_SCY_2 |\
	OR_GPCM_TRLX |\
	OR_GPCM_EAD)
#endif

/*
 * MMU Setup
 */

/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (\
	CONFIG_SYS_PAXE_BASE | \
	BATL_PP_10 | \
	BATL_MEMCOHERENCE)

#define CONFIG_SYS_IBAT5U (\
	CONFIG_SYS_PAXE_BASE | \
	BATU_BL_256M | \
	BATU_VS | \
	BATU_VP)

#define CONFIG_SYS_DBAT5L (\
	CONFIG_SYS_PAXE_BASE | \
	BATL_PP_10 | \
	BATL_CACHEINHIBIT | \
	BATL_GUARDEDSTORAGE)

#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

#ifdef CONFIG_KMCOGE5NE
/* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (\
	CONFIG_SYS_BFTIC3_BASE | \
	BATL_PP_10 | \
	BATL_MEMCOHERENCE)

#define CONFIG_SYS_IBAT6U (\
	CONFIG_SYS_BFTIC3_BASE | \
	BATU_BL_256M | \
	BATU_VS | \
	BATU_VP)

#define CONFIG_SYS_DBAT6L (\
	CONFIG_SYS_BFTIC3_BASE | \
	BATL_PP_10 | \
	BATL_CACHEINHIBIT | \
	BATL_GUARDEDSTORAGE)

#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U

/* DDR/LBC SDRAM next 256M: cacheable */
#define CONFIG_SYS_IBAT7L (\
	CONFIG_SYS_SDRAM_BASE2 |\
	BATL_PP_10 |\
	BATL_CACHEINHIBIT |\
	BATL_GUARDEDSTORAGE)

#define CONFIG_SYS_IBAT7U (\
	CONFIG_SYS_SDRAM_BASE2 |\
	BATU_BL_256M |\
	BATU_VS |\
	BATU_VP)
/* enable POST tests */
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
#define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
#define CONFIG_TESTPIN_REG  gprt3	/* for kmcoge5ne */
#define CONFIG_TESTPIN_MASK 0x20	/* for kmcoge5ne */

#else
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#endif

#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#endif /* CONFIG */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
0f2b721c HB	2	/*
	3	* (C) Copyright 2012
	4	* Holger Brunck, Keymile GmbH Hannover, <[email protected]>
	5	* Christian Herzig, Keymile AG Switzerland, <[email protected]>
0f2b721c HB	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/* KMBEC FPGA (PRIO) */
	12	#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
	13	#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
	14
	15	#if defined CONFIG_KMETER1
5bc0543d	16	#define CONFIG_HOSTNAME "kmeter1"
0f2b721c HB	17	#define CONFIG_KM_BOARD_NAME "kmeter1"
	18	#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
	19	#elif defined CONFIG_KMCOGE5NE
5bc0543d	20	#define CONFIG_HOSTNAME "kmcoge5ne"
0f2b721c HB	21	#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
0f2b721c HB	22	#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
be7576fa	23	#define CONFIG_NAND_ECC_BCH
0f2b721c HB	24	#define CONFIG_NAND_KMETER1
	25	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	26	#define NAND_MAX_CHIPS 1
	27	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
	28
	29	#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
	30	#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
0f2b721c HB	31	#else
	32	#error ("Board not supported")
	33	#endif
	34
	35	/*
	36	* High Level Configuration Options
	37	*/
	38	#define CONFIG_QE /* Has QE */
0f2b721c	39
0f2b721c	40	/* include common defines/options for all 83xx Keymile boards */
0921ea2b	41	#include "km83xx-common.h"
0f2b721c HB	42
	43	/*
	44	* System IO Setup
	45	*/
	46	#define CONFIG_SYS_SICRH (SICRH_UC1EOBI \| SICRH_UC2E1OBI)
	47
	48	/*
	49	* Hardware Reset Configuration Word
	50	*/
	51	#define CONFIG_SYS_HRCW_LOW (\
	52	HRCWL_CSB_TO_CLKIN_4X1 \| \
	53	HRCWL_CORE_TO_CSB_2X1 \| \
	54	HRCWL_CE_PLL_VCO_DIV_2 \| \
	55	HRCWL_CE_TO_PLL_1X6)
	56
	57	#define CONFIG_SYS_HRCW_HIGH (\
	58	HRCWH_CORE_ENABLE \| \
	59	HRCWH_FROM_0X00000100 \| \
	60	HRCWH_BOOTSEQ_DISABLE \| \
	61	HRCWH_SW_WATCHDOG_DISABLE \| \
	62	HRCWH_ROM_LOC_LOCAL_16BIT \| \
	63	HRCWH_BIG_ENDIAN \| \
	64	HRCWH_LALE_EARLY \| \
	65	HRCWH_LDP_CLEAR)
	66
	67	/**
	68	* DDR RAM settings
	69	*/
	70	#define CONFIG_SYS_DDR_SDRAM_CFG (\
	71	SDRAM_CFG_SDRAM_TYPE_DDR2 \| \
	72	SDRAM_CFG_SREN \| \
	73	SDRAM_CFG_HSE)
	74
	75	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
	76
	77	#ifdef CONFIG_KMCOGE5NE
	78	/**
	79	* KMCOGE5NE has 512 MB RAM
	80	*/
	81	#define CONFIG_SYS_DDR_CS0_CONFIG (\
	82	CSCONFIG_EN \| \
	83	CSCONFIG_AP \| \
22554ba1	84	CSCONFIG_ODT_WR_ONLY_CURRENT \| \
0f2b721c HB	85	CSCONFIG_BANK_BIT_3 \| \
	86	CSCONFIG_ROW_BIT_13 \| \
	87	CSCONFIG_COL_BIT_10)
	88	#else
	89	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \| CSCONFIG_AP \| \
	90	CSCONFIG_ROW_BIT_13 \| \
	91	CSCONFIG_COL_BIT_10 \| \
22554ba1	92	CSCONFIG_ODT_WR_ONLY_CURRENT)
0f2b721c HB	93	#endif
	94
	95	#define CONFIG_SYS_DDR_CLK_CNTL (\
	96	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	97
	98	#define CONFIG_SYS_DDR_INTERVAL (\
	99	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \| \
	100	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
	101
	102	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
	103
	104	#define CONFIG_SYS_DDRCDR (\
	105	DDRCDR_EN \| \
	106	DDRCDR_Q_DRN)
	107	#define CONFIG_SYS_DDR_MODE 0x47860452
	108	#define CONFIG_SYS_DDR_MODE2 0x8080c000
	109
	110	#define CONFIG_SYS_DDR_TIMING_0 (\
	111	(2 << TIMING_CFG0_MRS_CYC_SHIFT) \| \
	112	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \| \
	113	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \| \
	114	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \| \
	115	(0 << TIMING_CFG0_WWT_SHIFT) \| \
	116	(0 << TIMING_CFG0_RRT_SHIFT) \| \
	117	(0 << TIMING_CFG0_WRT_SHIFT) \| \
	118	(0 << TIMING_CFG0_RWT_SHIFT))
	119
	120	#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) \| \
	121	(2 << TIMING_CFG1_WRTORD_SHIFT) \| \
	122	(2 << TIMING_CFG1_ACTTOACT_SHIFT) \| \
	123	(3 << TIMING_CFG1_WRREC_SHIFT) \| \
	124	(7 << TIMING_CFG1_REFREC_SHIFT) \| \
	125	(3 << TIMING_CFG1_ACTTORW_SHIFT) \| \
	126	(8 << TIMING_CFG1_ACTTOPRE_SHIFT) \| \
	127	(3 << TIMING_CFG1_PRETOACT_SHIFT))
	128
	129	#define CONFIG_SYS_DDR_TIMING_2 (\
	130	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) \| \
	131	(3 << TIMING_CFG2_CKE_PLS_SHIFT) \| \
	132	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \| \
	133	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \| \
	134	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \| \
	135	(5 << TIMING_CFG2_CPO_SHIFT) \| \
	136	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
	137
	138	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	139
	140	/* EEprom support */
	141	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	142
	143	/*
	144	* Local Bus Configuration & Clock Setup
	145	*/
	146	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	147	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
	148	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
	149
	150	/*
	151	* PAXE on the local bus CS3
	152	*/
	153	#define CONFIG_SYS_PAXE_BASE 0xA0000000
	154	#define CONFIG_SYS_PAXE_SIZE 256
	155
	156	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
157
158	#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
159
160	#define CONFIG_SYS_BR3_PRELIM (\
161	CONFIG_SYS_PAXE_BASE \| \
162	(1 << BR_PS_SHIFT) \| \
163	BR_V)
164
165	#define CONFIG_SYS_OR3_PRELIM (\
166	MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) \| \
167	OR_GPCM_CSNT \| \
168	OR_GPCM_ACS_DIV2 \| \
169	OR_GPCM_SCY_2 \| \
170	OR_GPCM_TRLX \| \
171	OR_GPCM_EAD)
172
173	#ifdef CONFIG_KMCOGE5NE
174	/*
175	* BFTIC3 on the local bus CS4
176	*/
177	#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
178	#define CONFIG_SYS_BFTIC3_SIZE 256
179
180	#define CONFIG_SYS_BR4_PRELIM (\
181	CONFIG_SYS_BFTIC3_BASE \|\
182	(1 << BR_PS_SHIFT) \| \
183	BR_V)
184
185	#define CONFIG_SYS_OR4_PRELIM (\
186	MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) \|\
187	OR_GPCM_CSNT \| \
188	OR_GPCM_ACS_DIV2 \|\
189	OR_GPCM_SCY_2 \|\
190	OR_GPCM_TRLX \|\
191	OR_GPCM_EAD)
192	#endif
193
194	/*
195	* MMU Setup
196	*/
197
198	/* PAXE: icache cacheable, but dcache-inhibit and guarded */
199	#define CONFIG_SYS_IBAT5L (\
200	CONFIG_SYS_PAXE_BASE \| \
201	BATL_PP_10 \| \
202	BATL_MEMCOHERENCE)
203
204	#define CONFIG_SYS_IBAT5U (\
205	CONFIG_SYS_PAXE_BASE \| \
206	BATU_BL_256M \| \
207	BATU_VS \| \
208	BATU_VP)
209
210	#define CONFIG_SYS_DBAT5L (\
211	CONFIG_SYS_PAXE_BASE \| \
212	BATL_PP_10 \| \
213	BATL_CACHEINHIBIT \| \
214	BATL_GUARDEDSTORAGE)
215
216	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
217
0f2b721c HB	218	#ifdef CONFIG_KMCOGE5NE
	219	/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
	220	#define CONFIG_SYS_IBAT6L (\
	221	CONFIG_SYS_BFTIC3_BASE \| \
	222	BATL_PP_10 \| \
	223	BATL_MEMCOHERENCE)
	224
	225	#define CONFIG_SYS_IBAT6U (\
	226	CONFIG_SYS_BFTIC3_BASE \| \
	227	BATU_BL_256M \| \
	228	BATU_VS \| \
	229	BATU_VP)
	230
	231	#define CONFIG_SYS_DBAT6L (\
	232	CONFIG_SYS_BFTIC3_BASE \| \
	233	BATL_PP_10 \| \
	234	BATL_CACHEINHIBIT \| \
	235	BATL_GUARDEDSTORAGE)
	236
	237	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	238
	239	/* DDR/LBC SDRAM next 256M: cacheable */
	240	#define CONFIG_SYS_IBAT7L (\
	241	CONFIG_SYS_SDRAM_BASE2 \|\
	242	BATL_PP_10 \|\
	243	BATL_CACHEINHIBIT \|\
	244	BATL_GUARDEDSTORAGE)
	245
	246	#define CONFIG_SYS_IBAT7U (\
	247	CONFIG_SYS_SDRAM_BASE2 \|\
	248	BATU_BL_256M \|\
	249	BATU_VS \|\
	250	BATU_VP)
95209b66 TH	251	/* enable POST tests */
	252	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY\|CONFIG_SYS_POST_MEM_REGIONS)
	253	#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
	254	#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
	255	#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
	256	#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
95209b66	257
0f2b721c HB	258	#else
	259	#define CONFIG_SYS_IBAT6L (0)
	260	#define CONFIG_SYS_IBAT6U (0)
	261	#define CONFIG_SYS_IBAT7L (0)
	262	#define CONFIG_SYS_IBAT7U (0)
	263	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	264	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	265	#endif
	266
	267	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	268	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	269
	270	#endif /* CONFIG */