projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 991425fe | 2 | /* |
| 2ae18241 | 3 | * (C) Copyright 2006-2010 |
| 991425fe | 4 | * Wolfgang Denk, DENX Software Engineering, [email protected]. |
| 991425fe MB |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * mpc8349emds board configuration file | |
| 9 | * | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| 991425fe MB |
15 | /* |
| 16 | * High Level Configuration Options | |
| 17 | */ | |
| 18 | #define CONFIG_E300 1 /* E300 Family */ | |
| 991425fe | 19 | |
| 2ae18241 WD |
20 | #define CONFIG_PCI_66M |
| 21 | #ifdef CONFIG_PCI_66M | |
| 991425fe MB |
22 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
| 23 | #else | |
| 24 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
| 25 | #endif | |
| 26 | ||
| 447ad576 | 27 | #ifdef CONFIG_PCISLAVE |
| 447ad576 IS |
28 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ |
| 29 | #endif /* CONFIG_PCISLAVE */ | |
| 30 | ||
| 991425fe | 31 | #ifndef CONFIG_SYS_CLK_FREQ |
| 2ae18241 | 32 | #ifdef CONFIG_PCI_66M |
| 991425fe | 33 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 8fe9bf61 | 34 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
| 991425fe MB |
35 | #else |
| 36 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 8fe9bf61 | 37 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
| 991425fe MB |
38 | #endif |
| 39 | #endif | |
| 40 | ||
| 6d0f6bcf | 41 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 991425fe | 42 | |
| 32795eca | 43 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 6d0f6bcf JCPV |
44 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
| 45 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 991425fe MB |
46 | |
| 47 | /* | |
| 48 | * DDR Setup | |
| 49 | */ | |
| 8d172c0f | 50 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
| d326f4a2 | 51 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 991425fe MB |
52 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
| 53 | ||
| d4b91066 | 54 | /* |
| d26e34c4 YS |
55 | * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver |
| 56 | * unselect it to use old spd_sdram.c | |
| d4b91066 | 57 | */ |
| d4b91066 YS |
58 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 59 | #define SPD_EEPROM_ADDRESS1 0x52 | |
| 60 | #define SPD_EEPROM_ADDRESS2 0x51 | |
| d4b91066 YS |
61 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 62 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 63 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 64 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| d4b91066 | 65 | |
| dc9e499c RJ |
66 | /* |
| 67 | * 32-bit data path mode. | |
| cf48eb9a | 68 | * |
| dc9e499c RJ |
69 | * Please note that using this mode for devices with the real density of 64-bit |
| 70 | * effectively reduces the amount of available memory due to the effect of | |
| 71 | * wrapping around while translating address to row/columns, for example in the | |
| 72 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 73 | * 128MB); normally this define should be used for devices with real 32-bit | |
| cf48eb9a | 74 | * data path. |
| dc9e499c RJ |
75 | */ |
| 76 | #undef CONFIG_DDR_32BIT | |
| 77 | ||
| 32795eca JH |
78 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 79 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 6d0f6bcf | 80 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 32795eca JH |
81 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
| 82 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
| 991425fe MB |
83 | #undef CONFIG_DDR_2T_TIMING |
| 84 | ||
| 8d172c0f XX |
85 | /* |
| 86 | * DDRCDR - DDR Control Driver Register | |
| 87 | */ | |
| 6d0f6bcf | 88 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
| 8d172c0f | 89 | |
| 991425fe | 90 | #if defined(CONFIG_SPD_EEPROM) |
| dc9e499c RJ |
91 | /* |
| 92 | * Determine DDR configuration from I2C interface. | |
| 93 | */ | |
| 94 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
| 991425fe | 95 | #else |
| dc9e499c RJ |
96 | /* |
| 97 | * Manually set up DDR parameters | |
| 98 | */ | |
| 6d0f6bcf | 99 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| 8d172c0f | 100 | #if defined(CONFIG_DDR_II) |
| 6d0f6bcf | 101 | #define CONFIG_SYS_DDRCDR 0x80080001 |
| 32795eca | 102 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
| 6d0f6bcf | 103 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
| 32795eca JH |
104 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
| 105 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
| 106 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
| 107 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 108 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
| 6d0f6bcf JCPV |
109 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
| 110 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
| 32795eca | 111 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
| 6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
| 113 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
| 8d172c0f | 114 | #else |
| 2e651b24 | 115 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
| 32795eca JH |
116 | | CSCONFIG_ROW_BIT_13 \ |
| 117 | | CSCONFIG_COL_BIT_10) | |
| 6d0f6bcf JCPV |
118 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
| 119 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
| 32795eca | 120 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
| 6d0f6bcf | 121 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
| dc9e499c RJ |
122 | |
| 123 | #if defined(CONFIG_DDR_32BIT) | |
| 124 | /* set burst length to 8 for 32-bit data path */ | |
| 32795eca JH |
125 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 126 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
| dc9e499c RJ |
127 | #else |
| 128 | /* the default burst length is 4 - for 64-bit data path */ | |
| 32795eca JH |
129 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 130 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
| dc9e499c | 131 | #endif |
| 991425fe | 132 | #endif |
| 8d172c0f | 133 | #endif |
| 991425fe MB |
134 | |
| 135 | /* | |
| 136 | * SDRAM on the Local Bus | |
| 137 | */ | |
| 6d0f6bcf JCPV |
138 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 139 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 991425fe MB |
140 | |
| 141 | /* | |
| 142 | * FLASH on the Local Bus | |
| 143 | */ | |
| 6d0f6bcf | 144 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
| 32795eca | 145 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
| 991425fe | 146 | |
| 7d6a0982 JH |
147 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
| 148 | | BR_PS_16 /* 16 bit port */ \ | |
| 149 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
| 150 | | BR_V) /* valid */ | |
| 151 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 32795eca JH |
152 | | OR_UPM_XAM \ |
| 153 | | OR_GPCM_CSNT \ | |
| 154 | | OR_GPCM_ACS_DIV2 \ | |
| 155 | | OR_GPCM_XACS \ | |
| 156 | | OR_GPCM_SCY_15 \ | |
| 7d6a0982 JH |
157 | | OR_GPCM_TRLX_SET \ |
| 158 | | OR_GPCM_EHTR_SET \ | |
| 32795eca | 159 | | OR_GPCM_EAD) |
| 7d6a0982 | 160 | |
| 32795eca JH |
161 | /* window base at flash base */ |
| 162 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
| 7d6a0982 | 163 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
| 991425fe | 164 | |
| 32795eca JH |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 166 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 991425fe | 167 | |
| 6d0f6bcf JCPV |
168 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 169 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 170 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 991425fe | 171 | |
| 14d0a02a | 172 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 991425fe | 173 | |
| 6d0f6bcf JCPV |
174 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 175 | #define CONFIG_SYS_RAMBOOT | |
| 991425fe | 176 | #else |
| 6d0f6bcf | 177 | #undef CONFIG_SYS_RAMBOOT |
| 991425fe MB |
178 | #endif |
| 179 | ||
| 180 | /* | |
| 181 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
| 182 | */ | |
| 32795eca JH |
183 | #define CONFIG_SYS_BCSR 0xE2400000 |
| 184 | /* Access window base at BCSR base */ | |
| 185 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
| 7d6a0982 JH |
186 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
| 187 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
| 188 | | BR_PS_8 \ | |
| 189 | | BR_MS_GPCM \ | |
| 190 | | BR_V) | |
| 191 | /* 0x00000801 */ | |
| 192 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
| 193 | | OR_GPCM_XAM \ | |
| 194 | | OR_GPCM_CSNT \ | |
| 195 | | OR_GPCM_SCY_15 \ | |
| 196 | | OR_GPCM_TRLX_CLEAR \ | |
| 197 | | OR_GPCM_EHTR_CLEAR) | |
| 198 | /* 0xFFFFE8F0 */ | |
| 991425fe | 199 | |
| 6d0f6bcf | 200 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 32795eca JH |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
| 202 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
| 991425fe | 203 | |
| 32795eca JH |
204 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 205 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 6d0f6bcf | 206 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 991425fe | 207 | |
| 16c8c170 | 208 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| c8a90646 | 209 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
| 991425fe MB |
210 | |
| 211 | /* | |
| 212 | * Local Bus LCRR and LBCR regs | |
| 213 | * LCRR: DLL bypass, Clock divider is 4 | |
| 214 | * External Local Bus rate is | |
| 215 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 216 | */ | |
| 32795eca JH |
217 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 218 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
| 6d0f6bcf | 219 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 991425fe | 220 | |
| 8d172c0f XX |
221 | /* |
| 222 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
| 6d0f6bcf | 223 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
| 8d172c0f | 224 | */ |
| 6d0f6bcf | 225 | #undef CONFIG_SYS_LB_SDRAM |
| 991425fe | 226 | |
| 6d0f6bcf | 227 | #ifdef CONFIG_SYS_LB_SDRAM |
| 991425fe MB |
228 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
| 229 | /* | |
| 230 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 231 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 991425fe MB |
232 | * |
| 233 | * For BR2, need: | |
| 234 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 235 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 236 | * no parity checking = BR2[21:22] = 00 | |
| 237 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 238 | * Valid = BR[31] = 1 | |
| 239 | * | |
| 240 | * 0 4 8 12 16 20 24 28 | |
| 241 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
| 991425fe MB |
242 | */ |
| 243 | ||
| 7d6a0982 JH |
244 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 245 | | BR_PS_32 /* 32-bit port */ \ | |
| 246 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
| 247 | | BR_V) /* Valid */ | |
| 248 | /* 0xF0001861 */ | |
| 249 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
| 250 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
| 991425fe MB |
251 | |
| 252 | /* | |
| 6d0f6bcf | 253 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 991425fe MB |
254 | * |
| 255 | * For OR2, need: | |
| 256 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 257 | * XAM, OR2[17:18] = 11 | |
| 258 | * 9 columns OR2[19-21] = 010 | |
| 259 | * 13 rows OR2[23-25] = 100 | |
| 260 | * EAD set for extra time OR[31] = 1 | |
| 261 | * | |
| 262 | * 0 4 8 12 16 20 24 28 | |
| 263 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
| 264 | */ | |
| 265 | ||
| 7d6a0982 JH |
266 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
| 267 | | OR_SDRAM_XAM \ | |
| 268 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
| 269 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
| 270 | | OR_SDRAM_EAD) | |
| 271 | /* 0xFC006901 */ | |
| 991425fe | 272 | |
| 32795eca JH |
273 | /* LB sdram refresh timer, about 6us */ |
| 274 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
| 275 | /* LB refresh timer prescal, 266MHz/32 */ | |
| 276 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
| 991425fe | 277 | |
| 32795eca | 278 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
| 540dcf1c KG |
279 | | LSDMR_BSMA1516 \ |
| 280 | | LSDMR_RFCR8 \ | |
| 281 | | LSDMR_PRETOACT6 \ | |
| 282 | | LSDMR_ACTTORW3 \ | |
| 283 | | LSDMR_BL8 \ | |
| 284 | | LSDMR_WRC3 \ | |
| 32795eca | 285 | | LSDMR_CL3) |
| 991425fe MB |
286 | |
| 287 | /* | |
| 288 | * SDRAM Controller configuration sequence. | |
| 289 | */ | |
| 540dcf1c KG |
290 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 291 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 292 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 293 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
| 294 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
| 991425fe MB |
295 | #endif |
| 296 | ||
| 297 | /* | |
| 298 | * Serial Port | |
| 299 | */ | |
| 6d0f6bcf JCPV |
300 | #define CONFIG_SYS_NS16550_SERIAL |
| 301 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 302 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 991425fe | 303 | |
| 6d0f6bcf | 304 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 32795eca | 305 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 991425fe | 306 | |
| 6d0f6bcf JCPV |
307 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 308 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 991425fe | 309 | |
| 991425fe | 310 | /* I2C */ |
| 00f792e0 HS |
311 | #define CONFIG_SYS_I2C |
| 312 | #define CONFIG_SYS_I2C_FSL | |
| 313 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 314 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 315 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 316 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 317 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 318 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 319 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| 991425fe | 320 | |
| 80ddd226 | 321 | /* SPI */ |
| 80ddd226 | 322 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
| 80ddd226 BW |
323 | |
| 324 | /* GPIOs. Used as SPI chip selects */ | |
| 6d0f6bcf JCPV |
325 | #define CONFIG_SYS_GPIO1_PRELIM |
| 326 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
| 327 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
| 80ddd226 | 328 | |
| 991425fe | 329 | /* TSEC */ |
| 6d0f6bcf | 330 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 32795eca | 331 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
| 6d0f6bcf | 332 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
| 32795eca | 333 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
| 991425fe | 334 | |
| 8fe9bf61 | 335 | /* USB */ |
| 6d0f6bcf | 336 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
| 991425fe MB |
337 | |
| 338 | /* | |
| 339 | * General PCI | |
| 340 | * Addresses are mapped 1-1. | |
| 341 | */ | |
| 6d0f6bcf JCPV |
342 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 343 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 344 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 345 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 346 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 347 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 32795eca JH |
348 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 349 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 350 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 6d0f6bcf JCPV |
351 | |
| 352 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 353 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 354 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 355 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 356 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 357 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 32795eca JH |
358 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 359 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 360 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 991425fe MB |
361 | |
| 362 | #if defined(CONFIG_PCI) | |
| 363 | ||
| 8fe9bf61 | 364 | #define PCI_ONE_PCI1 |
| 991425fe MB |
365 | #if defined(PCI_64BIT) |
| 366 | #undef PCI_ALL_PCI1 | |
| 367 | #undef PCI_TWO_PCI1 | |
| 368 | #undef PCI_ONE_PCI1 | |
| 369 | #endif | |
| 370 | ||
| 162338e1 | 371 | #define CONFIG_83XX_PCI_STREAMING |
| 991425fe MB |
372 | |
| 373 | #undef CONFIG_EEPRO100 | |
| 374 | #undef CONFIG_TULIP | |
| 375 | ||
| 376 | #if !defined(CONFIG_PCI_PNP) | |
| 377 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 378 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 53677ef1 | 379 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 991425fe MB |
380 | #endif |
| 381 | ||
| 382 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 383 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 991425fe MB |
384 | |
| 385 | #endif /* CONFIG_PCI */ | |
| 386 | ||
| 387 | /* | |
| 388 | * TSEC configuration | |
| 389 | */ | |
| 991425fe MB |
390 | |
| 391 | #if defined(CONFIG_TSEC_ENET) | |
| 991425fe MB |
392 | |
| 393 | #define CONFIG_GMII 1 /* MII PHY management */ | |
| 32795eca | 394 | #define CONFIG_TSEC1 1 |
| 255a3577 | 395 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 32795eca | 396 | #define CONFIG_TSEC2 1 |
| 255a3577 | 397 | #define CONFIG_TSEC2_NAME "TSEC1" |
| 991425fe MB |
398 | #define TSEC1_PHY_ADDR 0 |
| 399 | #define TSEC2_PHY_ADDR 1 | |
| 400 | #define TSEC1_PHYIDX 0 | |
| 401 | #define TSEC2_PHYIDX 0 | |
| 3a79013e AF |
402 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 403 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 991425fe MB |
404 | |
| 405 | /* Options are: TSEC[0-1] */ | |
| 406 | #define CONFIG_ETHPRIME "TSEC0" | |
| 407 | ||
| 408 | #endif /* CONFIG_TSEC_ENET */ | |
| 409 | ||
| 410 | /* | |
| 411 | * Configure on-board RTC | |
| 412 | */ | |
| 32795eca JH |
413 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
| 414 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
| 991425fe MB |
415 | |
| 416 | /* | |
| 417 | * Environment | |
| 418 | */ | |
| 6d0f6bcf | 419 | #ifndef CONFIG_SYS_RAMBOOT |
| 32795eca JH |
420 | #define CONFIG_ENV_ADDR \ |
| 421 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 0e8d1586 JCPV |
422 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 423 | #define CONFIG_ENV_SIZE 0x2000 | |
| 991425fe MB |
424 | |
| 425 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
426 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 427 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 991425fe MB |
428 | |
| 429 | #else | |
| 6d0f6bcf | 430 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 431 | #define CONFIG_ENV_SIZE 0x2000 |
| 991425fe MB |
432 | #endif |
| 433 | ||
| 434 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 435 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 991425fe | 436 | |
| 659e2f67 JL |
437 | /* |
| 438 | * BOOTP options | |
| 439 | */ | |
| 440 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 659e2f67 | 441 | |
| 8ea5499a JL |
442 | /* |
| 443 | * Command line configuration. | |
| 444 | */ | |
| 8ea5499a | 445 | |
| 991425fe MB |
446 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 447 | ||
| 448 | /* | |
| 449 | * Miscellaneous configurable options | |
| 450 | */ | |
| 6d0f6bcf | 451 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 991425fe | 452 | |
| 991425fe MB |
453 | /* |
| 454 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 455 | * have to be in the first 256 MB of memory, since this is |
| 991425fe MB |
456 | * the maximum mapped by the Linux kernel during initialization. |
| 457 | */ | |
| 32795eca JH |
458 | /* Initial Memory map for Linux*/ |
| 459 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
| 63865278 | 460 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 991425fe | 461 | |
| 6d0f6bcf | 462 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 991425fe MB |
463 | |
| 464 | #if 1 /*528/264*/ | |
| 6d0f6bcf | 465 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
466 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 467 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 468 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
469 | HRCWL_VCO_1X2 |\ |
| 470 | HRCWL_CORE_TO_CSB_2X1) | |
| 471 | #elif 0 /*396/132*/ | |
| 6d0f6bcf | 472 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
473 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 474 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 475 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
476 | HRCWL_VCO_1X4 |\ |
| 477 | HRCWL_CORE_TO_CSB_3X1) | |
| 478 | #elif 0 /*264/132*/ | |
| 6d0f6bcf | 479 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
480 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 481 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 482 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
483 | HRCWL_VCO_1X4 |\ |
| 484 | HRCWL_CORE_TO_CSB_2X1) | |
| 485 | #elif 0 /*132/132*/ | |
| 6d0f6bcf | 486 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
487 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 488 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 489 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
490 | HRCWL_VCO_1X4 |\ |
| 491 | HRCWL_CORE_TO_CSB_1X1) | |
| 492 | #elif 0 /*264/264 */ | |
| 6d0f6bcf | 493 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
494 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 495 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 496 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
497 | HRCWL_VCO_1X4 |\ |
| 498 | HRCWL_CORE_TO_CSB_1X1) | |
| 499 | #endif | |
| 500 | ||
| 447ad576 | 501 | #ifdef CONFIG_PCISLAVE |
| 6d0f6bcf | 502 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 447ad576 IS |
503 | HRCWH_PCI_AGENT |\ |
| 504 | HRCWH_64_BIT_PCI |\ | |
| 505 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
| 506 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 507 | HRCWH_CORE_ENABLE |\ | |
| 508 | HRCWH_FROM_0X00000100 |\ | |
| 509 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 510 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 511 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 512 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 513 | HRCWH_TSEC2M_IN_GMII) |
| 447ad576 | 514 | #else |
| 991425fe | 515 | #if defined(PCI_64BIT) |
| 6d0f6bcf | 516 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
517 | HRCWH_PCI_HOST |\ |
| 518 | HRCWH_64_BIT_PCI |\ | |
| 519 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 520 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 521 | HRCWH_CORE_ENABLE |\ | |
| 522 | HRCWH_FROM_0X00000100 |\ | |
| 523 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 524 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 525 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 526 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 527 | HRCWH_TSEC2M_IN_GMII) |
| 991425fe | 528 | #else |
| 6d0f6bcf | 529 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
530 | HRCWH_PCI_HOST |\ |
| 531 | HRCWH_32_BIT_PCI |\ | |
| 532 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 533 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 534 | HRCWH_CORE_ENABLE |\ | |
| 535 | HRCWH_FROM_0X00000100 |\ | |
| 536 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 537 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 538 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 539 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 540 | HRCWH_TSEC2M_IN_GMII) |
| 447ad576 IS |
541 | #endif /* PCI_64BIT */ |
| 542 | #endif /* CONFIG_PCISLAVE */ | |
| 991425fe | 543 | |
| a5fe514e LN |
544 | /* |
| 545 | * System performance | |
| 546 | */ | |
| 6d0f6bcf | 547 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 32795eca | 548 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
| 6d0f6bcf JCPV |
549 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
| 550 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
| 551 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
| 552 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
| a5fe514e | 553 | |
| 991425fe | 554 | /* System IO Config */ |
| 3c9b1ee1 | 555 | #define CONFIG_SYS_SICRH 0 |
| 6d0f6bcf | 556 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
| 991425fe | 557 | |
| 6d0f6bcf | 558 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 32795eca JH |
559 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
| 560 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
| 991425fe | 561 | |
| 32795eca | 562 | /* #define CONFIG_SYS_HID0_FINAL (\ |
| 991425fe MB |
563 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 564 | HID0_ENABLE_M_BIT |\ | |
| 32795eca | 565 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
| 991425fe | 566 | |
| 6d0f6bcf | 567 | #define CONFIG_SYS_HID2 HID2_HBE |
| 31d82672 | 568 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 991425fe MB |
569 | |
| 570 | /* DDR @ 0x00000000 */ | |
| 32795eca | 571 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
| 72cd4087 | 572 | | BATL_PP_RW \ |
| 32795eca JH |
573 | | BATL_MEMCOHERENCE) |
| 574 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
| 575 | | BATU_BL_256M \ | |
| 576 | | BATU_VS \ | |
| 577 | | BATU_VP) | |
| 991425fe MB |
578 | |
| 579 | /* PCI @ 0x80000000 */ | |
| 580 | #ifdef CONFIG_PCI | |
| 842033e6 | 581 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 32795eca | 582 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
| 72cd4087 | 583 | | BATL_PP_RW \ |
| 32795eca JH |
584 | | BATL_MEMCOHERENCE) |
| 585 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
| 586 | | BATU_BL_256M \ | |
| 587 | | BATU_VS \ | |
| 588 | | BATU_VP) | |
| 589 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 72cd4087 | 590 | | BATL_PP_RW \ |
| 32795eca JH |
591 | | BATL_CACHEINHIBIT \ |
| 592 | | BATL_GUARDEDSTORAGE) | |
| 593 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 594 | | BATU_BL_256M \ | |
| 595 | | BATU_VS \ | |
| 596 | | BATU_VP) | |
| 991425fe | 597 | #else |
| 6d0f6bcf JCPV |
598 | #define CONFIG_SYS_IBAT1L (0) |
| 599 | #define CONFIG_SYS_IBAT1U (0) | |
| 600 | #define CONFIG_SYS_IBAT2L (0) | |
| 601 | #define CONFIG_SYS_IBAT2U (0) | |
| 991425fe MB |
602 | #endif |
| 603 | ||
| 8fe9bf61 | 604 | #ifdef CONFIG_MPC83XX_PCI2 |
| 32795eca | 605 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
| 72cd4087 | 606 | | BATL_PP_RW \ |
| 32795eca JH |
607 | | BATL_MEMCOHERENCE) |
| 608 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
| 609 | | BATU_BL_256M \ | |
| 610 | | BATU_VS \ | |
| 611 | | BATU_VP) | |
| 612 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 72cd4087 | 613 | | BATL_PP_RW \ |
| 32795eca JH |
614 | | BATL_CACHEINHIBIT \ |
| 615 | | BATL_GUARDEDSTORAGE) | |
| 616 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 617 | | BATU_BL_256M \ | |
| 618 | | BATU_VS \ | |
| 619 | | BATU_VP) | |
| 8fe9bf61 | 620 | #else |
| 6d0f6bcf JCPV |
621 | #define CONFIG_SYS_IBAT3L (0) |
| 622 | #define CONFIG_SYS_IBAT3U (0) | |
| 623 | #define CONFIG_SYS_IBAT4L (0) | |
| 624 | #define CONFIG_SYS_IBAT4U (0) | |
| 8fe9bf61 | 625 | #endif |
| 991425fe | 626 | |
| 8fe9bf61 | 627 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
| 32795eca | 628 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
| 72cd4087 | 629 | | BATL_PP_RW \ |
| 32795eca JH |
630 | | BATL_CACHEINHIBIT \ |
| 631 | | BATL_GUARDEDSTORAGE) | |
| 632 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
| 633 | | BATU_BL_256M \ | |
| 634 | | BATU_VS \ | |
| 635 | | BATU_VP) | |
| 991425fe | 636 | |
| 8fe9bf61 | 637 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| 32795eca | 638 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
| 72cd4087 JH |
639 | | BATL_PP_RW \ |
| 640 | | BATL_MEMCOHERENCE \ | |
| 641 | | BATL_GUARDEDSTORAGE) | |
| 32795eca JH |
642 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
| 643 | | BATU_BL_256M \ | |
| 644 | | BATU_VS \ | |
| 645 | | BATU_VP) | |
| 6d0f6bcf JCPV |
646 | |
| 647 | #define CONFIG_SYS_IBAT7L (0) | |
| 648 | #define CONFIG_SYS_IBAT7U (0) | |
| 649 | ||
| 650 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 651 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 652 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 653 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 654 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 655 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 656 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 657 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 658 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 659 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 660 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 661 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 662 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 663 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 664 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 665 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 991425fe | 666 | |
| 8ea5499a | 667 | #if defined(CONFIG_CMD_KGDB) |
| 991425fe | 668 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 991425fe MB |
669 | #endif |
| 670 | ||
| 671 | /* | |
| 672 | * Environment Configuration | |
| 673 | */ | |
| 674 | #define CONFIG_ENV_OVERWRITE | |
| 675 | ||
| 676 | #if defined(CONFIG_TSEC_ENET) | |
| 991425fe | 677 | #define CONFIG_HAS_ETH1 |
| 10327dc5 | 678 | #define CONFIG_HAS_ETH0 |
| 991425fe MB |
679 | #endif |
| 680 | ||
| 5bc0543d | 681 | #define CONFIG_HOSTNAME "mpc8349emds" |
| 8b3637c6 | 682 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
| b3f44c21 | 683 | #define CONFIG_BOOTFILE "uImage" |
| 991425fe | 684 | |
| 32795eca | 685 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
| 991425fe | 686 | |
| 991425fe | 687 | #define CONFIG_PREBOOT "echo;" \ |
| 32bf3d14 | 688 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| 991425fe MB |
689 | "echo" |
| 690 | ||
| 691 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 692 | "netdev=eth0\0" \ | |
| 693 | "hostname=mpc8349emds\0" \ | |
| 694 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 695 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 696 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 697 | "addip=setenv bootargs ${bootargs} " \ | |
| 698 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 699 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 700 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 701 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 702 | "bootm ${kernel_addr}\0" \ | |
| 703 | "flash_self=run ramargs addip addtty;" \ | |
| 704 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 705 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 706 | "bootm\0" \ | |
| 991425fe MB |
707 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
| 708 | "update=protect off fe000000 fe03ffff; " \ | |
| 32795eca | 709 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
| d8ab58b2 | 710 | "upd=run load update\0" \ |
| 79f516bc | 711 | "fdtaddr=780000\0" \ |
| cc861f71 | 712 | "fdtfile=mpc834x_mds.dtb\0" \ |
| 991425fe MB |
713 | "" |
| 714 | ||
| 32795eca JH |
715 | #define CONFIG_NFSBOOTCOMMAND \ |
| 716 | "setenv bootargs root=/dev/nfs rw " \ | |
| 717 | "nfsroot=$serverip:$rootpath " \ | |
| 718 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
| 719 | "$netdev:off " \ | |
| 720 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 721 | "tftp $loadaddr $bootfile;" \ | |
| 722 | "tftp $fdtaddr $fdtfile;" \ | |
| 723 | "bootm $loadaddr - $fdtaddr" | |
| bf0b542d KP |
724 | |
| 725 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 32795eca JH |
726 | "setenv bootargs root=/dev/ram rw " \ |
| 727 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 728 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 729 | "tftp $loadaddr $bootfile;" \ | |
| 730 | "tftp $fdtaddr $fdtfile;" \ | |
| 731 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| bf0b542d | 732 | |
| 991425fe MB |
733 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 734 | ||
| 735 | #endif /* __CONFIG_H */ |