[J-u-boot.git] / include / configs / M5253DEMO.h

/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser ([email protected])
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_ENV_OFFSET		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x1000
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x1000
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*);

/*
 * Command line configuration.
 */

#ifdef CONFIG_IDE
/* ATA */
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG
#	define CONFIG_DM9000_BYTE_SWAPPED

#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0xff800000 0xff82ffff;"	\
		"era 0xff800000 0xff82ffff;"		\
		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		"M5253DEMO"

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(8) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		0x007F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		0x00000001
#define CONFIG_SYS_CS1_CTRL		0x00003DD8

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
6af3a0ea	2	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6d33c6ac	3	* Hayden Fraser ([email protected])
6d33c6ac TL	4	*/
	5
	6	#ifndef _M5253DEMO_H
	7	#define _M5253DEMO_H
	8
6d33c6ac TL	9	#define CONFIG_MCFTMR
	10
	11	#define CONFIG_MCFUART
6d0f6bcf	12	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac TL	13
	14	#undef CONFIG_WATCHDOG /* disable watchdog */
	15
6d33c6ac TL	16
	17	/* Configuration for environment
	18	* Environment is embedded in u-boot in the second sector of the flash
	19	*/
	20	#ifdef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	21	# define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	22	# define CONFIG_ENV_SECT_SIZE 0x1000
6d33c6ac	23	#else
6d0f6bcf	24	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	25	# define CONFIG_ENV_SECT_SIZE 0x1000
6d33c6ac TL	26	#endif
6d33c6ac TL	27
5296cb1d	28	#define LDS_BOARD_TEXT \
0649cd0d SG	29	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	30	env/embedded.o(.text*);
5296cb1d	31
6d33c6ac TL	32	/*
	33	* Command line configuration.
	34	*/
6d33c6ac	35
fc843a02	36	#ifdef CONFIG_IDE
6d33c6ac	37	/* ATA */
6d33c6ac TL	38	# define CONFIG_IDE_RESET 1
	39	# define CONFIG_IDE_PREINIT 1
	40	# define CONFIG_ATAPI
	41	# undef CONFIG_LBA48
	42
6d0f6bcf JCPV	43	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	44	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	45
6d0f6bcf JCPV	46	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	47	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	48
6d0f6bcf JCPV	49	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	50	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	51	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	52	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	53	#endif
	54
	55	#define CONFIG_DRIVER_DM9000
	56	#ifdef CONFIG_DRIVER_DM9000
012522fe	57	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
6d33c6ac TL	58	# define DM9000_IO CONFIG_DM9000_BASE
	59	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	60	# undef CONFIG_DM9000_DEBUG
f73e7d67	61	# define CONFIG_DM9000_BYTE_SWAPPED
6d33c6ac	62
6d33c6ac TL	63	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	64
	65	# define CONFIG_EXTRA_ENV_SETTINGS \
	66	"netdev=eth0\0" \
5368c55d	67	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	68	"loadaddr=10000\0" \
	69	"u-boot=u-boot.bin\0" \
	70	"load=tftp ${loadaddr) ${u-boot}\0" \
	71	"upd=run load; run prog\0" \
ac265f7f TL	72	"prog=prot off 0xff800000 0xff82ffff;" \
ac265f7f TL	73	"era 0xff800000 0xff82ffff;" \
f26a2473	74	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
6d33c6ac TL	75	"save\0" \
	76	""
	77	#endif
	78
5bc0543d	79	#define CONFIG_HOSTNAME "M5253DEMO"
6d33c6ac	80
eec567a6	81	/* I2C */
00f792e0 HS	82	#define CONFIG_SYS_I2C
	83	#define CONFIG_SYS_I2C_FSL
	84	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	85	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	86	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
6d0f6bcf JCPV	87	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	88	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	89	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	90	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	91
6d0f6bcf	92	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	95	#define CONFIG_SYS_MEMTEST_END 0x380000
6d33c6ac	96
6d0f6bcf JCPV	97	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	98	#define CONFIG_SYS_FAST_CLK
	99	#ifdef CONFIG_SYS_FAST_CLK
	100	# define CONFIG_SYS_PLLCR 0x1243E054
	101	# define CONFIG_SYS_CLK 140000000
6d33c6ac	102	#else
6d0f6bcf JCPV	103	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	104	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	105	#endif
	106
	107	/*
	108	* Low Level Configuration Settings
	109	* (address mappings, register initial values, etc.)
	110	* You should know what you are doing if you make changes here.
	111	*/
	112
6d0f6bcf JCPV	113	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	114	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	115
	116	/*
	117	* Definitions for initial stack pointer and data area (in DPRAM)
	118	*/
6d0f6bcf	119	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	120	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	121	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	122	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	123
	124	/*
	125	* Start addresses for the final memory configuration
	126	* (Set up by the startup code)
6d0f6bcf	127	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	128	*/
6d0f6bcf JCPV	129	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	131
6d33c6ac TL	132	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	133	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	134	#else
6d0f6bcf	135	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	136	#endif
6d33c6ac TL	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_MONITOR_LEN 0x40000
	139	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	140	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	141
	142	/*
	143	* For booting Linux, the board info and command line data
	144	* have to be in the first 8 MB of memory, since this is
	145	* the maximum mapped by the Linux kernel during initialization ??
	146	*/
6d0f6bcf	147	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	148	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
6d33c6ac TL	149
6d33c6ac TL	150	/* FLASH organization */
012522fe	151	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
6d0f6bcf JCPV	152	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	153	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	154	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	155
	156	#define FLASH_SST6401B 0x200
	157	#define SST_ID_xF6401B 0x236D236D
	158
6d0f6bcf	159	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	160	/*
	161	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	162	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	163	* 0x30 is block erase in SST
	164	*/
6d0f6bcf JCPV	165	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	166	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	167	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	168	#else
6d0f6bcf JCPV	169	# define CONFIG_SYS_SST_SECT 2048
	170	# define CONFIG_SYS_SST_SECTSZ 0x1000
	171	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	172	#endif
	173
	174	/* Cache Configuration */
6d0f6bcf	175	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac	176
dd9f054e	177	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	178	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	179	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	180	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	181	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	182	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	183	CF_ADDRMASK(8) \| \
	184	CF_ACR_EN \| CF_ACR_SM_ALL)
	185	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	186	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	187	CF_ACR_EN \| CF_ACR_SM_ALL)
	188	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	189	CF_CACR_DBWE)
	190
6d33c6ac	191	/* Port configuration */
6d0f6bcf	192	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	193
012522fe TL	194	#define CONFIG_SYS_CS0_BASE 0xFF800000
	195	#define CONFIG_SYS_CS0_MASK 0x007F0021
	196	#define CONFIG_SYS_CS0_CTRL 0x00001D80
6d33c6ac	197
012522fe TL	198	#define CONFIG_SYS_CS1_BASE 0xE0000000
	199	#define CONFIG_SYS_CS1_MASK 0x00000001
	200	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
6d33c6ac TL	201
	202	/*-----------------------------------------------------------------------
	203	* Port configuration
	204	*/
6d0f6bcf JCPV	205	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	206	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	207	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	208	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	209	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	210	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	211	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	212
6d33c6ac TL	213	#endif /* _M5253DEMO_H */