[J-u-boot.git] / include / configs / VoVPN-GW.h

/*
 * (C) Copyright 2004
 * Elmeg Communications Systems GmbH, Juergen Selent ([email protected])
 *
 * Support for the Elmeg VoVPN Gateway Module
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* define cpu used */
#define	CONFIG_MPC8272			1

/* define busmode: 8260 */
#undef	CONFIG_BUSMODE_60x

#define	CONFIG_SYS_TEXT_BASE		0xfff00000

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#ifdef	CONFIG_CLKIN_66MHz
#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
#else
#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
#endif

/* call board_early_init_f */
#define	CONFIG_BOARD_EARLY_INIT_F	1

/* have misc_init_r() function */
#define CONFIG_MISC_INIT_R		1

/* have reset_phy_r() function */
#define CONFIG_RESET_PHY_R		1

/* have special reset function */
#define	CONFIG_HAVE_OWN_RESET		1

/* allow serial and ethaddr to be overwritten */
#define	CONFIG_ENV_OVERWRITE

/* watchdog disabled */
#undef	CONFIG_WATCHDOG

/* include support for bzip2 compressed images */
#undef	CONFIG_BZIP2

/* status led */
#undef	CONFIG_STATUS_LED		/* XXX jse */

/* vendor parameter protection */
#define CONFIG_ENV_OVERWRITE

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC
#undef	CONFIG_CONS_ON_SCC
#undef	CONFIG_CONS_NONE
#define	CONFIG_CONS_INDEX		1

/* serial port default baudrate */
#define CONFIG_BAUDRATE			115200

/* echo on for serial download	*/
#define CONFIG_LOADS_ECHO		1

/* don't allow baudrate change	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC
#define	CONFIG_ETHER_ON_FCC
#undef	CONFIG_ETHER_NONE

#ifdef	CONFIG_ETHER_ON_FCC

/* which SCC/FCC channel for ethernet */
#define	CONFIG_ETHER_INDEX		1

/* Marvell Switch SMI base addr */
#define CONFIG_SYS_PHY_ADDR			0x10

/* FCC1 RMII REFCLK is CLK10 */
#define CONFIG_SYS_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
#define CONFIG_SYS_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)

/* BDs and buffers on 60x bus */
#define CONFIG_SYS_CPMFCR_RAMTYPE		0

/* Local Protect, Full duplex, Flowcontrol, RMII */
#define CONFIG_SYS_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
					 FCC_PSMR_FCE|FCC_PSMR_RMII)

/* bit-bang MII PHY management	*/
#define CONFIG_BITBANGMII

#define MDIO_PORT			1		/* Port B */

#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE		MDIO_DECLARE

#define CONFIG_SYS_MDIO_PIN			0x00002000	/* PB18 */
#define CONFIG_SYS_MDC_PIN			0x00001000	/* PB19 */
#define MDIO_ACTIVE			(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
#define MDIO_TRISTATE			(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
#define MDIO_READ			((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
#define MDIO(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
					else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
#define MDC(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
					else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
#define MIIDELAY			udelay(1)

#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SOURCE


/*
 * boot options & environment
 */
#define CONFIG_BOOTDELAY		3
#define CONFIG_BOOTCOMMAND		"run flash_self"
#undef  CONFIG_BOOTARGS
#define	CONFIG_EXTRA_ENV_SETTINGS	\
"clean_nv=erase fff20000 ffffffff\0" \
"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
"fstype=cramfs\0" \
"rootpath=/root_fs\0" \
"uboot=PPC/u-boot.bin\0" \
"kernel=PPC/uImage\0" \
"kernel_addr=ffe00000\0" \
"fs=PPC/root_fs\0" \
"console=ttyS0\0" \
"netdev=eth0\0" \
"rootdev=31:3\0" \
"ethaddr=00:09:4f:01:02:03\0" \
"ipaddr=10.0.0.201\0" \
"netmask=255.255.255.0\0" \
"serverip=10.0.0.136\0" \
"gatewayip=10.0.0.10\0" \
"hostname=bastard\0" \
""


/*
 * miscellaneous configurable options
 */

/* undef to save memory */
#define	CONFIG_SYS_LONGHELP

/* monitor command prompt */

/* console i/o buffer size */
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE			1024
#else
#define	CONFIG_SYS_CBSIZE			256
#endif

/* print buffer size */
#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* max number of command args */
#define	CONFIG_SYS_MAXARGS			16

/* boot argument buffer size */
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START		0x00100000
/* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_MEMTEST_END			0x00f00000
/* full featured memtest */
#define CONFIG_SYS_ALT_MEMTEST

/* default load address */
#define	CONFIG_SYS_LOAD_ADDR			0x00100000

/* decrementer freq: 1 ms ticks	*/

/* configure flash */
#define CONFIG_SYS_FLASH_BASE			0xff800000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		64
#define CONFIG_SYS_FLASH_SIZE			8
#undef	CONFIG_SYS_FLASH_16BIT
#define CONFIG_SYS_FLASH_ERASE_TOUT		240000
#define CONFIG_SYS_FLASH_WRITE_TOUT		500
#define CONFIG_SYS_FLASH_LOCK_TOUT		500
#define CONFIG_SYS_FLASH_UNLOCK_TOUT		10000
#define CONFIG_SYS_FLASH_PROTECTION

/* monitor in flash */
#define CONFIG_SYS_MONITOR_OFFSET		0x00700000

/* environment in flash */
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00020000)
#define CONFIG_ENV_SIZE			0x00020000
#define CONFIG_ENV_SECT_SIZE		0x00020000

/*
 * Initial memory map for linux
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ			(8 << 20)

/* hard reset configuration words */
#ifdef	CONFIG_CLKIN_66MHz
#define CONFIG_SYS_HRCW_MASTER			0x04643050
#else
#error NO HRCW FOR 100MHZ SPECIFIED !!!
#endif
#define CONFIG_SYS_HRCW_SLAVE1			0x00000000
#define CONFIG_SYS_HRCW_SLAVE2			0x00000000
#define CONFIG_SYS_HRCW_SLAVE3			0x00000000
#define CONFIG_SYS_HRCW_SLAVE4			0x00000000
#define CONFIG_SYS_HRCW_SLAVE5			0x00000000
#define CONFIG_SYS_HRCW_SLAVE6			0x00000000
#define CONFIG_SYS_HRCW_SLAVE7			0x00000000

/* internal memory mapped register */
#define CONFIG_SYS_IMMR			0xF0000000

/* definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE			0x00000000
#define CONFIG_SYS_SDRAM_SIZE			(32*1024*1024)
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_FLASH		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
#define CONFIG_SYS_MONITOR_LEN			0x00020000
#define CONFIG_SYS_MALLOC_LEN			0x00020000

/* cache configuration */
#define CONFIG_SYS_CACHELINE_SIZE		32      /* for MPC8260 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT		5	/* log base 2 of above */
#endif

/*
 * HIDx - Hardware Implementation-dependent Registers
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT			(HID0_ICE|HID0_DCE|\
					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL			(HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2			0

/* RMR - reset mode register - turn on checkstop reset enable */
#define CONFIG_SYS_RMR				RMR_CSRE

/* BCR - bus configuration */
#define CONFIG_SYS_BCR				0x00000000

/* SIUMCR - siu module configuration */
#define CONFIG_SYS_SIUMCR			0x4905c000

/* SYPCR - system protection control */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR			0xffffff87
#else
#define CONFIG_SYS_SYPCR			0xffffff83
#endif

/* TMCNTSC - time counter status and control */
/* clear interrupts XXX jse */
/*#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
					 TMCNTSC_TCF|TMCNTSC_TCE)

/* PISCR - periodic interrupt status and control */
/* clear interrupts XXX jse */
/*#define CONFIG_SYS_PISCR			(PISCR_PS) */
#define CONFIG_SYS_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)

/* SCCR - system clock control */
#define CONFIG_SYS_SCCR			0x000001a9

/* RCCR - risc controller configuration */
#define CONFIG_SYS_RCCR			0

/*
 * MEMORY MAP
 * ----------
 * CS0 - FLASH    8MB/8Bit	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
 * CS1 - SDRAM   32MB/64Bit	base=0x00000000
 * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
 * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
 * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
 * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
 * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
 *  x  - IMMR     384KB		base=0xf0000000
 */
/* XXX jse 100MHz TODO */
#define CONFIG_SYS_BR0_PRELIM			0xff800801
#define CONFIG_SYS_OR0_PRELIM			0xff801e44
#define CONFIG_SYS_BR1_PRELIM			0x00000041
#define CONFIG_SYS_OR1_PRELIM			0xfe002ec0
#if 1
#define CONFIG_SYS_BR2_PRELIM			0xf0101001
#define CONFIG_SYS_OR2_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR3_PRELIM			0xf0201001
#define CONFIG_SYS_OR3_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR4_PRELIM			0xf0301001
#define CONFIG_SYS_OR4_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR5_PRELIM			0xf0401001
#define CONFIG_SYS_OR5_PRELIM			0xfff00ef4
#else
#define CONFIG_SYS_BR2_PRELIM			0xf0101081
#define CONFIG_SYS_OR2_PRELIM			0xfff00104
#define CONFIG_SYS_BR3_PRELIM			0xf0201081
#define CONFIG_SYS_OR3_PRELIM			0xfff00104
#define CONFIG_SYS_BR4_PRELIM			0xf0301081
#define CONFIG_SYS_OR4_PRELIM			0xfff00104
#define CONFIG_SYS_BR5_PRELIM			0xf0401081
#define CONFIG_SYS_OR5_PRELIM			0xfff00104
#endif
#define CONFIG_SYS_BR7_PRELIM			0xf0500881
#define CONFIG_SYS_OR7_PRELIM			0xffff8104
#define CONFIG_SYS_MPTPR			0x2700
#define CONFIG_SYS_PSDMR			0x822a2452	/* optimal */
/*#define CONFIG_SYS_PSDMR			0x822a48a3 */	/* relaxed */
#define CONFIG_SYS_PSRT			0x1a

/* "bad" address */
#define	CONFIG_SYS_RESET_ADDRESS		0x40000000

#endif	/* __CONFIG_H */
Commit	Line	Data
ba91e26a WD	1	/*
	2	* (C) Copyright 2004
	3	* Elmeg Communications Systems GmbH, Juergen Selent ([email protected])
	4	*
	5	* Support for the Elmeg VoVPN Gateway Module
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
ba91e26a WD	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/* define cpu used */
	14	#define CONFIG_MPC8272 1
	15
	16	/* define busmode: 8260 */
	17	#undef CONFIG_BUSMODE_60x
	18
2ae18241 WD	19	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	20
ba91e26a WD	21	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	22	#ifdef CONFIG_CLKIN_66MHz
	23	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	24	#else
	25	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
	26	#endif
	27
	28	/* call board_early_init_f */
	29	#define CONFIG_BOARD_EARLY_INIT_F 1
	30
	31	/* have misc_init_r() function */
	32	#define CONFIG_MISC_INIT_R 1
	33
	34	/* have reset_phy_r() function */
	35	#define CONFIG_RESET_PHY_R 1
	36
	37	/* have special reset function */
	38	#define CONFIG_HAVE_OWN_RESET 1
	39
	40	/* allow serial and ethaddr to be overwritten */
	41	#define CONFIG_ENV_OVERWRITE
	42
	43	/* watchdog disabled */
	44	#undef CONFIG_WATCHDOG
	45
	46	/* include support for bzip2 compressed images */
	47	#undef CONFIG_BZIP2
	48
	49	/* status led */
	50	#undef CONFIG_STATUS_LED /* XXX jse */
	51
	52	/* vendor parameter protection */
	53	#define CONFIG_ENV_OVERWRITE
	54
	55	/*
	56	* select serial console configuration
	57	*
	58	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	59	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	60	* for SCC).
	61	*/
	62	#define CONFIG_CONS_ON_SMC
	63	#undef CONFIG_CONS_ON_SCC
	64	#undef CONFIG_CONS_NONE
	65	#define CONFIG_CONS_INDEX 1
	66
	67	/* serial port default baudrate */
	68	#define CONFIG_BAUDRATE 115200
	69
	70	/* echo on for serial download */
	71	#define CONFIG_LOADS_ECHO 1
	72
	73	/* don't allow baudrate change */
6d0f6bcf	74	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
ba91e26a	75
ba91e26a WD	76	/*
	77	* select ethernet configuration
	78	*
	79	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	80	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	81	* for FCC)
	82	*
	83	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	84	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
ba91e26a WD	85	*/
	86	#undef CONFIG_ETHER_ON_SCC
	87	#define CONFIG_ETHER_ON_FCC
	88	#undef CONFIG_ETHER_NONE
	89
	90	#ifdef CONFIG_ETHER_ON_FCC
	91
	92	/* which SCC/FCC channel for ethernet */
	93	#define CONFIG_ETHER_INDEX 1
	94
	95	/* Marvell Switch SMI base addr */
6d0f6bcf	96	#define CONFIG_SYS_PHY_ADDR 0x10
ba91e26a WD	97
ba91e26a WD	98	/* FCC1 RMII REFCLK is CLK10 */
6d0f6bcf JCPV	99	#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
6d0f6bcf JCPV	100	#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1\|CMXFCR_TF1CS_MSK)
ba91e26a WD	101
ba91e26a WD	102	/* BDs and buffers on 60x bus */
6d0f6bcf	103	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
ba91e26a WD	104
ba91e26a WD	105	/* Local Protect, Full duplex, Flowcontrol, RMII */
6d0f6bcf	106	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB\|FCC_PSMR_FDE\|\
ba91e26a WD	107	FCC_PSMR_FCE\|FCC_PSMR_RMII)
	108
	109	/* bit-bang MII PHY management */
	110	#define CONFIG_BITBANGMII
	111
	112	#define MDIO_PORT 1 /* Port B */
be225442 LCM	113
	114	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	115	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	116	#define MDC_DECLARE MDIO_DECLARE
	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
	119	#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
	120	#define MDIO_ACTIVE (iop->pdir \|= CONFIG_SYS_MDIO_PIN)
	121	#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
	122	#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
	123	#define MDIO(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDIO_PIN; \
	124	else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
	125	#define MDC(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDC_PIN; \
	126	else iop->pdat &= ~CONFIG_SYS_MDC_PIN
ba91e26a WD	127	#define MIIDELAY udelay(1)
	128
	129	#endif
	130
a1aa0bb5 JL	131	/*
	132	* BOOTP options
	133	*/
	134	#define CONFIG_BOOTP_BOOTFILESIZE
	135	#define CONFIG_BOOTP_BOOTPATH
	136	#define CONFIG_BOOTP_GATEWAY
	137	#define CONFIG_BOOTP_HOSTNAME
	138
	139
a5562901 JL	140	/*
	141	* Command line configuration.
	142	*/
	143
a5562901 JL	144	#define CONFIG_CMD_BDI
	145	#define CONFIG_CMD_CONSOLE
	146	#define CONFIG_CMD_ECHO
a5562901 JL	147	#define CONFIG_CMD_FLASH
	148	#define CONFIG_CMD_IMI
	149	#define CONFIG_CMD_IMLS
	150	#define CONFIG_CMD_LOADB
	151	#define CONFIG_CMD_MEMORY
	152	#define CONFIG_CMD_MISC
	153	#define CONFIG_CMD_NET
	154	#define CONFIG_CMD_PING
	155	#define CONFIG_CMD_RUN
74de7aef WD	156	#define CONFIG_CMD_SAVEENV
74de7aef WD	157	#define CONFIG_CMD_SOURCE
a5562901	158
ba91e26a WD	159
	160	/*
	161	* boot options & environment
	162	*/
	163	#define CONFIG_BOOTDELAY 3
	164	#define CONFIG_BOOTCOMMAND "run flash_self"
	165	#undef CONFIG_BOOTARGS
	166	#define CONFIG_EXTRA_ENV_SETTINGS \
	167	"clean_nv=erase fff20000 ffffffff\0" \
fe126d8b WD	168	"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
	169	"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
	170	"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
	171	"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
	172	"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
	173	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
	174	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
	175	"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
	176	"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
	177	"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
	178	"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
	179	"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
ba91e26a WD	180	"fstype=cramfs\0" \
	181	"rootpath=/root_fs\0" \
	182	"uboot=PPC/u-boot.bin\0" \
	183	"kernel=PPC/uImage\0" \
	184	"kernel_addr=ffe00000\0" \
	185	"fs=PPC/root_fs\0" \
	186	"console=ttyS0\0" \
	187	"netdev=eth0\0" \
	188	"rootdev=31:3\0" \
	189	"ethaddr=00:09:4f:01:02:03\0" \
	190	"ipaddr=10.0.0.201\0" \
	191	"netmask=255.255.255.0\0" \
	192	"serverip=10.0.0.136\0" \
	193	"gatewayip=10.0.0.10\0" \
	194	"hostname=bastard\0" \
	195	""
	196
	197
	198	/*
	199	* miscellaneous configurable options
	200	*/
	201
	202	/* undef to save memory */
6d0f6bcf	203	#define CONFIG_SYS_LONGHELP
ba91e26a WD	204
ba91e26a WD	205	/* monitor command prompt */
ba91e26a WD	206
ba91e26a WD	207	/* console i/o buffer size */
a5562901	208	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	209	#define CONFIG_SYS_CBSIZE 1024
ba91e26a	210	#else
6d0f6bcf	211	#define CONFIG_SYS_CBSIZE 256
ba91e26a WD	212	#endif
	213
	214	/* print buffer size */
6d0f6bcf	215	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
ba91e26a WD	216
ba91e26a WD	217	/* max number of command args */
6d0f6bcf	218	#define CONFIG_SYS_MAXARGS 16
ba91e26a WD	219
ba91e26a WD	220	/* boot argument buffer size */
6d0f6bcf	221	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
ba91e26a WD	222
ba91e26a WD	223	/* memtest works on */
6d0f6bcf	224	#define CONFIG_SYS_MEMTEST_START 0x00100000
ba91e26a	225	/* 1 ... 15 MB in DRAM */
6d0f6bcf	226	#define CONFIG_SYS_MEMTEST_END 0x00f00000
ba91e26a	227	/* full featured memtest */
6d0f6bcf	228	#define CONFIG_SYS_ALT_MEMTEST
ba91e26a WD	229
ba91e26a WD	230	/* default load address */
6d0f6bcf	231	#define CONFIG_SYS_LOAD_ADDR 0x00100000
ba91e26a WD	232
ba91e26a WD	233	/* decrementer freq: 1 ms ticks */
ba91e26a WD	234
ba91e26a WD	235	/* configure flash */
6d0f6bcf JCPV	236	#define CONFIG_SYS_FLASH_BASE 0xff800000
	237	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	238	#define CONFIG_SYS_MAX_FLASH_SECT 64
	239	#define CONFIG_SYS_FLASH_SIZE 8
	240	#undef CONFIG_SYS_FLASH_16BIT
	241	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	242	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	243	#define CONFIG_SYS_FLASH_LOCK_TOUT 500
	244	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
	245	#define CONFIG_SYS_FLASH_PROTECTION
ba91e26a WD	246
ba91e26a WD	247	/* monitor in flash */
6d0f6bcf	248	#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
ba91e26a WD	249
ba91e26a WD	250	/* environment in flash */
5a1aceb0	251	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	252	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
0e8d1586 JCPV	253	#define CONFIG_ENV_SIZE 0x00020000
0e8d1586 JCPV	254	#define CONFIG_ENV_SECT_SIZE 0x00020000
ba91e26a WD	255
	256	/*
	257	* Initial memory map for linux
	258	* For booting Linux, the board info and command line data
	259	* have to be in the first 8 MB of memory, since this is
	260	* the maximum mapped by the Linux kernel during initialization.
	261	*/
6d0f6bcf	262	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
ba91e26a WD	263
	264	/* hard reset configuration words */
	265	#ifdef CONFIG_CLKIN_66MHz
6d0f6bcf	266	#define CONFIG_SYS_HRCW_MASTER 0x04643050
ba91e26a WD	267	#else
	268	#error NO HRCW FOR 100MHZ SPECIFIED !!!
	269	#endif
6d0f6bcf JCPV	270	#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
	271	#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
	272	#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
	273	#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
	274	#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
	275	#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
	276	#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
ba91e26a WD	277
ba91e26a WD	278	/* internal memory mapped register */
6d0f6bcf	279	#define CONFIG_SYS_IMMR 0xF0000000
ba91e26a WD	280
ba91e26a WD	281	/* definitions for initial stack pointer and data area (in DPRAM) */
6d0f6bcf	282	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	283	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
25ddd1fb	284	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	285	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
ba91e26a WD	286
	287	/*
	288	* Start addresses for the final memory configuration
	289	* (Set up by the startup code)
6d0f6bcf	290	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
ba91e26a	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	293	#define CONFIG_SYS_SDRAM_SIZE (3210241024)
14d0a02a	294	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	295	#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
	296	#define CONFIG_SYS_MONITOR_LEN 0x00020000
	297	#define CONFIG_SYS_MALLOC_LEN 0x00020000
ba91e26a	298
ba91e26a	299	/* cache configuration */
6d0f6bcf	300	#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
a5562901	301	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	302	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
ba91e26a WD	303	#endif
	304
	305	/*
	306	* HIDx - Hardware Implementation-dependent Registers
	307	*-----------------------------------------------------------------------
	308	* HID0 also contains cache control - initially enable both caches and
	309	* invalidate contents, then the final state leaves only the instruction
	310	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	311	* but Soft reset does not.
	312	*
	313	* HID1 has only read-only information - nothing to set.
	314	*/
6d0f6bcf	315	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|\
ba91e26a	316	HID0_ICFI\|HID0_DCI\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	317	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	318	#define CONFIG_SYS_HID2 0
ba91e26a WD	319
ba91e26a WD	320	/* RMR - reset mode register - turn on checkstop reset enable */
6d0f6bcf	321	#define CONFIG_SYS_RMR RMR_CSRE
ba91e26a WD	322
ba91e26a WD	323	/* BCR - bus configuration */
6d0f6bcf	324	#define CONFIG_SYS_BCR 0x00000000
ba91e26a WD	325
ba91e26a WD	326	/* SIUMCR - siu module configuration */
6d0f6bcf	327	#define CONFIG_SYS_SIUMCR 0x4905c000
ba91e26a WD	328
	329	/* SYPCR - system protection control */
	330	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	331	#define CONFIG_SYS_SYPCR 0xffffff87
ba91e26a	332	#else
6d0f6bcf	333	#define CONFIG_SYS_SYPCR 0xffffff83
ba91e26a WD	334	#endif
	335
	336	/* TMCNTSC - time counter status and control */
	337	/* clear interrupts XXX jse */
6d0f6bcf JCPV	338	/#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR) /
6d0f6bcf JCPV	339	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|\
ba91e26a WD	340	TMCNTSC_TCF\|TMCNTSC_TCE)
	341
	342	/* PISCR - periodic interrupt status and control */
	343	/* clear interrupts XXX jse */
6d0f6bcf JCPV	344	/#define CONFIG_SYS_PISCR (PISCR_PS) /
6d0f6bcf JCPV	345	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
ba91e26a WD	346
ba91e26a WD	347	/* SCCR - system clock control */
6d0f6bcf	348	#define CONFIG_SYS_SCCR 0x000001a9
ba91e26a WD	349
ba91e26a WD	350	/* RCCR - risc controller configuration */
6d0f6bcf	351	#define CONFIG_SYS_RCCR 0
ba91e26a WD	352
	353	/*
	354	* MEMORY MAP
	355	* ----------
53677ef1	356	* CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
ba91e26a WD	357	* CS1 - SDRAM 32MB/64Bit base=0x00000000
	358	* CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
	359	* CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
	360	* CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
	361	* CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
	362	* CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
	363	* x - IMMR 384KB base=0xf0000000
	364	*/
	365	/* XXX jse 100MHz TODO */
6d0f6bcf JCPV	366	#define CONFIG_SYS_BR0_PRELIM 0xff800801
	367	#define CONFIG_SYS_OR0_PRELIM 0xff801e44
	368	#define CONFIG_SYS_BR1_PRELIM 0x00000041
	369	#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
ba91e26a	370	#if 1
6d0f6bcf JCPV	371	#define CONFIG_SYS_BR2_PRELIM 0xf0101001
	372	#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
	373	#define CONFIG_SYS_BR3_PRELIM 0xf0201001
	374	#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
	375	#define CONFIG_SYS_BR4_PRELIM 0xf0301001
	376	#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
	377	#define CONFIG_SYS_BR5_PRELIM 0xf0401001
	378	#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
ba91e26a	379	#else
6d0f6bcf JCPV	380	#define CONFIG_SYS_BR2_PRELIM 0xf0101081
	381	#define CONFIG_SYS_OR2_PRELIM 0xfff00104
	382	#define CONFIG_SYS_BR3_PRELIM 0xf0201081
	383	#define CONFIG_SYS_OR3_PRELIM 0xfff00104
	384	#define CONFIG_SYS_BR4_PRELIM 0xf0301081
	385	#define CONFIG_SYS_OR4_PRELIM 0xfff00104
	386	#define CONFIG_SYS_BR5_PRELIM 0xf0401081
	387	#define CONFIG_SYS_OR5_PRELIM 0xfff00104
ba91e26a	388	#endif
6d0f6bcf JCPV	389	#define CONFIG_SYS_BR7_PRELIM 0xf0500881
	390	#define CONFIG_SYS_OR7_PRELIM 0xffff8104
	391	#define CONFIG_SYS_MPTPR 0x2700
	392	#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
	393	/#define CONFIG_SYS_PSDMR 0x822a48a3 / /* relaxed */
	394	#define CONFIG_SYS_PSRT 0x1a
ba91e26a WD	395
ba91e26a WD	396	/* "bad" address */
6d0f6bcf	397	#define CONFIG_SYS_RESET_ADDRESS 0x40000000
ba91e26a WD	398
ba91e26a WD	399	#endif /* __CONFIG_H */