[J-u-boot.git] / drivers / i2c / imx_lpi2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Freescale Semiconductors, Inc.
 */

#include <errno.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <imx_lpi2c.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
#include <dm/device_compat.h>

#define LPI2C_FIFO_SIZE 4
#define LPI2C_NACK_TOUT_MS 1
#define LPI2C_TIMEOUT_MS 100

static int bus_i2c_init(struct udevice *bus, int speed);

/* Weak linked function for overridden by some SoC power function */
int __weak init_i2c_power(unsigned i2c_num)
{
	return 0;
}

static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 status;

	status = readl(&regs->msr);

	if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
		result = LPI2C_BUSY;

	return result;
}

static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 val, status;

	status = readl(&regs->msr);
	/* errors to check for */
	status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
		LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;

	if (status) {
		if (status & LPI2C_MSR_PLTF_MASK)
			result = LPI2C_PIN_LOW_TIMEOUT_ERR;
		else if (status & LPI2C_MSR_ALF_MASK)
			result = LPI2C_ARB_LOST_ERR;
		else if (status & LPI2C_MSR_NDF_MASK)
			result = LPI2C_NAK_ERR;
		else if (status & LPI2C_MSR_FEF_MASK)
			result = LPI2C_FIFO_ERR;

		/* clear status flags */
		writel(0x7f00, &regs->msr);
		/* reset fifos */
		val = readl(&regs->mcr);
		val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
		writel(val, &regs->mcr);
	}

	return result;
}

static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 txcount = 0;
	ulong start_time = get_timer(0);

	do {
		txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
		txcount = LPI2C_FIFO_SIZE - txcount;
		result = imx_lpci2c_check_clear_error(regs);
		if (result) {
			debug("i2c: wait for tx ready: result 0x%x\n", result);
			return result;
		}
		if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
			debug("i2c: wait for tx ready: timeout\n");
			return -1;
		}
	} while (!txcount);

	return result;
}

static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	lpi2c_status_t result = LPI2C_SUCESS;

	/* empty tx */
	if (!len)
		return result;

	while (len--) {
		result = bus_i2c_wait_for_tx_ready(regs);
		if (result) {
			debug("i2c: send wait for tx ready: %d\n", result);
			return result;
		}
		writel(*txbuf++, &regs->mtdr);
	}

	return result;
}

static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 val;
	ulong start_time = get_timer(0);

	/* empty read */
	if (!len)
		return result;

	result = bus_i2c_wait_for_tx_ready(regs);
	if (result) {
		debug("i2c: receive wait fot tx ready: %d\n", result);
		return result;
	}

	/* clear all status flags */
	writel(0x7f00, &regs->msr);
	/* send receive command */
	val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
	writel(val, &regs->mtdr);

	while (len--) {
		do {
			result = imx_lpci2c_check_clear_error(regs);
			if (result) {
				debug("i2c: receive check clear error: %d\n",
				      result);
				return result;
			}
			if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
				debug("i2c: receive mrdr: timeout\n");
				return -1;
			}
			val = readl(&regs->mrdr);
		} while (val & LPI2C_MRDR_RXEMPTY_MASK);
		*rxbuf++ = LPI2C_MRDR_DATA(val);
	}

	return result;
}

static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
{
	lpi2c_status_t result;
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 val;

	result = imx_lpci2c_check_busy_bus(regs);
	if (result) {
		debug("i2c: start check busy bus: 0x%x\n", result);

		/* Try to init the lpi2c then check the bus busy again */
		bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
		result = imx_lpci2c_check_busy_bus(regs);
		if (result) {
			printf("i2c: Error check busy bus: 0x%x\n", result);
			return result;
		}
	}
	/* clear all status flags */
	writel(0x7f00, &regs->msr);
	/* turn off auto-stop condition */
	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
	writel(val, &regs->mcfgr1);
	/* wait tx fifo ready */
	result = bus_i2c_wait_for_tx_ready(regs);
	if (result) {
		debug("i2c: start wait for tx ready: 0x%x\n", result);
		return result;
	}
	/* issue start command */
	val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
	writel(val, &regs->mtdr);

	return result;
}

static int bus_i2c_stop(struct udevice *bus)
{
	lpi2c_status_t result;
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 status;
	ulong start_time;

	result = bus_i2c_wait_for_tx_ready(regs);
	if (result) {
		debug("i2c: stop wait for tx ready: 0x%x\n", result);
		return result;
	}

	/* send stop command */
	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);

	start_time = get_timer(0);
	while (1) {
		status = readl(&regs->msr);
		result = imx_lpci2c_check_clear_error(regs);
		/* stop detect flag */
		if (status & LPI2C_MSR_SDF_MASK) {
			/* clear stop flag */
			status &= LPI2C_MSR_SDF_MASK;
			writel(status, &regs->msr);
			break;
		}

		if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
			debug("stop timeout\n");
			return -ETIMEDOUT;
		}
	}

	return result;
}

static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 1);
	if (result)
		return result;
	result = bus_i2c_receive(bus, buf, len);
	if (result)
		return result;

	return result;
}

static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 0);
	if (result)
		return result;
	result = bus_i2c_send(bus, buf, len);
	if (result)
		return result;

	return result;
}

u32 __weak imx_get_i2cclk(u32 i2c_num)
{
	return 0;
}

static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 val;
	u32 preescale = 0, best_pre = 0, clkhi = 0;
	u32 best_clkhi = 0, abs_error = 0, rate;
	u32 error = 0xffffffff;
	u32 clock_rate;
	bool mode;
	int i;

	if (CONFIG_IS_ENABLED(CLK)) {
		clock_rate = clk_get_rate(&i2c_bus->per_clk);
		if (clock_rate <= 0) {
			dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
			return clock_rate;
		}
	} else {
		clock_rate = imx_get_i2cclk(dev_seq(bus));
		if (!clock_rate)
			return -EPERM;
	}

	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
	/* disable master mode */
	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	writel(val | LPI2C_MCR_MEN(0), &regs->mcr);

	for (preescale = 1; (preescale <= 128) &&
		(error != 0); preescale = 2 * preescale) {
		for (clkhi = 1; clkhi < 32; clkhi++) {
			if (clkhi == 1)
				rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
			else
				rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));

			abs_error = speed > rate ? speed - rate : rate - speed;

			if (abs_error < error) {
				best_pre = preescale;
				best_clkhi = clkhi;
				error = abs_error;
				if (abs_error == 0)
					break;
			}
		}
	}

	/* Standard, fast, fast mode plus and ultra-fast transfers. */
	val = LPI2C_MCCR0_CLKHI(best_clkhi);
	if (best_clkhi < 2)
		val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
	else
		val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
			LPI2C_MCCR0_DATAVD(best_clkhi / 2);
	writel(val, &regs->mccr0);

	for (i = 0; i < 8; i++) {
		if (best_pre == (1 << i)) {
			best_pre = i;
			break;
		}
	}

	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
	writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);

	if (mode) {
		val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
		writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
	}

	return 0;
}

static int bus_i2c_init(struct udevice *bus, int speed)
{
	u32 val;
	int ret;

	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	/* reset peripheral */
	writel(LPI2C_MCR_RST_MASK, &regs->mcr);
	writel(0x0, &regs->mcr);
	/* Disable Dozen mode */
	writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
	/* host request disable, active high, external pin */
	val = readl(&regs->mcfgr0);
	val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
				LPI2C_MCFGR0_HRSEL_MASK));
	val |= LPI2C_MCFGR0_HRPOL(0x1);
	writel(val, &regs->mcfgr0);
	/* pincfg and ignore ack */
	val = readl(&regs->mcfgr1);
	val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
	val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
	val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
	writel(val, &regs->mcfgr1);

	ret = bus_i2c_set_bus_speed(bus, speed);

	/* enable lpi2c in master mode */
	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	writel(val | LPI2C_MCR_MEN(1), &regs->mcr);

	debug("i2c : controller bus %d, speed %d:\n", dev_seq(bus), speed);

	return ret;
}

static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
				u32 chip_flags)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 0);
	if (result) {
		bus_i2c_stop(bus);
		bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
		return result;
	}

	result = bus_i2c_stop(bus);
	if (result)
		bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);

	return result;
}

static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
	int ret = 0, ret_stop;

	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD)
			ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
		else {
			ret = bus_i2c_write(bus, msg->addr, msg->buf,
					    msg->len);
			if (ret)
				break;
		}
	}

	if (ret)
		debug("i2c_write: error sending\n");

	ret_stop = bus_i2c_stop(bus);
	if (ret_stop)
		debug("i2c_xfer: stop bus error\n");

	ret |= ret_stop;

	return ret;
}

static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	return bus_i2c_set_bus_speed(bus, speed);
}

__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
{
	return 0;
}

static int imx_lpi2c_probe(struct udevice *bus)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	fdt_addr_t addr;
	int ret;

	i2c_bus->driver_data = dev_get_driver_data(bus);

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	i2c_bus->base = addr;
	i2c_bus->index = dev_seq(bus);
	i2c_bus->bus = bus;

	/* power up i2c resource */
	ret = init_i2c_power(dev_seq(bus));
	if (ret) {
		debug("init_i2c_power err = %d\n", ret);
		return ret;
	}

	if (CONFIG_IS_ENABLED(CLK)) {
		ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
		if (ret) {
			dev_err(bus, "Failed to get per clk\n");
			return ret;
		}
		ret = clk_enable(&i2c_bus->per_clk);
		if (ret) {
			dev_err(bus, "Failed to enable per clk\n");
			return ret;
		}

		ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
		if (ret) {
			dev_err(bus, "Failed to get ipg clk\n");
			return ret;
		}
		ret = clk_enable(&i2c_bus->ipg_clk);
		if (ret) {
			dev_err(bus, "Failed to enable ipg clk\n");
			return ret;
		}
	} else {
		/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
		ret = enable_i2c_clk(1, dev_seq(bus));
		if (ret < 0)
			return ret;
	}

	ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
	if (ret < 0)
		return ret;

	debug("i2c : controller bus %d at 0x%lx , speed %d: ",
	      dev_seq(bus), i2c_bus->base,
	      i2c_bus->speed);

	return 0;
}

static const struct dm_i2c_ops imx_lpi2c_ops = {
	.xfer		= imx_lpi2c_xfer,
	.probe_chip	= imx_lpi2c_probe_chip,
	.set_bus_speed	= imx_lpi2c_set_bus_speed,
};

static const struct udevice_id imx_lpi2c_ids[] = {
	{ .compatible = "fsl,imx7ulp-lpi2c", },
	{ .compatible = "fsl,imx8qm-lpi2c", },
	{}
};

U_BOOT_DRIVER(imx_lpi2c) = {
	.name = "imx_lpi2c",
	.id = UCLASS_I2C,
	.of_match = imx_lpi2c_ids,
	.probe = imx_lpi2c_probe,
	.priv_auto	= sizeof(struct imx_lpi2c_bus),
	.ops = &imx_lpi2c_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7ee3f149 PF	2	/*
7ee3f149 PF	3	* Copyright 2016 Freescale Semiconductors, Inc.
7ee3f149 PF	4	*/
7ee3f149 PF	5
7ee3f149	6	#include <errno.h>
f7ae49fc	7	#include <log.h>
7ee3f149 PF	8	#include <asm/io.h>
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/imx-regs.h>
9b2ebcc0	11	#include <imx_lpi2c.h>
7ee3f149 PF	12	#include <asm/arch/sys_proto.h>
	13	#include <dm.h>
	14	#include <fdtdec.h>
	15	#include <i2c.h>
336d4615	16	#include <dm/device_compat.h>
7ee3f149	17
7ee3f149	18	#define LPI2C_FIFO_SIZE 4
a32effd2	19	#define LPI2C_NACK_TOUT_MS 1
7ee3f149 PF	20	#define LPI2C_TIMEOUT_MS 100
7ee3f149 PF	21
971490c8 YL	22	static int bus_i2c_init(struct udevice *bus, int speed);
971490c8 YL	23
7ee3f149 PF	24	/* Weak linked function for overridden by some SoC power function */
	25	int __weak init_i2c_power(unsigned i2c_num)
	26	{
	27	return 0;
	28	}
	29
a821c4af	30	static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
7ee3f149	31	{
7ee3f149 PF	32	lpi2c_status_t result = LPI2C_SUCESS;
	33	u32 status;
	34
	35	status = readl(&regs->msr);
	36
	37	if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
	38	result = LPI2C_BUSY;
	39
	40	return result;
	41	}
	42
a821c4af	43	static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
7ee3f149	44	{
7ee3f149 PF	45	lpi2c_status_t result = LPI2C_SUCESS;
	46	u32 val, status;
	47
	48	status = readl(&regs->msr);
	49	/* errors to check for */
	50	status &= LPI2C_MSR_NDF_MASK \| LPI2C_MSR_ALF_MASK \|
	51	LPI2C_MSR_FEF_MASK \| LPI2C_MSR_PLTF_MASK;
	52
	53	if (status) {
	54	if (status & LPI2C_MSR_PLTF_MASK)
	55	result = LPI2C_PIN_LOW_TIMEOUT_ERR;
	56	else if (status & LPI2C_MSR_ALF_MASK)
	57	result = LPI2C_ARB_LOST_ERR;
	58	else if (status & LPI2C_MSR_NDF_MASK)
	59	result = LPI2C_NAK_ERR;
	60	else if (status & LPI2C_MSR_FEF_MASK)
	61	result = LPI2C_FIFO_ERR;
	62
	63	/* clear status flags */
	64	writel(0x7f00, &regs->msr);
	65	/* reset fifos */
	66	val = readl(&regs->mcr);
	67	val \|= LPI2C_MCR_RRF_MASK \| LPI2C_MCR_RTF_MASK;
	68	writel(val, &regs->mcr);
	69	}
	70
	71	return result;
	72	}
	73
a821c4af	74	static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
7ee3f149	75	{
7ee3f149 PF	76	lpi2c_status_t result = LPI2C_SUCESS;
	77	u32 txcount = 0;
	78	ulong start_time = get_timer(0);
	79
	80	do {
	81	txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
	82	txcount = LPI2C_FIFO_SIZE - txcount;
a821c4af	83	result = imx_lpci2c_check_clear_error(regs);
7ee3f149 PF	84	if (result) {
	85	debug("i2c: wait for tx ready: result 0x%x\n", result);
	86	return result;
	87	}
	88	if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
	89	debug("i2c: wait for tx ready: timeout\n");
	90	return -1;
	91	}
	92	} while (!txcount);
	93
	94	return result;
	95	}
	96
971490c8	97	static int bus_i2c_send(struct udevice bus, u8 txbuf, int len)
7ee3f149	98	{
35d3982e YL	99	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	100	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	101	lpi2c_status_t result = LPI2C_SUCESS;
	102
	103	/* empty tx */
	104	if (!len)
	105	return result;
	106
	107	while (len--) {
a821c4af	108	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149	109	if (result) {
7677c0de	110	debug("i2c: send wait for tx ready: %d\n", result);
7ee3f149 PF	111	return result;
	112	}
	113	writel(*txbuf++, &regs->mtdr);
	114	}
	115
	116	return result;
	117	}
	118
971490c8	119	static int bus_i2c_receive(struct udevice bus, u8 rxbuf, int len)
7ee3f149	120	{
35d3982e YL	121	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	122	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	123	lpi2c_status_t result = LPI2C_SUCESS;
	124	u32 val;
	125	ulong start_time = get_timer(0);
	126
	127	/* empty read */
	128	if (!len)
	129	return result;
	130
a821c4af	131	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149 PF	132	if (result) {
	133	debug("i2c: receive wait fot tx ready: %d\n", result);
	134	return result;
	135	}
	136
	137	/* clear all status flags */
	138	writel(0x7f00, &regs->msr);
	139	/* send receive command */
	140	val = LPI2C_MTDR_CMD(0x1) \| LPI2C_MTDR_DATA(len - 1);
	141	writel(val, &regs->mtdr);
	142
	143	while (len--) {
	144	do {
a821c4af	145	result = imx_lpci2c_check_clear_error(regs);
7ee3f149	146	if (result) {
a821c4af SG	147	debug("i2c: receive check clear error: %d\n",
a821c4af SG	148	result);
7ee3f149 PF	149	return result;
	150	}
	151	if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
	152	debug("i2c: receive mrdr: timeout\n");
	153	return -1;
	154	}
	155	val = readl(&regs->mrdr);
	156	} while (val & LPI2C_MRDR_RXEMPTY_MASK);
	157	*rxbuf++ = LPI2C_MRDR_DATA(val);
	158	}
	159
	160	return result;
	161	}
	162
971490c8	163	static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
7ee3f149	164	{
d45c2f39	165	lpi2c_status_t result;
35d3982e YL	166	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	167	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	168	u32 val;
7ee3f149 PF	169
a821c4af	170	result = imx_lpci2c_check_busy_bus(regs);
7ee3f149 PF	171	if (result) {
7ee3f149 PF	172	debug("i2c: start check busy bus: 0x%x\n", result);
971490c8 YL	173
971490c8 YL	174	/* Try to init the lpi2c then check the bus busy again */
f3d46152	175	bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
971490c8 YL	176	result = imx_lpci2c_check_busy_bus(regs);
	177	if (result) {
	178	printf("i2c: Error check busy bus: 0x%x\n", result);
	179	return result;
	180	}
7ee3f149 PF	181	}
	182	/* clear all status flags */
	183	writel(0x7f00, &regs->msr);
	184	/* turn off auto-stop condition */
	185	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
	186	writel(val, &regs->mcfgr1);
	187	/* wait tx fifo ready */
a821c4af	188	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149 PF	189	if (result) {
	190	debug("i2c: start wait for tx ready: 0x%x\n", result);
	191	return result;
	192	}
	193	/* issue start command */
	194	val = LPI2C_MTDR_CMD(0x4) \| (addr << 0x1) \| dir;
	195	writel(val, &regs->mtdr);
	196
	197	return result;
	198	}
a821c4af	199
971490c8	200	static int bus_i2c_stop(struct udevice *bus)
7ee3f149	201	{
d45c2f39	202	lpi2c_status_t result;
35d3982e YL	203	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	204	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149	205	u32 status;
a32effd2	206	ulong start_time;
7ee3f149	207
a821c4af	208	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149 PF	209	if (result) {
	210	debug("i2c: stop wait for tx ready: 0x%x\n", result);
	211	return result;
	212	}
	213
	214	/* send stop command */
	215	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
	216
a32effd2 GP	217	start_time = get_timer(0);
a32effd2 GP	218	while (1) {
7ee3f149	219	status = readl(&regs->msr);
a821c4af	220	result = imx_lpci2c_check_clear_error(regs);
7ee3f149 PF	221	/* stop detect flag */
	222	if (status & LPI2C_MSR_SDF_MASK) {
	223	/* clear stop flag */
	224	status &= LPI2C_MSR_SDF_MASK;
	225	writel(status, &regs->msr);
	226	break;
	227	}
a32effd2 GP	228
	229	if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
	230	debug("stop timeout\n");
	231	return -ETIMEDOUT;
	232	}
7ee3f149 PF	233	}
	234
	235	return result;
	236	}
	237
971490c8	238	static int bus_i2c_read(struct udevice bus, u32 chip, u8 buf, int len)
7ee3f149	239	{
d45c2f39	240	lpi2c_status_t result;
7ee3f149	241
971490c8	242	result = bus_i2c_start(bus, chip, 1);
7ee3f149 PF	243	if (result)
7ee3f149 PF	244	return result;
971490c8	245	result = bus_i2c_receive(bus, buf, len);
7ee3f149 PF	246	if (result)
	247	return result;
	248
	249	return result;
	250	}
	251
971490c8	252	static int bus_i2c_write(struct udevice bus, u32 chip, u8 buf, int len)
7ee3f149	253	{
d45c2f39	254	lpi2c_status_t result;
7ee3f149	255
971490c8	256	result = bus_i2c_start(bus, chip, 0);
7ee3f149 PF	257	if (result)
7ee3f149 PF	258	return result;
971490c8	259	result = bus_i2c_send(bus, buf, len);
7ee3f149 PF	260	if (result)
	261	return result;
	262
	263	return result;
	264	}
	265
3d7690ae PF	266	u32 __weak imx_get_i2cclk(u32 i2c_num)
	267	{
	268	return 0;
	269	}
	270
7ee3f149 PF	271	static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
7ee3f149 PF	272	{
3d7690ae	273	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e	274	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	275	u32 val;
	276	u32 preescale = 0, best_pre = 0, clkhi = 0;
	277	u32 best_clkhi = 0, abs_error = 0, rate;
	278	u32 error = 0xffffffff;
	279	u32 clock_rate;
	280	bool mode;
	281	int i;
	282
b4004c29	283	if (CONFIG_IS_ENABLED(CLK)) {
3d7690ae PF	284	clock_rate = clk_get_rate(&i2c_bus->per_clk);
	285	if (clock_rate <= 0) {
	286	dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
	287	return clock_rate;
	288	}
	289	} else {
8b85dfc6	290	clock_rate = imx_get_i2cclk(dev_seq(bus));
3d7690ae PF	291	if (!clock_rate)
	292	return -EPERM;
	293	}
7ee3f149 PF	294
	295	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
	296	/* disable master mode */
	297	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	298	writel(val \| LPI2C_MCR_MEN(0), &regs->mcr);
	299
	300	for (preescale = 1; (preescale <= 128) &&
	301	(error != 0); preescale = 2 * preescale) {
	302	for (clkhi = 1; clkhi < 32; clkhi++) {
	303	if (clkhi == 1)
	304	rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
	305	else
	306	rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
	307
	308	abs_error = speed > rate ? speed - rate : rate - speed;
	309
	310	if (abs_error < error) {
	311	best_pre = preescale;
	312	best_clkhi = clkhi;
	313	error = abs_error;
	314	if (abs_error == 0)
	315	break;
	316	}
	317	}
	318	}
	319
	320	/* Standard, fast, fast mode plus and ultra-fast transfers. */
	321	val = LPI2C_MCCR0_CLKHI(best_clkhi);
	322	if (best_clkhi < 2)
	323	val \|= LPI2C_MCCR0_CLKLO(3) \| LPI2C_MCCR0_SETHOLD(2) \| LPI2C_MCCR0_DATAVD(1);
	324	else
	325	val \|= LPI2C_MCCR0_CLKLO(2 * best_clkhi) \| LPI2C_MCCR0_SETHOLD(best_clkhi) \|
	326	LPI2C_MCCR0_DATAVD(best_clkhi / 2);
	327	writel(val, &regs->mccr0);
	328
	329	for (i = 0; i < 8; i++) {
	330	if (best_pre == (1 << i)) {
	331	best_pre = i;
	332	break;
	333	}
	334	}
	335
	336	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
	337	writel(val \| LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
	338
	339	if (mode) {
	340	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	341	writel(val \| LPI2C_MCR_MEN(1), &regs->mcr);
	342	}
	343
	344	return 0;
	345	}
	346
	347	static int bus_i2c_init(struct udevice *bus, int speed)
	348	{
7ee3f149 PF	349	u32 val;
	350	int ret;
	351
35d3982e YL	352	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	353	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	354	/* reset peripheral */
	355	writel(LPI2C_MCR_RST_MASK, &regs->mcr);
	356	writel(0x0, &regs->mcr);
	357	/* Disable Dozen mode */
	358	writel(LPI2C_MCR_DBGEN(0) \| LPI2C_MCR_DOZEN(1), &regs->mcr);
	359	/* host request disable, active high, external pin */
	360	val = readl(&regs->mcfgr0);
	361	val &= (~(LPI2C_MCFGR0_HREN_MASK \| LPI2C_MCFGR0_HRPOL_MASK \|
	362	LPI2C_MCFGR0_HRSEL_MASK));
	363	val \|= LPI2C_MCFGR0_HRPOL(0x1);
	364	writel(val, &regs->mcfgr0);
	365	/* pincfg and ignore ack */
	366	val = readl(&regs->mcfgr1);
	367	val &= ~(LPI2C_MCFGR1_PINCFG_MASK \| LPI2C_MCFGR1_IGNACK_MASK);
	368	val \|= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
	369	val \|= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
	370	writel(val, &regs->mcfgr1);
	371
	372	ret = bus_i2c_set_bus_speed(bus, speed);
	373
	374	/* enable lpi2c in master mode */
	375	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	376	writel(val \| LPI2C_MCR_MEN(1), &regs->mcr);
	377
8b85dfc6	378	debug("i2c : controller bus %d, speed %d:\n", dev_seq(bus), speed);
7ee3f149 PF	379
	380	return ret;
	381	}
	382
	383	static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
	384	u32 chip_flags)
	385	{
d45c2f39	386	lpi2c_status_t result;
7ee3f149	387
971490c8	388	result = bus_i2c_start(bus, chip, 0);
7ee3f149	389	if (result) {
971490c8	390	bus_i2c_stop(bus);
f3d46152	391	bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
7ee3f149 PF	392	return result;
	393	}
	394
971490c8	395	result = bus_i2c_stop(bus);
a32effd2	396	if (result)
f3d46152	397	bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
7ee3f149 PF	398
	399	return result;
	400	}
	401
	402	static int imx_lpi2c_xfer(struct udevice bus, struct i2c_msg msg, int nmsgs)
	403	{
d144f61a	404	int ret = 0, ret_stop;
7ee3f149 PF	405
	406	for (; nmsgs > 0; nmsgs--, msg++) {
	407	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	408	if (msg->flags & I2C_M_RD)
971490c8	409	ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
7ee3f149	410	else {
971490c8	411	ret = bus_i2c_write(bus, msg->addr, msg->buf,
7ee3f149 PF	412	msg->len);
	413	if (ret)
	414	break;
	415	}
	416	}
	417
	418	if (ret)
	419	debug("i2c_write: error sending\n");
	420
971490c8	421	ret_stop = bus_i2c_stop(bus);
d144f61a YL	422	if (ret_stop)
	423	debug("i2c_xfer: stop bus error\n");
	424
	425	ret \|= ret_stop;
	426
7ee3f149 PF	427	return ret;
	428	}
	429
	430	static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	431	{
	432	return bus_i2c_set_bus_speed(bus, speed);
	433	}
	434
3d7690ae PF	435	__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
	436	{
	437	return 0;
	438	}
	439
7ee3f149 PF	440	static int imx_lpi2c_probe(struct udevice *bus)
	441	{
	442	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	443	fdt_addr_t addr;
	444	int ret;
	445
	446	i2c_bus->driver_data = dev_get_driver_data(bus);
	447
2548493a	448	addr = dev_read_addr(bus);
7ee3f149	449	if (addr == FDT_ADDR_T_NONE)
7c84319a	450	return -EINVAL;
7ee3f149 PF	451
7ee3f149 PF	452	i2c_bus->base = addr;
8b85dfc6	453	i2c_bus->index = dev_seq(bus);
7ee3f149 PF	454	i2c_bus->bus = bus;
	455
	456	/* power up i2c resource */
8b85dfc6	457	ret = init_i2c_power(dev_seq(bus));
7ee3f149 PF	458	if (ret) {
	459	debug("init_i2c_power err = %d\n", ret);
	460	return ret;
	461	}
	462
b4004c29	463	if (CONFIG_IS_ENABLED(CLK)) {
3d7690ae PF	464	ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
	465	if (ret) {
	466	dev_err(bus, "Failed to get per clk\n");
	467	return ret;
	468	}
	469	ret = clk_enable(&i2c_bus->per_clk);
	470	if (ret) {
	471	dev_err(bus, "Failed to enable per clk\n");
	472	return ret;
	473	}
d02be21d PF	474
	475	ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
	476	if (ret) {
	477	dev_err(bus, "Failed to get ipg clk\n");
	478	return ret;
	479	}
	480	ret = clk_enable(&i2c_bus->ipg_clk);
	481	if (ret) {
	482	dev_err(bus, "Failed to enable ipg clk\n");
	483	return ret;
	484	}
3d7690ae PF	485	} else {
3d7690ae PF	486	/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
8b85dfc6	487	ret = enable_i2c_clk(1, dev_seq(bus));
3d7690ae PF	488	if (ret < 0)
	489	return ret;
	490	}
7ee3f149	491
f3d46152	492	ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
7ee3f149 PF	493	if (ret < 0)
	494	return ret;
	495
7677c0de	496	debug("i2c : controller bus %d at 0x%lx , speed %d: ",
8b85dfc6	497	dev_seq(bus), i2c_bus->base,
7ee3f149 PF	498	i2c_bus->speed);
	499
	500	return 0;
	501	}
	502
	503	static const struct dm_i2c_ops imx_lpi2c_ops = {
	504	.xfer = imx_lpi2c_xfer,
	505	.probe_chip = imx_lpi2c_probe_chip,
	506	.set_bus_speed = imx_lpi2c_set_bus_speed,
	507	};
	508
	509	static const struct udevice_id imx_lpi2c_ids[] = {
	510	{ .compatible = "fsl,imx7ulp-lpi2c", },
9b2ebcc0	511	{ .compatible = "fsl,imx8qm-lpi2c", },
7ee3f149 PF	512	{}
	513	};
	514
	515	U_BOOT_DRIVER(imx_lpi2c) = {
	516	.name = "imx_lpi2c",
	517	.id = UCLASS_I2C,
	518	.of_match = imx_lpi2c_ids,
	519	.probe = imx_lpi2c_probe,
41575d8e	520	.priv_auto = sizeof(struct imx_lpi2c_bus),
7ee3f149 PF	521	.ops = &imx_lpi2c_ops,
7ee3f149 PF	522	};