[J-u-boot.git] / include / configs / M5208EVBE.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF5208EVBe.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

#ifndef _M5208EVBE_H
#define _M5208EVBE_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CFG_SYS_UART_PORT		(0)

/* I2C */

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		"M5208EVBe"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CFG_SYS_CLK		166666666	/* CPU Core Clock */
#define CFG_SYS_PLL_ODR	0x36
#define CFG_SYS_PLL_FDR	0x7D

#define CFG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CFG_SYS_INIT_RAM_ADDR	0x80000000
#define CFG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL	0x221

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CFG_SYS_SDRAM_BASE		0x40000000
#define CFG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1		0x43711630
#define CFG_SYS_SDRAM_CFG2		0x56670000
#define CFG_SYS_SDRAM_CTRL		0xE1002000
#define CFG_SYS_SDRAM_EMOD		0x80010000
#define CFG_SYS_SDRAM_MODE		0x00CD0000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))

/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#endif

#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE

/*
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*);

/* Cache Configuration */

#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
					 CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
					 CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/* Chipselect bank definitions */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CFG_SYS_CS0_BASE		0
#define CFG_SYS_CS0_MASK		0x007F0001
#define CFG_SYS_CS0_CTRL		0x00001FA0

#endif				/* _M5208EVBE_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
bf9a5215 TL	2	/*
	3	* Configuation settings for the Freescale MCF5208EVBe.
	4	*
	5	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	6	* TsiChung Liew ([email protected])
bf9a5215 TL	7	*/
	8
	9	#ifndef _M5208EVBE_H
	10	#define _M5208EVBE_H
	11
	12	/*
	13	* High Level Configuration Options
	14	* (easy to change)
	15	*/
65cc0e2a	16	#define CFG_SYS_UART_PORT (0)
bf9a5215	17
bf9a5215	18	/* I2C */
bf9a5215	19
bf9a5215	20	#ifdef CONFIG_MCFFEC
bf9a5215 TL	21	# define CONFIG_IPADDR 192.162.1.2
	22	# define CONFIG_NETMASK 255.255.255.0
	23	# define CONFIG_SERVERIP 192.162.1.1
	24	# define CONFIG_GATEWAYIP 192.162.1.1
bf9a5215 TL	25	#endif /* CONFIG_MCFFEC */
bf9a5215 TL	26
5bc0543d	27	#define CONFIG_HOSTNAME "M5208EVBe"
bf9a5215 TL	28	#define CONFIG_EXTRA_ENV_SETTINGS \
	29	"netdev=eth0\0" \
	30	"loadaddr=40010000\0" \
	31	"u-boot=u-boot.bin\0" \
	32	"load=tftp ${loadaddr) ${u-boot}\0" \
	33	"upd=run load; run prog\0" \
	34	"prog=prot off 0 3ffff;" \
	35	"era 0 3ffff;" \
	36	"cp.b ${loadaddr} 0 ${filesize};" \
	37	"save\0" \
	38	""
	39
	40	#define CONFIG_PRAM 512 /* 512 KB */
bf9a5215	41
65cc0e2a TR	42	#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
	43	#define CFG_SYS_PLL_ODR 0x36
	44	#define CFG_SYS_PLL_FDR 0x7D
bf9a5215	45
65cc0e2a	46	#define CFG_SYS_MBAR 0xFC000000
bf9a5215 TL	47
	48	/*
	49	* Low Level Configuration Settings
	50	* (address mappings, register initial values, etc.)
	51	* You should know what you are doing if you make changes here.
	52	*/
	53	/* Definitions for initial stack pointer and data area (in DPRAM) */
65cc0e2a TR	54	#define CFG_SYS_INIT_RAM_ADDR 0x80000000
	55	#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
	56	#define CFG_SYS_INIT_RAM_CTRL 0x221
bf9a5215 TL	57
	58	/*
	59	* Start addresses for the final memory configuration
	60	* (Set up by the startup code)
aa6e94de	61	* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
bf9a5215	62	*/
aa6e94de TR	63	#define CFG_SYS_SDRAM_BASE 0x40000000
	64	#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
	65	#define CFG_SYS_SDRAM_CFG1 0x43711630
	66	#define CFG_SYS_SDRAM_CFG2 0x56670000
	67	#define CFG_SYS_SDRAM_CTRL 0xE1002000
	68	#define CFG_SYS_SDRAM_EMOD 0x80010000
	69	#define CFG_SYS_SDRAM_MODE 0x00CD0000
bf9a5215	70
bf9a5215 TL	71	/*
	72	* For booting Linux, the board info and command line data
	73	* have to be in the first 8 MB of memory, since this is
	74	* the maximum mapped by the Linux kernel during initialization ??
	75	*/
65cc0e2a	76	#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
bf9a5215 TL	77
bf9a5215 TL	78	/* FLASH organization */
bf9a5215	79	#ifdef CONFIG_SYS_FLASH_CFI
65cc0e2a	80	# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
bf9a5215 TL	81	#endif
bf9a5215 TL	82
65cc0e2a	83	#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
bf9a5215 TL	84
	85	/*
	86	* Configuration for environment
	87	* Environment is embedded in u-boot in the second sector of the flash
	88	*/
bf9a5215	89
5296cb1d	90	#define LDS_BOARD_TEXT \
0649cd0d SG	91	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	92	env/embedded.o(.text*);
5296cb1d	93
bf9a5215	94	/* Cache Configuration */
bf9a5215	95
65cc0e2a TR	96	#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
	97	CFG_SYS_INIT_RAM_SIZE - 8)
	98	#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
	99	CFG_SYS_INIT_RAM_SIZE - 4)
	100	#define CFG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	101	#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE \| \
aa6e94de	102	CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) \| \
dd9f054e	103	CF_ACR_EN \| CF_ACR_SM_ALL)
65cc0e2a	104	#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
dd9f054e TL	105	CF_CACR_DISD \| CF_CACR_INVI \| \
	106	CF_CACR_CEIB \| CF_CACR_DCM \| \
	107	CF_CACR_EUSP)
	108
bf9a5215 TL	109	/* Chipselect bank definitions */
	110	/*
	111	* CS0 - NOR Flash
	112	* CS1 - Available
	113	* CS2 - Available
	114	* CS3 - Available
	115	* CS4 - Available
	116	* CS5 - Available
	117	*/
65cc0e2a TR	118	#define CFG_SYS_CS0_BASE 0
	119	#define CFG_SYS_CS0_MASK 0x007F0001
	120	#define CFG_SYS_CS0_CTRL 0x00001FA0
bf9a5215 TL	121
bf9a5215 TL	122	#endif /* _M5208EVBE_H */