[J-u-boot.git] / drivers / usb / host / ehci-omap.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Derived from Beagle Board code by
 *	Sunil Kumar <[email protected]>
 *	Shashi Ranjan <[email protected]>
 *
 */

#include <common.h>
#include <log.h>
#include <usb.h>
#include <linux/delay.h>
#include <usb/ulpi.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <power/regulator.h>

#include "ehci.h"

static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;

static int omap_uhh_reset(void)
{
	int timeout = 0;
	u32 rev;

	rev = readl(&uhh->rev);

	/* Soft RESET */
	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);

	switch (rev) {
	case OMAP_USBHS_REV1:
		/* Wait for soft RESET to complete */
		while (!(readl(&uhh->syss) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		/* Set No-Idle, No-Standby */
		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;

	default:	/* Rev. 2 onwards */

		udelay(2); /* Need to wait before accessing SYSCONFIG back */

		/* Wait for soft RESET to complete */
		while ((readl(&uhh->sysc) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;
	}

	return 0;
}

static int omap_ehci_tll_reset(void)
{
	unsigned long init = get_timer(0);

	/* perform TLL soft reset, and wait until reset is complete */
	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);

	/* Wait for TLL reset to complete */
	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
		if (get_timer(init) > CONFIG_SYS_HZ) {
			debug("OMAP EHCI error: timeout resetting TLL\n");
			return -EL3RST;
	}

	return 0;
}

static void omap_usbhs_hsic_init(int port)
{
	unsigned int reg;

	/* Enable channels now */
	reg = readl(&usbtll->channel_conf + port);

	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
		| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
		| OMAP_TLL_CHANNEL_CONF_DRVVBUS
		| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
		| OMAP_TLL_CHANNEL_CONF_CHANEN));

	writel(reg, &usbtll->channel_conf + port);
}

#ifdef CONFIG_USB_ULPI
static void omap_ehci_soft_phy_reset(int port)
{
	struct ulpi_viewport ulpi_vp;

	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	ulpi_vp.port_num = port;

	ulpi_reset(&ulpi_vp);
}
#else
static void omap_ehci_soft_phy_reset(int port)
{
	return;
}
#endif

struct ehci_omap_priv_data {
	struct ehci_ctrl ctrl;
	struct omap_ehci *ehci;
#ifdef CONFIG_DM_REGULATOR
	struct udevice *vbus_supply;
#endif
	enum usb_init_type init_type;
	int portnr;
	struct phy phy[OMAP_HS_USB_PORTS];
	int nports;
};

/*
 * Initialize the OMAP EHCI controller and PHY.
 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
 * See there for additional Copyrights.
 */
static int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
			      struct udevice *dev)
{
	int ret;
	unsigned int i, reg = 0, rev = 0;

	debug("Initializing OMAP EHCI\n");

	ret = board_usb_init(index, USB_INIT_HOST);
	if (ret < 0)
		return ret;

	/* Hold the PHY in RESET for enough time till DIR is high */
	/* Refer: ISSUE1 */
	udelay(10);

	ret = omap_uhh_reset();
	if (ret < 0)
		return ret;

	ret = omap_ehci_tll_reset();
	if (ret)
		return ret;

	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
		OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
		OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);

	/* Put UHH in NoIdle/NoStandby mode */
	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);

	/* setup ULPI bypass and burst configurations */
	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
		(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));

	rev = readl(&uhh->rev);
	if (rev == OMAP_USBHS_REV1) {
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	} else if (rev == OMAP_USBHS_REV2) {

		clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
					OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

	} else if (rev == OMAP_USBHS_REV2_1) {

		clrsetbits_le32(&reg,
				(OMAP_P1_MODE_CLEAR |
				 OMAP_P2_MODE_CLEAR |
				 OMAP_P3_MODE_CLEAR),
				OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
			setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	}

	debug("OMAP UHH_REVISION 0x%x\n", rev);
	writel(reg, &uhh->hostconfig);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
			omap_usbhs_hsic_init(i);

	/*
	 * Refer ISSUE1:
	 * Hold the PHY in RESET for enough time till
	 * PHY is settled and ready
	 */
	udelay(10);

	/*
	 * An undocumented "feature" in the OMAP3 EHCI controller,
	 * causes suspended ports to be taken out of suspend when
	 * the USBCMD.Run/Stop bit is cleared (for example when
	 * we do ehci_bus_suspend).
	 * This breaks suspend-resume if the root-hub is allowed
	 * to suspend. Writing 1 to this undocumented register bit
	 * disables this feature and restores normal behavior.
	 */
	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
			omap_ehci_soft_phy_reset(i);

	debug("OMAP EHCI init done\n");
	return 0;
}

static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};

static void omap_usbhs_set_mode(u8 index, const char *mode)
{
	if (!strcmp(mode, "ehci-phy"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
	else if (!strcmp(mode, "ehci-tll"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
	else if (!strcmp(mode, "ehci-hsic"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
}

static int omap_usbhs_probe(struct udevice *dev)
{
	u8 i;
	const char *mode;
	char prop[11];

	/* Go through each port portX-mode to determing phy mode */
	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
		snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
		mode = dev_read_string(dev, prop);

		/* If the portX-mode exists, set the mode */
		if (mode)
			omap_usbhs_set_mode(i, mode);
	}

	return 0;
}

static const struct udevice_id omap_usbhs_dt_ids[] = {
	{ .compatible = "ti,usbhs-host" },
	{ }
};

U_BOOT_DRIVER(usb_omaphs_host) = {
	.name	= "usbhs-host",
	.id	= UCLASS_SIMPLE_BUS,
	.of_match = omap_usbhs_dt_ids,
	.probe	= omap_usbhs_probe,
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};

static int ehci_usb_of_to_plat(struct udevice *dev)
{
	struct usb_plat *plat = dev_get_plat(dev);

	plat->init_type = USB_INIT_HOST;

	return 0;
}

/*
 * This driver references phys based on the USB port.  If
 * the port is unused, the corresponding phy is listed as NULL
 * which generic_phy_init_bulk treats as an error, so we need
 * a custom one that tolerates empty phys
 */
static int omap_ehci_phy_get(struct udevice *dev)
{
	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
	int i, ret;

	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
		ret = generic_phy_get_by_index(dev, i, &priv->phy[i]);
		if (ret && ret != -ENOENT)
			return ret;
	};

	return 0;
};

static int omap_ehci_probe(struct udevice *dev)
{
	struct usb_plat *plat = dev_get_plat(dev);
	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	int ret;

	priv->ehci = dev_read_addr_ptr(dev);
	priv->portnr = dev_seq(dev);
	priv->init_type = plat->init_type;

	hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
	hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;

	/* Identify Phys */
	ret = omap_ehci_phy_get(dev);
	if (ret) {
		printf("Failed to get phys\n");
		return ret;
	}

	/* Register the EHCI */
	ret = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
	if (ret) {
		printf("Failed to register EHCI\n");
		return ret;
	}

	ret = omap_ehci_hcd_init(0, &usbhs_bdata, dev);
	if (ret)
		return ret;

	return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}

static const struct udevice_id omap_ehci_dt_ids[] = {
	{ .compatible = "ti,ehci-omap" },
	{ }
};

U_BOOT_DRIVER(usb_omap_ehci) = {
	.name	= "omap-ehci",
	.id	= UCLASS_USB,
	.of_match = omap_ehci_dt_ids,
	.probe = omap_ehci_probe,
	.of_to_plat = ehci_usb_of_to_plat,
	.plat_auto	= sizeof(struct usb_plat),
	.priv_auto	= sizeof(struct ehci_omap_priv_data),
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
29321c05 IY	2	/*
	3	* (C) Copyright 2011 Ilya Yanok, Emcraft Systems
	4	* (C) Copyright 2004-2008
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* Derived from Beagle Board code by
	8	* Sunil Kumar <[email protected]>
	9	* Shashi Ranjan <[email protected]>
	10	*
29321c05	11	*/
1a459660	12
29321c05	13	#include <common.h>
f7ae49fc	14	#include <log.h>
29321c05	15	#include <usb.h>
c05ed00a	16	#include <linux/delay.h>
43b62393 G	17	#include <usb/ulpi.h>
43b62393 G	18	#include <errno.h>
29321c05 IY	19	#include <asm/io.h>
29321c05 IY	20	#include <asm/gpio.h>
43b62393 G	21	#include <asm/arch/ehci.h>
43b62393 G	22	#include <asm/ehci-omap.h>
94ed6619 AF	23	#include <dm.h>
	24	#include <dm/device-internal.h>
	25	#include <dm/lists.h>
	26	#include <power/regulator.h>
676ae068 LS	27
676ae068 LS	28	#include "ehci.h"
29321c05	29
43b62393 G	30	static struct omap_uhh const uhh = (struct omap_uhh )OMAP_UHH_BASE;
	31	static struct omap_usbtll const usbtll = (struct omap_usbtll )OMAP_USBTLL_BASE;
	32	static struct omap_ehci const ehci = (struct omap_ehci )OMAP_EHCI_BASE;
	33
	34	static int omap_uhh_reset(void)
	35	{
835a5559 RQ	36	int timeout = 0;
	37	u32 rev;
	38
	39	rev = readl(&uhh->rev);
	40
	41	/* Soft RESET */
	42	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
	43
	44	switch (rev) {
	45	case OMAP_USBHS_REV1:
	46	/* Wait for soft RESET to complete */
	47	while (!(readl(&uhh->syss) & 0x1)) {
	48	if (timeout > 100) {
	49	printf("%s: RESET timeout\n", __func__);
	50	return -1;
	51	}
	52	udelay(10);
	53	timeout++;
	54	}
	55
	56	/* Set No-Idle, No-Standby */
	57	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	58	break;
	59
	60	default: /* Rev. 2 onwards */
	61
	62	udelay(2); /* Need to wait before accessing SYSCONFIG back */
	63
	64	/* Wait for soft RESET to complete */
	65	while ((readl(&uhh->sysc) & 0x1)) {
	66	if (timeout > 100) {
	67	printf("%s: RESET timeout\n", __func__);
	68	return -1;
	69	}
	70	udelay(10);
	71	timeout++;
	72	}
	73
	74	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	75	break;
	76	}
	77
43b62393 G	78	return 0;
	79	}
	80
	81	static int omap_ehci_tll_reset(void)
	82	{
	83	unsigned long init = get_timer(0);
	84
	85	/* perform TLL soft reset, and wait until reset is complete */
	86	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
	87
	88	/* Wait for TLL reset to complete */
	89	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
	90	if (get_timer(init) > CONFIG_SYS_HZ) {
	91	debug("OMAP EHCI error: timeout resetting TLL\n");
	92	return -EL3RST;
	93	}
	94
	95	return 0;
	96	}
	97
	98	static void omap_usbhs_hsic_init(int port)
	99	{
	100	unsigned int reg;
	101
	102	/* Enable channels now */
	103	reg = readl(&usbtll->channel_conf + port);
	104
	105	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
	106	\| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
	107	\| OMAP_TLL_CHANNEL_CONF_DRVVBUS
	108	\| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
	109	\| OMAP_TLL_CHANNEL_CONF_CHANEN));
	110
	111	writel(reg, &usbtll->channel_conf + port);
	112	}
	113
120503f3	114	#ifdef CONFIG_USB_ULPI
43b62393 G	115	static void omap_ehci_soft_phy_reset(int port)
	116	{
	117	struct ulpi_viewport ulpi_vp;
	118
	119	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	120	ulpi_vp.port_num = port;
	121
	122	ulpi_reset(&ulpi_vp);
	123	}
120503f3 DM	124	#else
	125	static void omap_ehci_soft_phy_reset(int port)
	126	{
	127	return;
	128	}
	129	#endif
43b62393	130
70dbff1f AF	131	struct ehci_omap_priv_data {
	132	struct ehci_ctrl ctrl;
	133	struct omap_ehci *ehci;
	134	#ifdef CONFIG_DM_REGULATOR
	135	struct udevice *vbus_supply;
29321c05	136	#endif
70dbff1f AF	137	enum usb_init_type init_type;
	138	int portnr;
	139	struct phy phy[OMAP_HS_USB_PORTS];
	140	int nports;
	141	};
29321c05	142
29321c05	143	/*
43b62393 G	144	* Initialize the OMAP EHCI controller and PHY.
43b62393 G	145	* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
29321c05 IY	146	* See there for additional Copyrights.
29321c05 IY	147	*/
70dbff1f AF	148	static int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
70dbff1f AF	149	struct udevice *dev)
94ed6619	150	{
29321c05	151	int ret;
43b62393	152	unsigned int i, reg = 0, rev = 0;
29321c05	153
43b62393	154	debug("Initializing OMAP EHCI\n");
29321c05	155
16297cfb	156	ret = board_usb_init(index, USB_INIT_HOST);
29321c05 IY	157	if (ret < 0)
	158	return ret;
	159
70dbff1f AF	160	/* Hold the PHY in RESET for enough time till DIR is high */
	161	/* Refer: ISSUE1 */
	162	udelay(10);
29321c05	163
43b62393 G	164	ret = omap_uhh_reset();
	165	if (ret < 0)
	166	return ret;
29321c05	167
43b62393 G	168	ret = omap_ehci_tll_reset();
	169	if (ret)
	170	return ret;
29321c05 IY	171
	172	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP \|
	173	OMAP_USBTLL_SYSCONFIG_SIDLEMODE \|
43b62393	174	OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
29321c05 IY	175
29321c05 IY	176	/* Put UHH in NoIdle/NoStandby mode */
43b62393 G	177	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	178
	179	/* setup ULPI bypass and burst configurations */
	180	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
	181	(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN \|
	182	OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN \|
	183	OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
	184
	185	rev = readl(&uhh->rev);
	186	if (rev == OMAP_USBHS_REV1) {
	187	if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
	188	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	189	else
	190	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	191
	192	if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
	193	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
	194	else
90579fdd	195	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
43b62393 G	196
	197	if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
	198	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	199	else
90579fdd	200	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
43b62393	201	} else if (rev == OMAP_USBHS_REV2) {
d3d037ae	202
43b62393 G	203	clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR \| OMAP_P2_MODE_CLEAR),
	204	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	205
d3d037ae DM	206	/* Clear port mode fields for PHY mode */
	207
	208	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	209	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	210
	211	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	212	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	213
	214	} else if (rev == OMAP_USBHS_REV2_1) {
	215
	216	clrsetbits_le32(&reg,
	217	(OMAP_P1_MODE_CLEAR \|
	218	OMAP_P2_MODE_CLEAR \|
	219	OMAP_P3_MODE_CLEAR),
	220	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	221
	222	/* Clear port mode fields for PHY mode */
43b62393 G	223
	224	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	225	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	226
	227	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	228	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	229
	230	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
	231	setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	232	}
	233
	234	debug("OMAP UHH_REVISION 0x%x\n", rev);
	235	writel(reg, &uhh->hostconfig);
	236
	237	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	238	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
	239	omap_usbhs_hsic_init(i);
29321c05	240
70dbff1f AF	241	/*
	242	* Refer ISSUE1:
	243	* Hold the PHY in RESET for enough time till
	244	* PHY is settled and ready
	245	*/
	246	udelay(10);
29321c05	247
43b62393 G	248	/*
	249	* An undocumented "feature" in the OMAP3 EHCI controller,
	250	* causes suspended ports to be taken out of suspend when
	251	* the USBCMD.Run/Stop bit is cleared (for example when
	252	* we do ehci_bus_suspend).
	253	* This breaks suspend-resume if the root-hub is allowed
	254	* to suspend. Writing 1 to this undocumented register bit
	255	* disables this feature and restores normal behavior.
	256	*/
	257	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
	258
	259	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	260	if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
	261	omap_ehci_soft_phy_reset(i);
	262
43b62393	263	debug("OMAP EHCI init done\n");
29321c05 IY	264	return 0;
29321c05 IY	265	}
94ed6619	266
94ed6619 AF	267	static struct omap_usbhs_board_data usbhs_bdata = {
	268	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	269	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	270	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	271	};
	272
	273	static void omap_usbhs_set_mode(u8 index, const char *mode)
	274	{
	275	if (!strcmp(mode, "ehci-phy"))
	276	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
	277	else if (!strcmp(mode, "ehci-tll"))
	278	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
	279	else if (!strcmp(mode, "ehci-hsic"))
	280	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
	281	}
	282
	283	static int omap_usbhs_probe(struct udevice *dev)
	284	{
	285	u8 i;
	286	const char *mode;
	287	char prop[11];
	288
	289	/* Go through each port portX-mode to determing phy mode */
	290	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
	291	snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
	292	mode = dev_read_string(dev, prop);
	293
	294	/* If the portX-mode exists, set the mode */
	295	if (mode)
	296	omap_usbhs_set_mode(i, mode);
	297	}
	298
ac0c125b	299	return 0;
94ed6619 AF	300	}
	301
	302	static const struct udevice_id omap_usbhs_dt_ids[] = {
	303	{ .compatible = "ti,usbhs-host" },
	304	{ }
	305	};
	306
	307	U_BOOT_DRIVER(usb_omaphs_host) = {
	308	.name = "usbhs-host",
	309	.id = UCLASS_SIMPLE_BUS,
	310	.of_match = omap_usbhs_dt_ids,
	311	.probe = omap_usbhs_probe,
	312	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	313	};
	314
d1998a9f	315	static int ehci_usb_of_to_plat(struct udevice *dev)
94ed6619	316	{
8a8d24bd	317	struct usb_plat *plat = dev_get_plat(dev);
94ed6619 AF	318
	319	plat->init_type = USB_INIT_HOST;
	320
	321	return 0;
	322	}
	323
70dbff1f AF	324	/*
	325	* This driver references phys based on the USB port. If
	326	* the port is unused, the corresponding phy is listed as NULL
	327	* which generic_phy_init_bulk treats as an error, so we need
	328	* a custom one that tolerates empty phys
	329	*/
	330	static int omap_ehci_phy_get(struct udevice *dev)
	331	{
	332	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
	333	int i, ret;
	334
	335	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
	336	ret = generic_phy_get_by_index(dev, i, &priv->phy[i]);
	337	if (ret && ret != -ENOENT)
	338	return ret;
	339	};
	340
	341	return 0;
	342	};
	343
94ed6619 AF	344	static int omap_ehci_probe(struct udevice *dev)
94ed6619 AF	345	{
8a8d24bd	346	struct usb_plat *plat = dev_get_plat(dev);
94ed6619 AF	347	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
	348	struct ehci_hccr *hccr;
	349	struct ehci_hcor *hcor;
ac0c125b	350	int ret;
94ed6619	351
8613c8d8	352	priv->ehci = dev_read_addr_ptr(dev);
8b85dfc6	353	priv->portnr = dev_seq(dev);
94ed6619 AF	354	priv->init_type = plat->init_type;
	355
	356	hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
	357	hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
	358
70dbff1f AF	359	/* Identify Phys */
	360	ret = omap_ehci_phy_get(dev);
	361	if (ret) {
	362	printf("Failed to get phys\n");
	363	return ret;
	364	}
	365
	366	/* Register the EHCI */
	367	ret = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
	368	if (ret) {
	369	printf("Failed to register EHCI\n");
	370	return ret;
	371	}
	372
	373	ret = omap_ehci_hcd_init(0, &usbhs_bdata, dev);
ac0c125b AF	374	if (ret)
	375	return ret;
	376
94ed6619 AF	377	return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
	378	}
	379
	380	static const struct udevice_id omap_ehci_dt_ids[] = {
	381	{ .compatible = "ti,ehci-omap" },
	382	{ }
	383	};
	384
	385	U_BOOT_DRIVER(usb_omap_ehci) = {
	386	.name = "omap-ehci",
	387	.id = UCLASS_USB,
	388	.of_match = omap_ehci_dt_ids,
	389	.probe = omap_ehci_probe,
d1998a9f	390	.of_to_plat = ehci_usb_of_to_plat,
8a8d24bd	391	.plat_auto = sizeof(struct usb_plat),
41575d8e	392	.priv_auto = sizeof(struct ehci_omap_priv_data),
94ed6619 AF	393	.remove = ehci_deregister,
	394	.ops = &ehci_usb_ops,
	395	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	396	};