[J-u-boot.git] / drivers / spi / kirkwood_spi.c

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <[email protected]>
 *
 * Derived from drivers/spi/mpc8xxx_spi.c
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/mpp.h>
#endif
#include <asm/arch-mvebu/spi.h>

static void _spi_cs_activate(struct kwspi_registers *reg)
{
	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static void _spi_cs_deactivate(struct kwspi_registers *reg)
{
	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
		     const void *dout, void *din, unsigned long flags)
{
	unsigned int tmpdout, tmpdin;
	int tm, isread = 0;

	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		_spi_cs_activate(reg);

	/*
	 * handle data in 8-bit chunks
	 * TBD: 2byte xfer mode to be enabled
	 */
	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);

	while (bitlen > 4) {
		debug("loopstart bitlen %d\n", bitlen);
		tmpdout = 0;

		/* Shift data so it's msb-justified */
		if (dout)
			tmpdout = *(u32 *)dout & 0xff;

		clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
		writel(tmpdout, &reg->dout);	/* Write the data out */
		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
		      tmpdout, bitlen);

		/*
		 * Wait for SPI transmit to get out
		 * or time out (1 second = 1000 ms)
		 * The NE event must be read and cleared first
		 */
		for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
			if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
				isread = 1;
				tmpdin = readl(&reg->din);
				debug("spi_xfer: din %p..%08x read\n",
				      din, tmpdin);

				if (din) {
					*((u8 *)din) = (u8)tmpdin;
					din += 1;
				}
				if (dout)
					dout += 1;
				bitlen -= 8;
			}
			if (isread)
				break;
		}
		if (tm >= KWSPI_TIMEOUT)
			printf("*** spi_xfer: Time out during SPI transfer\n");

		debug("loopend bitlen %d\n", bitlen);
	}

	if (flags & SPI_XFER_END)
		_spi_cs_deactivate(reg);

	return 0;
}

#ifndef CONFIG_DM_SPI

static struct kwspi_registers *spireg =
	(struct kwspi_registers *)MVEBU_SPI_BASE;

#ifdef CONFIG_KIRKWOOD
static u32 cs_spi_mpp_back[2];
#endif

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				unsigned int max_hz, unsigned int mode)
{
	struct spi_slave *slave;
	u32 data;
#ifdef CONFIG_KIRKWOOD
	static const u32 kwspi_mpp_config[2][2] = {
		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
	};
#endif

	if (!spi_cs_is_valid(bus, cs))
		return NULL;

	slave = spi_alloc_slave_base(bus, cs);
	if (!slave)
		return NULL;

	writel(KWSPI_SMEMRDY, &spireg->ctrl);

	/* calculate spi clock prescaller using max_hz */
	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;

	/* program spi clock prescaller using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
	debug("data = 0x%08x\n", data);

	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
	writel(KWSPI_IRQMASK, &spireg->irq_mask);

#ifdef CONFIG_KIRKWOOD
	/* program mpp registers to select  SPI_CSn */
	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
#endif

	return slave;
}

void spi_free_slave(struct spi_slave *slave)
{
#ifdef CONFIG_KIRKWOOD
	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
#endif
	free(slave);
}

#if defined(CONFIG_SYS_KW_SPI_MPP)
u32 spi_mpp_backup[4];
#endif

__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
	return 0;
}

int spi_claim_bus(struct spi_slave *slave)
{
#if defined(CONFIG_SYS_KW_SPI_MPP)
	u32 config;
	u32 spi_mpp_config[4];

	config = CONFIG_SYS_KW_SPI_MPP;

	if (config & MOSI_MPP6)
		spi_mpp_config[0] = MPP6_SPI_MOSI;
	else
		spi_mpp_config[0] = MPP1_SPI_MOSI;

	if (config & SCK_MPP10)
		spi_mpp_config[1] = MPP10_SPI_SCK;
	else
		spi_mpp_config[1] = MPP2_SPI_SCK;

	if (config & MISO_MPP11)
		spi_mpp_config[2] = MPP11_SPI_MISO;
	else
		spi_mpp_config[2] = MPP3_SPI_MISO;

	spi_mpp_config[3] = 0;
	spi_mpp_backup[3] = 0;

	/* set new spi mpp and save current mpp config */
	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
#endif

	return board_spi_claim_bus(slave);
}

__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
{
}

void spi_release_bus(struct spi_slave *slave)
{
#if defined(CONFIG_SYS_KW_SPI_MPP)
	kirkwood_mpp_conf(spi_mpp_backup, NULL);
#endif

	board_spi_release_bus(slave);
}

#ifndef CONFIG_SPI_CS_IS_VALID
/*
 * you can define this function board specific
 * define above CONFIG in board specific config file and
 * provide the function in board specific src file
 */
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && (cs == 0 || cs == 1);
}
#endif

void spi_init(void)
{
}

void spi_cs_activate(struct spi_slave *slave)
{
	_spi_cs_activate(spireg);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	_spi_cs_deactivate(spireg);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	     const void *dout, void *din, unsigned long flags)
{
	return _spi_xfer(spireg, bitlen, dout, din, flags);
}

#else

/* Here now the DM part */

struct mvebu_spi_platdata {
	struct kwspi_registers *spireg;
};

struct mvebu_spi_priv {
	struct kwspi_registers *spireg;
};

static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	u32 data;

	/* calculate spi clock prescaller using max_hz */
	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;

	/* program spi clock prescaler using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
	debug("data = 0x%08x\n", data);

	return 0;
}

static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	u32 data = readl(&reg->cfg);

	data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);

	if (mode & SPI_CPHA)
		data |= KWSPI_CPHA;
	if (mode & SPI_CPOL)
		data |= KWSPI_CPOL;
	if (mode & SPI_LSB_FIRST)
		data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);

	writel(data, &reg->cfg);

	return 0;
}

static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
			  const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}

static int mvebu_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	/* Configure the chip-select in the CTRL register */
	clrsetbits_le32(&plat->spireg->ctrl,
			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
			spi_chip_select(dev) << KWSPI_CS_SHIFT);

	return 0;
}

static int mvebu_spi_probe(struct udevice *bus)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;

	writel(KWSPI_SMEMRDY, &reg->ctrl);
	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
	writel(KWSPI_IRQMASK, &reg->irq_mask);

	return 0;
}

static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);

	return 0;
}

static const struct dm_spi_ops mvebu_spi_ops = {
	.claim_bus	= mvebu_spi_claim_bus,
	.xfer		= mvebu_spi_xfer,
	.set_speed	= mvebu_spi_set_speed,
	.set_mode	= mvebu_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id mvebu_spi_ids[] = {
	{ .compatible = "marvell,armada-375-spi" },
	{ .compatible = "marvell,armada-380-spi" },
	{ .compatible = "marvell,armada-xp-spi" },
	{ }
};

U_BOOT_DRIVER(mvebu_spi) = {
	.name = "mvebu_spi",
	.id = UCLASS_SPI,
	.of_match = mvebu_spi_ids,
	.ops = &mvebu_spi_ops,
	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
	.probe = mvebu_spi_probe,
};
#endif
Commit	Line	Data
5710de45 PW	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Prafulla Wadaskar <[email protected]>
	5	*
	6	* Derived from drivers/spi/mpc8xxx_spi.c
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
5710de45 PW	9	*/
	10
	11	#include <common.h>
9985bdb1	12	#include <dm.h>
5710de45 PW	13	#include <malloc.h>
5710de45 PW	14	#include <spi.h>
a7efd719	15	#include <asm/io.h>
3dc23f78	16	#include <asm/arch/soc.h>
4aceea20	17	#ifdef CONFIG_KIRKWOOD
5710de45	18	#include <asm/arch/mpp.h>
4aceea20	19	#endif
3e972cb9	20	#include <asm/arch-mvebu/spi.h>
5710de45	21
9985bdb1 SR	22	static void _spi_cs_activate(struct kwspi_registers *reg)
	23	{
	24	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
	25	}
	26
	27	static void _spi_cs_deactivate(struct kwspi_registers *reg)
	28	{
	29	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
	30	}
	31
	32	static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
	33	const void dout, void din, unsigned long flags)
	34	{
	35	unsigned int tmpdout, tmpdin;
	36	int tm, isread = 0;
	37
	38	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
	39
	40	if (flags & SPI_XFER_BEGIN)
	41	_spi_cs_activate(reg);
	42
	43	/*
	44	* handle data in 8-bit chunks
	45	* TBD: 2byte xfer mode to be enabled
	46	*/
	47	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
	48
	49	while (bitlen > 4) {
	50	debug("loopstart bitlen %d\n", bitlen);
	51	tmpdout = 0;
	52
	53	/* Shift data so it's msb-justified */
	54	if (dout)
	55	tmpdout = (u32 )dout & 0xff;
	56
	57	clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
	58	writel(tmpdout, &reg->dout); /* Write the data out */
	59	debug("*** spi_xfer: ... %08x written, bitlen %d\n",
	60	tmpdout, bitlen);
	61
	62	/*
	63	* Wait for SPI transmit to get out
	64	* or time out (1 second = 1000 ms)
	65	* The NE event must be read and cleared first
	66	*/
	67	for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
	68	if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
	69	isread = 1;
	70	tmpdin = readl(&reg->din);
	71	debug("spi_xfer: din %p..%08x read\n",
	72	din, tmpdin);
	73
	74	if (din) {
	75	((u8 )din) = (u8)tmpdin;
	76	din += 1;
	77	}
	78	if (dout)
	79	dout += 1;
	80	bitlen -= 8;
	81	}
	82	if (isread)
	83	break;
	84	}
	85	if (tm >= KWSPI_TIMEOUT)
86	printf("*** spi_xfer: Time out during SPI transfer\n");
87
88	debug("loopend bitlen %d\n", bitlen);
89	}
90
91	if (flags & SPI_XFER_END)
92	_spi_cs_deactivate(reg);
93
94	return 0;
95	}
96
97	#ifndef CONFIG_DM_SPI
98
4fd7717e SR	99	static struct kwspi_registers *spireg =
4fd7717e SR	100	(struct kwspi_registers *)MVEBU_SPI_BASE;
5710de45	101
4aceea20	102	#ifdef CONFIG_KIRKWOOD
0299046e	103	static u32 cs_spi_mpp_back[2];
4aceea20	104	#endif
ca880679	105
5710de45 PW	106	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	107	unsigned int max_hz, unsigned int mode)
	108	{
	109	struct spi_slave *slave;
	110	u32 data;
4aceea20	111	#ifdef CONFIG_KIRKWOOD
9d86f0c3 AA	112	static const u32 kwspi_mpp_config[2][2] = {
	113	{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
	114	{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
	115	};
4aceea20	116	#endif
5710de45 PW	117
	118	if (!spi_cs_is_valid(bus, cs))
	119	return NULL;
	120
d3504fee	121	slave = spi_alloc_slave_base(bus, cs);
5710de45 PW	122	if (!slave)
	123	return NULL;
	124
c032174f	125	writel(KWSPI_SMEMRDY, &spireg->ctrl);
5710de45 PW	126
5710de45 PW	127	/* calculate spi clock prescaller using max_hz */
8203b201 VL	128	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
	129	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	130	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
5710de45 PW	131
	132	/* program spi clock prescaller using max_hz */
	133	writel(KWSPI_ADRLEN_3BYTE \| data, &spireg->cfg);
bf9b86dc	134	debug("data = 0x%08x\n", data);
5710de45 PW	135
5710de45 PW	136	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
3f843551	137	writel(KWSPI_IRQMASK, &spireg->irq_mask);
5710de45	138
4aceea20	139	#ifdef CONFIG_KIRKWOOD
5710de45	140	/* program mpp registers to select SPI_CSn */
9d86f0c3	141	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
4aceea20	142	#endif
5710de45 PW	143
	144	return slave;
	145	}
	146
	147	void spi_free_slave(struct spi_slave *slave)
	148	{
4aceea20	149	#ifdef CONFIG_KIRKWOOD
ca880679	150	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
4aceea20	151	#endif
5710de45 PW	152	free(slave);
	153	}
	154
ac486e3b VL	155	#if defined(CONFIG_SYS_KW_SPI_MPP)
	156	u32 spi_mpp_backup[4];
	157	#endif
	158
24934fea VL	159	__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
	160	{
	161	return 0;
	162	}
	163
5710de45 PW	164	int spi_claim_bus(struct spi_slave *slave)
5710de45 PW	165	{
ac486e3b VL	166	#if defined(CONFIG_SYS_KW_SPI_MPP)
	167	u32 config;
	168	u32 spi_mpp_config[4];
	169
	170	config = CONFIG_SYS_KW_SPI_MPP;
	171
	172	if (config & MOSI_MPP6)
	173	spi_mpp_config[0] = MPP6_SPI_MOSI;
	174	else
	175	spi_mpp_config[0] = MPP1_SPI_MOSI;
	176
	177	if (config & SCK_MPP10)
	178	spi_mpp_config[1] = MPP10_SPI_SCK;
	179	else
	180	spi_mpp_config[1] = MPP2_SPI_SCK;
	181
	182	if (config & MISO_MPP11)
	183	spi_mpp_config[2] = MPP11_SPI_MISO;
	184	else
	185	spi_mpp_config[2] = MPP3_SPI_MISO;
	186
	187	spi_mpp_config[3] = 0;
	188	spi_mpp_backup[3] = 0;
	189
	190	/* set new spi mpp and save current mpp config */
	191	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
ac486e3b VL	192	#endif
ac486e3b VL	193
24934fea VL	194	return board_spi_claim_bus(slave);
	195	}
	196
	197	__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
	198	{
5710de45 PW	199	}
	200
	201	void spi_release_bus(struct spi_slave *slave)
	202	{
ac486e3b VL	203	#if defined(CONFIG_SYS_KW_SPI_MPP)
	204	kirkwood_mpp_conf(spi_mpp_backup, NULL);
	205	#endif
24934fea VL	206
24934fea VL	207	board_spi_release_bus(slave);
5710de45 PW	208	}
	209
	210	#ifndef CONFIG_SPI_CS_IS_VALID
	211	/*
	212	* you can define this function board specific
	213	* define above CONFIG in board specific config file and
	214	* provide the function in board specific src file
	215	*/
	216	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	217	{
bf9b86dc	218	return bus == 0 && (cs == 0 \|\| cs == 1);
5710de45 PW	219	}
	220	#endif
	221
efa4e43a MW	222	void spi_init(void)
	223	{
	224	}
	225
5710de45 PW	226	void spi_cs_activate(struct spi_slave *slave)
5710de45 PW	227	{
18dd3b22	228	_spi_cs_activate(spireg);
5710de45 PW	229	}
	230
	231	void spi_cs_deactivate(struct spi_slave *slave)
	232	{
18dd3b22	233	_spi_cs_deactivate(spireg);
5710de45 PW	234	}
5710de45 PW	235
9985bdb1 SR	236	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
9985bdb1 SR	237	const void dout, void din, unsigned long flags)
5710de45	238	{
9985bdb1 SR	239	return _spi_xfer(spireg, bitlen, dout, din, flags);
9985bdb1 SR	240	}
5710de45	241
9985bdb1	242	#else
5710de45	243
9985bdb1	244	/* Here now the DM part */
5710de45	245
9985bdb1 SR	246	struct mvebu_spi_platdata {
	247	struct kwspi_registers *spireg;
	248	};
5710de45	249
9985bdb1 SR	250	struct mvebu_spi_priv {
	251	struct kwspi_registers *spireg;
	252	};
5710de45	253
9985bdb1 SR	254	static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
	255	{
	256	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	257	struct kwspi_registers *reg = plat->spireg;
	258	u32 data;
5710de45	259
9985bdb1 SR	260	/* calculate spi clock prescaller using max_hz */
	261	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
	262	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	263	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
5710de45	264
9985bdb1 SR	265	/* program spi clock prescaler using max_hz */
	266	writel(KWSPI_ADRLEN_3BYTE \| data, &reg->cfg);
	267	debug("data = 0x%08x\n", data);
5710de45	268
9985bdb1 SR	269	return 0;
9985bdb1 SR	270	}
5710de45	271
9985bdb1 SR	272	static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
9985bdb1 SR	273	{
ebfa18cb CP	274	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	275	struct kwspi_registers *reg = plat->spireg;
	276	u32 data = readl(&reg->cfg);
	277
	278	data &= ~(KWSPI_CPHA \| KWSPI_CPOL \| KWSPI_RXLSBF \| KWSPI_TXLSBF);
	279
	280	if (mode & SPI_CPHA)
	281	data \|= KWSPI_CPHA;
	282	if (mode & SPI_CPOL)
	283	data \|= KWSPI_CPOL;
	284	if (mode & SPI_LSB_FIRST)
	285	data \|= (KWSPI_RXLSBF \| KWSPI_TXLSBF);
	286
	287	writel(data, &reg->cfg);
	288
9985bdb1 SR	289	return 0;
9985bdb1 SR	290	}
5710de45	291
9985bdb1 SR	292	static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
	293	const void dout, void din, unsigned long flags)
	294	{
	295	struct udevice *bus = dev->parent;
	296	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	297
	298	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
	299	}
	300
9fc56631 SR	301	static int mvebu_spi_claim_bus(struct udevice *dev)
	302	{
	303	struct udevice *bus = dev->parent;
	304	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	305
	306	/* Configure the chip-select in the CTRL register */
	307	clrsetbits_le32(&plat->spireg->ctrl,
	308	KWSPI_CS_MASK << KWSPI_CS_SHIFT,
	309	spi_chip_select(dev) << KWSPI_CS_SHIFT);
	310
	311	return 0;
	312	}
	313
9985bdb1 SR	314	static int mvebu_spi_probe(struct udevice *bus)
	315	{
	316	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	317	struct kwspi_registers *reg = plat->spireg;
	318
	319	writel(KWSPI_SMEMRDY, &reg->ctrl);
	320	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
	321	writel(KWSPI_IRQMASK, &reg->irq_mask);
5710de45 PW	322
	323	return 0;
	324	}
18dd3b22	325
9985bdb1	326	static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
18dd3b22	327	{
9985bdb1 SR	328	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	329
	330	plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
	331
	332	return 0;
18dd3b22	333	}
9985bdb1 SR	334
9985bdb1 SR	335	static const struct dm_spi_ops mvebu_spi_ops = {
9fc56631	336	.claim_bus = mvebu_spi_claim_bus,
9985bdb1 SR	337	.xfer = mvebu_spi_xfer,
	338	.set_speed = mvebu_spi_set_speed,
	339	.set_mode = mvebu_spi_set_mode,
	340	/*
	341	* cs_info is not needed, since we require all chip selects to be
	342	* in the device tree explicitly
	343	*/
	344	};
	345
	346	static const struct udevice_id mvebu_spi_ids[] = {
951f1b5f	347	{ .compatible = "marvell,armada-375-spi" },
9985bdb1 SR	348	{ .compatible = "marvell,armada-380-spi" },
	349	{ .compatible = "marvell,armada-xp-spi" },
	350	{ }
	351	};
	352
	353	U_BOOT_DRIVER(mvebu_spi) = {
	354	.name = "mvebu_spi",
	355	.id = UCLASS_SPI,
	356	.of_match = mvebu_spi_ids,
	357	.ops = &mvebu_spi_ops,
	358	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
	359	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
	360	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
	361	.probe = mvebu_spi_probe,
	362	};
	363	#endif