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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * (C) Copyright 2005 | |
4 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
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5 | */ |
6 | ||
7 | /* | |
8 | * TQM8349 board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
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14 | /* |
15 | * High Level Configuration Options | |
16 | */ | |
17 | #define CONFIG_E300 1 /* E300 Family */ | |
e6f2e902 | 18 | |
e6f2e902 | 19 | /* board pre init: do not call, nothing to do */ |
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20 | |
21 | /* detect the number of flash banks */ | |
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22 | |
23 | /* | |
24 | * DDR Setup | |
25 | */ | |
df939e16 | 26 | /* DDR is system memory*/ |
8a81bfd2 | 27 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
df939e16 JH |
28 | #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ |
29 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
30 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ | |
e6f2e902 | 31 | |
df939e16 | 32 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
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33 | |
34 | /* | |
35 | * FLASH on the Local Bus | |
36 | */ | |
6d0f6bcf JCPV |
37 | #undef CONFIG_SYS_FLASH_CHECKSUM |
38 | #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ | |
39 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ | |
df939e16 | 40 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ |
e6f2e902 MB |
41 | |
42 | /* | |
43 | * FLASH bank number detection | |
44 | */ | |
45 | ||
46 | /* | |
df939e16 JH |
47 | * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of |
48 | * Flash banks has to be determined at runtime and stored in a gloabl variable | |
49 | * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is | |
50 | * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array | |
51 | * flash_info, and should be made sufficiently large to accomodate the number | |
52 | * of banks that might actually be detected. Since most (all?) Flash related | |
53 | * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on | |
54 | * the board, it is defined as tqm834x_num_flash_banks. | |
e6f2e902 | 55 | */ |
6d0f6bcf | 56 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
e6f2e902 | 57 | |
df939e16 | 58 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ |
e6f2e902 | 59 | |
e6f2e902 | 60 | |
e6f2e902 | 61 | /* disable remaining mappings */ |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_BR1_PRELIM 0x00000000 |
63 | #define CONFIG_SYS_OR1_PRELIM 0x00000000 | |
6d0f6bcf JCPV |
64 | |
65 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 | |
66 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
6d0f6bcf JCPV |
67 | |
68 | #define CONFIG_SYS_BR3_PRELIM 0x00000000 | |
69 | #define CONFIG_SYS_OR3_PRELIM 0x00000000 | |
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70 | |
71 | /* | |
72 | * Monitor config | |
73 | */ | |
14d0a02a | 74 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
e6f2e902 | 75 | |
6d0f6bcf | 76 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
4681e673 | 77 | # define CONFIG_SYS_RAMBOOT |
e6f2e902 | 78 | #else |
4681e673 | 79 | # undef CONFIG_SYS_RAMBOOT |
e6f2e902 MB |
80 | #endif |
81 | ||
6d0f6bcf | 82 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
df939e16 JH |
83 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ |
84 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
e6f2e902 | 85 | |
df939e16 JH |
86 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
87 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 88 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e6f2e902 | 89 | |
df939e16 JH |
90 | /* Reserve 384 kB = 3 sect. for Mon */ |
91 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
92 | /* Reserve 512 kB for malloc */ | |
93 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
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94 | |
95 | /* | |
96 | * Serial Port | |
97 | */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_NS16550_SERIAL |
99 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
100 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
e6f2e902 | 101 | |
6d0f6bcf | 102 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
df939e16 | 103 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
e6f2e902 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
106 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
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107 | |
108 | /* | |
109 | * I2C | |
110 | */ | |
00f792e0 HS |
111 | #define CONFIG_SYS_I2C |
112 | #define CONFIG_SYS_I2C_FSL | |
113 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
114 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
115 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
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116 | |
117 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ | |
df939e16 JH |
118 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
119 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ | |
120 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ | |
121 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ | |
e6f2e902 MB |
122 | |
123 | /* I2C RTC */ | |
df939e16 JH |
124 | #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ |
125 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
e6f2e902 | 126 | |
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127 | /* |
128 | * TSEC | |
129 | */ | |
e6f2e902 | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
df939e16 | 132 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 133 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
df939e16 | 134 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) |
e6f2e902 MB |
135 | |
136 | #if defined(CONFIG_TSEC_ENET) | |
137 | ||
255a3577 KP |
138 | #define CONFIG_TSEC1 1 |
139 | #define CONFIG_TSEC1_NAME "TSEC0" | |
140 | #define CONFIG_TSEC2 1 | |
141 | #define CONFIG_TSEC2_NAME "TSEC1" | |
df939e16 JH |
142 | #define TSEC1_PHY_ADDR 2 |
143 | #define TSEC2_PHY_ADDR 1 | |
144 | #define TSEC1_PHYIDX 0 | |
145 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
146 | #define TSEC1_FLAGS TSEC_GIGABIT |
147 | #define TSEC2_FLAGS TSEC_GIGABIT | |
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148 | |
149 | /* Options are: TSEC[0-1] */ | |
df939e16 | 150 | #define CONFIG_ETHPRIME "TSEC0" |
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151 | |
152 | #endif /* CONFIG_TSEC_ENET */ | |
153 | ||
e6f2e902 MB |
154 | #if defined(CONFIG_PCI) |
155 | ||
df939e16 | 156 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6902df56 RJ |
157 | |
158 | /* PCI1 host bridge */ | |
df939e16 JH |
159 | #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 |
160 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
161 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
162 | #define CONFIG_SYS_PCI1_MMIO_BASE \ | |
163 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
164 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
165 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
166 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
167 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
168 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
e6f2e902 | 169 | |
e6f2e902 | 170 | #undef CONFIG_EEPRO100 |
63ff004c | 171 | #define CONFIG_EEPRO100 |
e6f2e902 MB |
172 | #undef CONFIG_TULIP |
173 | ||
174 | #if !defined(CONFIG_PCI_PNP) | |
6d0f6bcf JCPV |
175 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE |
176 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE | |
6902df56 | 177 | #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ |
e6f2e902 MB |
178 | #endif |
179 | ||
6d0f6bcf | 180 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
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181 | |
182 | #endif /* CONFIG_PCI */ | |
183 | ||
184 | /* | |
185 | * Environment | |
186 | */ | |
929b79a0 | 187 | |
df939e16 JH |
188 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
189 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
e6f2e902 | 190 | |
a1aa0bb5 JL |
191 | /* |
192 | * BOOTP options | |
193 | */ | |
194 | #define CONFIG_BOOTP_BOOTFILESIZE | |
a1aa0bb5 | 195 | |
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196 | /* |
197 | * Miscellaneous configurable options | |
198 | */ | |
df939e16 | 199 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
e6f2e902 | 200 | |
df939e16 | 201 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
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202 | |
203 | /* | |
204 | * For booting Linux, the board info and command line data | |
9f530d59 | 205 | * have to be in the first 256 MB of memory, since this is |
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206 | * the maximum mapped by the Linux kernel during initialization. |
207 | */ | |
df939e16 JH |
208 | /* Initial Memory map for Linux */ |
209 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
e6f2e902 | 210 | |
9260a561 | 211 | /* System IO Config */ |
3c9b1ee1 | 212 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 213 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
9260a561 | 214 | |
2688e2f9 | 215 | /* PCI */ |
6fe16a87 | 216 | #ifdef CONFIG_PCI |
842033e6 | 217 | #define CONFIG_PCI_INDIRECT_BRIDGE |
6fe16a87 | 218 | #endif |
2688e2f9 | 219 | |
2694690e | 220 | #if defined(CONFIG_CMD_KGDB) |
e6f2e902 | 221 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
e6f2e902 MB |
222 | #endif |
223 | ||
224 | /* | |
225 | * Environment Configuration | |
226 | */ | |
227 | ||
df939e16 JH |
228 | /* default location for tftp and bootm */ |
229 | #define CONFIG_LOADADDR 400000 | |
e6f2e902 | 230 | |
e6f2e902 MB |
231 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
232 | "netdev=eth0\0" \ | |
b931b3a9 | 233 | "hostname=tqm834x\0" \ |
e6f2e902 | 234 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 235 | "nfsroot=${serverip}:${rootpath}\0" \ |
e6f2e902 | 236 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
237 | "addip=setenv bootargs ${bootargs} " \ |
238 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
239 | ":${hostname}:${netdev}:off panic=1\0" \ | |
df939e16 | 240 | "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
4681e673 | 241 | "flash_nfs_old=run nfsargs addip addcons;" \ |
fe126d8b | 242 | "bootm ${kernel_addr}\0" \ |
4681e673 WD |
243 | "flash_nfs=run nfsargs addip addcons;" \ |
244 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
245 | "flash_self_old=run ramargs addip addcons;" \ | |
fe126d8b | 246 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
4681e673 WD |
247 | "flash_self=run ramargs addip addcons;" \ |
248 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
249 | "net_nfs_old=tftp 400000 ${bootfile};" \ | |
250 | "run nfsargs addip addcons;bootm\0" \ | |
251 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
252 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
253 | "run nfsargs addip addcons; " \ | |
254 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
e6f2e902 | 255 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
4681e673 WD |
256 | "bootfile=tqm834x/uImage\0" \ |
257 | "fdtfile=tqm834x/tqm834x.dtb\0" \ | |
258 | "kernel_addr_r=400000\0" \ | |
259 | "fdt_addr_r=600000\0" \ | |
260 | "ramdisk_addr_r=800000\0" \ | |
261 | "kernel_addr=800C0000\0" \ | |
262 | "fdt_addr=800A0000\0" \ | |
263 | "ramdisk_addr=80300000\0" \ | |
264 | "u-boot=tqm834x/u-boot.bin\0" \ | |
265 | "load=tftp 200000 ${u-boot}\0" \ | |
266 | "update=protect off 80000000 +${filesize};" \ | |
267 | "era 80000000 +${filesize};" \ | |
268 | "cp.b 200000 80000000 ${filesize}\0" \ | |
d8ab58b2 | 269 | "upd=run load update\0" \ |
e6f2e902 MB |
270 | "" |
271 | ||
272 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
273 | ||
274 | /* | |
275 | * JFFS2 partitions | |
276 | */ | |
277 | /* mtdparts command line support */ | |
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278 | |
279 | /* default mtd partition table */ | |
e6f2e902 | 280 | #endif /* __CONFIG_H */ |