[J-u-boot.git] / board / fads / fads.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
 * and Dan Malek
 *
 * Modified by, Yuli Barcohen, Arabella Software Ltd., [email protected]
 *
 * This header file contains values common to all FADS family boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/****************************************************************************
 * Flash Memory Map as used by U-Boot:
 *
 *                          Start Address    Length
 * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
 * |                       | 0xFE00_0100     Reset Vector
 * +                       + 0xFE0?_????
 * | U-Boot code           |
 * |                       |
 * +-----------------------+ 0xFE04_0000 (sector border)
 * |                       |
 * |                       |
 * | U-Boot environment    |
 * |                       |                                 ^
 * |                       |                                 | U-Boot
 * +=======================+ 0xFE08_0000 (sector border)    -----------------
 * | Available             |                                 | Applications
 * | ...                   |                                 v
 *
 *****************************************************************************/

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
    "dhcp;"									\
    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "		\
    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
    "bootm"

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */

/*
 * New MPC86xADS and Duet provide two Ethernet connectivity options:
 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
 * got FEC so FEC is the default.
 */
#ifndef CONFIG_ADS
#undef	CONFIG_SCC1_ENET		/* Disable SCC1 ethernet */
#define	CONFIG_FEC_ENET			/* Use FEC ethernet  */
#else					/* Old ADS has not got FEC option */
#define	CONFIG_SCC1_ENET		/* Use SCC1 ethernet */
#undef	CONFIG_FEC_ENET			/* No FEC ethernet  */
#endif /* !CONFIG_ADS */

#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#ifdef CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#endif

#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
			 | CFG_CMD_DHCP   \
			 | CFG_CMD_IMMAP  \
			 | CFG_CMD_JFFS2  \
			 | CFG_CMD_MII    \
			 | CFG_CMD_PCMCIA \
			 | CFG_CMD_PING   \
			)
#endif /* !CONFIG_COMMANDS */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#undef	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_LOAD_ADDR	 	0x00100000

#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
#define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
#elif defined(CONFIG_FADS)				/* Old/new FADS */
#define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
#else							/* Old ADS */
#define	CFG_SDRAM_SIZE		0x00000000		/* No SDRAM */
#endif

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#if (CFG_SDRAM_SIZE)
#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
#else
#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
#endif /* CFG_SDRAM_SIZE */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

#define CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/

#ifdef CONFIG_BZIP2
#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
#else
#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * Flash organization
 */
#define CFG_FLASH_BASE		CFG_MONITOR_BASE
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/

#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
#define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/

#define	CFG_DIRECT_FLASH_TFTP

#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
#define MTDPARTS_DEFAULT	"mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
*/

#define CFG_JFFS2_SORT_FRAGMENTS
#endif /* CFG_CMD_JFFS2 */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * I2C configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE		0x7F
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control
 */
#ifndef CFG_PLPRCR
#define CFG_PLPRCR	PLPRCR_TEXPS
#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER		 0

/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently.  Normally, you write the option register
* first, and then enable the chip select by writing the
* base register.  For CS0, you must write the base register
* first, followed by the option register.
*/

/*
 * Init Memory Controller:
 *
 * BR0/OR0 (Flash)
 * BR1/OR1 (BCSR)
 */
/* the other CS:s are determined by looking at parameters in BCSRx */

#define BCSR_ADDR		((uint) 0xFF080000)

#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )

/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/* values according to the manual */

#define PCMCIA_MEM_ADDR		((uint)0xFF020000)
#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))

#define	BCSR0			((uint) (BCSR_ADDR + 0x00))
#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
#define	BCSR4			((uint) (BCSR_ADDR + 0x10))

/*
 * (F)ADS bitvalues by Helmut Buchsbaum
 *
 * See User's Manual for a proper
 * description of the following structures
 */

#define BCSR0_ERB       ((uint)0x80000000)
#define BCSR0_IP        ((uint)0x40000000)
#define BCSR0_BDIS      ((uint)0x10000000)
#define BCSR0_BPS_MASK  ((uint)0x0C000000)
#define BCSR0_ISB_MASK  ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN           ((uint)0x80000000)
#define BCSR1_DRAM_EN            ((uint)0x40000000)
#define BCSR1_ETHEN              ((uint)0x20000000)
#define BCSR1_IRDEN              ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN            ((uint)0x02000000)
#define BCSR1_RS232EN_1          ((uint)0x01000000)
#define BCSR1_PCCEN              ((uint)0x00800000)
#define BCSR1_PCCVCC0            ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
#define BCSR1_RS232EN_2          ((uint)0x00040000)
#define BCSR1_SDRAM_EN           ((uint)0x00020000)
#define BCSR1_PCCVCC1            ((uint)0x00010000)

#define BCSR1_PCCVCCON		 BCSR1_PCCVCC0

#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT     28
#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT      23
#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)

#define BCSR3_DBID_MASK          ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0            ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
#define BCSR3_BREVN1             ((ushort)0x0008)
#define BCSR3_BREVN2_MASK        ((ushort)0x0003)

#define BCSR4_ETHLOOP            ((uint)0x80000000)
#define BCSR4_TFPLDL             ((uint)0x40000000)
#define BCSR4_TPSQEL             ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
#define BCSR4_FETH_EN            ((uint)0x08000000)
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#define BCSR4_FETHFDE            ((uint)0x02000000)
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#define BCSR4_FETHRST            ((uint)0x00200000)

#ifdef CONFIG_MPC823
#define BCSR4_USB_EN             ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN            ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED          ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO               ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE            ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON           ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST          ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST            ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN           ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC850 */

/* BSCR5 exists on MPC86xADS and Duet ADS only */

#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)

#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)

#define BCSR5_MII2_EN		0x40
#define BCSR5_MII2_RST		0x20
#define BCSR5_T1_RST		0x10
#define BCSR5_ATM155_RST	0x08
#define BCSR5_ATM25_RST		0x04
#define BCSR5_MII1_EN		0x02
#define BCSR5_MII1_RST		0x01

/* We don't use the 8259.
*/
#define NR_8259_INTS	0

/* Machine type
*/
#define _MACH_8xx (_MACH_fads)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_MAC_PARTITION    1
#define CONFIG_DOS_PARTITION    1
#define CONFIG_ISO_PARTITION	1

#undef	CONFIG_ATAPI
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
#define CFG_ATA_IDE0_OFFSET	0x0000

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0000

#define CONFIG_DISK_SPINUP_TIME 1000000
Commit	Line	Data
2d39b71f	1	/*
180d3f74	2	* (C) Copyright 2000-2004
2d39b71f WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
2d39b71f WD	4	*
180d3f74 WD	5	* Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
	6	* and Dan Malek
	7	*
	8	* Modified by, Yuli Barcohen, Arabella Software Ltd., [email protected]
	9	*
	10	* This header file contains values common to all FADS family boards.
	11	*
2d39b71f WD	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	/****************************************************************************
180d3f74	32	* Flash Memory Map as used by U-Boot:
2d39b71f WD	33	*
	34	* Start Address Length
	35	* +-----------------------+ 0xFE00_0000 Start of Flash -----------------
180d3f74 WD	36	* \| \| 0xFE00_0100 Reset Vector
	37	* + + 0xFE0?_????
	38	* \| U-Boot code \|
	39	* \| \|
	40	* +-----------------------+ 0xFE04_0000 (sector border)
	41	* \| \|
	42	* \| \|
	43	* \| U-Boot environment \|
	44	* \| \| ^
	45	* \| \| \| U-Boot
	46	* +=======================+ 0xFE08_0000 (sector border) -----------------
	47	* \| Available \| \| Applications
2d39b71f WD	48	* \| ... \| v
	49	*
	50	*****************************************************************************/
180d3f74 WD	51
	52	#if 0
	53	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	54	#else
	55	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	56	#endif
	57
	58	#undef CONFIG_BOOTARGS
	59	#define CONFIG_BOOTCOMMAND \
	60	"dhcp;" \
	61	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	62	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	63	"bootm"
	64
	65	#undef CONFIG_WATCHDOG /* watchdog disabled */
1114257c	66	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
180d3f74 WD	67
	68	/*
	69	* New MPC86xADS and Duet provide two Ethernet connectivity options:
	70	* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
	71	* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
	72	* got FEC so FEC is the default.
	73	*/
	74	#ifndef CONFIG_ADS
	75	#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
	76	#define CONFIG_FEC_ENET /* Use FEC ethernet */
	77	#else /* Old ADS has not got FEC option */
	78	#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
	79	#undef CONFIG_FEC_ENET /* No FEC ethernet */
	80	#endif /* !CONFIG_ADS */
	81
	82	#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
	83	#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
	84	#endif
	85
	86	#ifdef CONFIG_FEC_ENET
	87	#define CFG_DISCOVER_PHY
	88	#endif
	89
	90	#ifndef CONFIG_COMMANDS
1114257c WD	91	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	92	\| CFG_CMD_DHCP \
	93	\| CFG_CMD_IMMAP \
99edcfb2	94	\| CFG_CMD_JFFS2 \
1114257c WD	95	\| CFG_CMD_MII \
	96	\| CFG_CMD_PCMCIA \
	97	\| CFG_CMD_PING \
180d3f74 WD	98	)
	99	#endif /* !CONFIG_COMMANDS */
	100
	101	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	102	#include <cmd_confdefs.h>
	103
	104	/*
	105	* Miscellaneous configurable options
	106	*/
	107	#undef CFG_LONGHELP /* undef to save memory */
	108	#define CFG_PROMPT "=>" /* Monitor Command Prompt */
	109	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	110	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	111	#else
	112	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	113	#endif
	114	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	115	#define CFG_MAXARGS 16 /* max number of command args */
	116	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	117
	118	#define CFG_LOAD_ADDR 0x00100000
	119
	120	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	121
	122	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	123
	124	/*
	125	* Low Level Configuration Settings
	126	* (address mappings, register initial values, etc.)
	127	* You should know what you are doing if you make changes here.
	128	*/
	129	/*-----------------------------------------------------------------------
	130	* Internal Memory Mapped Register
	131	*/
	132	#define CFG_IMMR 0xFF000000
	133
	134	/*-----------------------------------------------------------------------
	135	* Definitions for initial stack pointer and data area (in DPRAM)
	136	*/
	137	#define CFG_INIT_RAM_ADDR CFG_IMMR
	138	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	139	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	140	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	141	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	142
	143	/*-----------------------------------------------------------------------
	144	* Start addresses for the final memory configuration
	145	* (Set up by the startup code)
	146	* Please note that CFG_SDRAM_BASE _must_ start at 0
	147	*/
	148	#define CFG_SDRAM_BASE 0x00000000
1114257c	149	#if defined(CONFIG_MPC86xADS) \|\| defined(CONFIG_MPC885ADS) /* New ADS or Duet */
180d3f74 WD	150	#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
	151	#elif defined(CONFIG_FADS) /* Old/new FADS */
	152	#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
	153	#else /* Old ADS */
	154	#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
	155	#endif
	156
	157	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	158	#if (CFG_SDRAM_SIZE)
	159	#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
	160	#else
	161	#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
	162	#endif /* CFG_SDRAM_SIZE */
	163
	164	/*
	165	* For booting Linux, the board info and command line data
	166	* have to be in the first 8 MB of memory, since this is
	167	* the maximum mapped by the Linux kernel during initialization.
	168	*/
	169	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
99edcfb2 WD	170
	171	#define CFG_MONITOR_BASE TEXT_BASE
	172	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
	173
	174	#ifdef CONFIG_BZIP2
	175	#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
	176	#else
	177	#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
	178	#endif /* CONFIG_BZIP2 */
	179
180d3f74 WD	180	/*-----------------------------------------------------------------------
	181	* Flash organization
	182	*/
99edcfb2 WD	183	#define CFG_FLASH_BASE CFG_MONITOR_BASE
99edcfb2 WD	184	#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
180d3f74	185
99edcfb2 WD	186	#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
99edcfb2 WD	187	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
180d3f74 WD	188
	189	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	190	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	191
	192	#define CFG_ENV_IS_IN_FLASH 1
	193	#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
	194	#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
	195	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
	196
99edcfb2	197	#define CFG_DIRECT_FLASH_TFTP
1114257c	198
99edcfb2	199	#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
700a0c64 WD	200
	201	/*
	202	* JFFS2 partitions
	203	*
	204	*/
	205	/* No command line, one static partition, whole device */
	206	#undef CONFIG_JFFS2_CMDLINE
	207	#define CONFIG_JFFS2_DEV "nor0"
	208	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	209	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	210
	211	/* mtdparts command line support */
	212	/* Note: fake mtd_id used, no linux mtd map file */
	213	/*
	214	#define CONFIG_JFFS2_CMDLINE
	215	#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
	216	#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
	217	*/
	218
99edcfb2 WD	219	#define CFG_JFFS2_SORT_FRAGMENTS
99edcfb2 WD	220	#endif /* CFG_CMD_JFFS2 */
180d3f74 WD	221
	222	/*-----------------------------------------------------------------------
	223	* Cache Configuration
	224	*/
	225	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
	226	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	227	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	228	#endif
	229
	230	/*-----------------------------------------------------------------------
	231	* I2C configuration
	232	*/
	233	#if (CONFIG_COMMANDS & CFG_CMD_I2C)
	234	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	235	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
	236	#define CFG_I2C_SLAVE 0x7F
	237	#endif
	238
	239	/*-----------------------------------------------------------------------
	240	* SYPCR - System Protection Control 11-9
	241	* SYPCR can only be written once after reset!
	242	*-----------------------------------------------------------------------
	243	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	244	*/
	245	#if defined(CONFIG_WATCHDOG)
	246	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	247	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	248	#else
	249	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	250	#endif
	251
	252	/*-----------------------------------------------------------------------
	253	* SIUMCR - SIU Module Configuration 11-6
	254	*-----------------------------------------------------------------------
	255	* PCMCIA config., multi-function pin tri-state
	256	*/
	257	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	258
	259	/*-----------------------------------------------------------------------
	260	* TBSCR - Time Base Status and Control 11-26
	261	*-----------------------------------------------------------------------
	262	* Clear Reference Interrupt Status, Timebase freezing enabled
	263	*/
	264	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	265
	266	/*-----------------------------------------------------------------------
	267	* PISCR - Periodic Interrupt Status and Control 11-31
	268	*-----------------------------------------------------------------------
	269	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	270	*/
	271	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	272
	273	/*-----------------------------------------------------------------------
	274	* SCCR - System Clock and reset Control Register 15-27
	275	*-----------------------------------------------------------------------
	276	* Set clock output, timebase and RTC source and divider,
	277	* power management and some other internal clocks
	278	*/
	279	#define SCCR_MASK SCCR_EBDF11
	280	#define CFG_SCCR (SCCR_TBS\|SCCR_COM00\|SCCR_DFSYNC00\|SCCR_DFBRG00\|SCCR_DFNL000\|SCCR_DFNH000\|SCCR_DFLCD000\|SCCR_DFALCD00)
	281
1114257c WD	282	/*-----------------------------------------------------------------------
	283	* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
	284	*-----------------------------------------------------------------------
	285	* set the PLL, the low-power modes and the reset control
	286	*/
	287	#ifndef CFG_PLPRCR
	288	#define CFG_PLPRCR PLPRCR_TEXPS
	289	#endif
	290
	291	/*-----------------------------------------------------------------------
180d3f74 WD	292	*
	293	*-----------------------------------------------------------------------
	294	*
	295	*/
	296	#define CFG_DER 0
	297
	298	/* Because of the way the 860 starts up and assigns CS0 the
	299	* entire address space, we have to set the memory controller
	300	* differently. Normally, you write the option register
	301	* first, and then enable the chip select by writing the
	302	* base register. For CS0, you must write the base register
	303	* first, followed by the option register.
	304	*/
	305
	306	/*
	307	* Init Memory Controller:
	308	*
	309	* BR0/OR0 (Flash)
	310	* BR1/OR1 (BCSR)
	311	*/
	312	/* the other CS:s are determined by looking at parameters in BCSRx */
	313
	314	#define BCSR_ADDR ((uint) 0xFF080000)
	315
	316	#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
	317
	318	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
	319	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
	320
	321	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
	322	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) \| BR_V )
	323
	324	/* BCSRx - Board Control and Status Registers */
	325	#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
	326	#define CFG_BR1_PRELIM ((BCSR_ADDR) \| BR_V)
	327
	328	/*
	329	* Internal Definitions
	330	*
	331	* Boot Flags
	332	*/
	333	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	334	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	335
	336	/* values according to the manual */
	337
	338	#define PCMCIA_MEM_ADDR ((uint)0xFF020000)
	339	#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
	340
	341	#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
	342	#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
	343	#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
	344	#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
	345	#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
	346
	347	/*
	348	* (F)ADS bitvalues by Helmut Buchsbaum
	349	*
	350	* See User's Manual for a proper
	351	* description of the following structures
	352	*/
	353
	354	#define BCSR0_ERB ((uint)0x80000000)
	355	#define BCSR0_IP ((uint)0x40000000)
356	#define BCSR0_BDIS ((uint)0x10000000)
357	#define BCSR0_BPS_MASK ((uint)0x0C000000)
358	#define BCSR0_ISB_MASK ((uint)0x01800000)
359	#define BCSR0_DBGC_MASK ((uint)0x00600000)
360	#define BCSR0_DBPC_MASK ((uint)0x00180000)
361	#define BCSR0_EBDF_MASK ((uint)0x00060000)
362
363	#define BCSR1_FLASH_EN ((uint)0x80000000)
364	#define BCSR1_DRAM_EN ((uint)0x40000000)
365	#define BCSR1_ETHEN ((uint)0x20000000)
366	#define BCSR1_IRDEN ((uint)0x10000000)
367	#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
368	#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
369	#define BCSR1_BCSR_EN ((uint)0x02000000)
370	#define BCSR1_RS232EN_1 ((uint)0x01000000)
371	#define BCSR1_PCCEN ((uint)0x00800000)
372	#define BCSR1_PCCVCC0 ((uint)0x00400000)
373	#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
374	#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
375	#define BCSR1_RS232EN_2 ((uint)0x00040000)
376	#define BCSR1_SDRAM_EN ((uint)0x00020000)
377	#define BCSR1_PCCVCC1 ((uint)0x00010000)
378
379	#define BCSR1_PCCVCCON BCSR1_PCCVCC0
380
381	#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
99edcfb2	382	#define BCSR2_FLASH_PD_SHIFT 28
180d3f74 WD	383	#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
	384	#define BCSR2_DRAM_PD_SHIFT 23
	385	#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
	386	#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
	387
	388	#define BCSR3_DBID_MASK ((ushort)0x3800)
	389	#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
	390	#define BCSR3_BREVNR0 ((ushort)0x0080)
	391	#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
	392	#define BCSR3_BREVN1 ((ushort)0x0008)
	393	#define BCSR3_BREVN2_MASK ((ushort)0x0003)
	394
	395	#define BCSR4_ETHLOOP ((uint)0x80000000)
	396	#define BCSR4_TFPLDL ((uint)0x40000000)
	397	#define BCSR4_TPSQEL ((uint)0x20000000)
	398	#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
	399	#define BCSR4_FETH_EN ((uint)0x08000000)
	400	#define BCSR4_FETHCFG0 ((uint)0x04000000)
	401	#define BCSR4_FETHFDE ((uint)0x02000000)
	402	#define BCSR4_FETHCFG1 ((uint)0x00400000)
	403	#define BCSR4_FETHRST ((uint)0x00200000)
	404
	405	#ifdef CONFIG_MPC823
	406	#define BCSR4_USB_EN ((uint)0x08000000)
	407	#endif /* CONFIG_MPC823 */
	408	#ifdef CONFIG_MPC860SAR
	409	#define BCSR4_UTOPIA_EN ((uint)0x08000000)
	410	#endif /* CONFIG_MPC860SAR */
	411	#ifdef CONFIG_MPC860T
	412	#define BCSR4_FETH_EN ((uint)0x08000000)
	413	#endif /* CONFIG_MPC860T */
	414	#ifdef CONFIG_MPC823
	415	#define BCSR4_USB_SPEED ((uint)0x04000000)
	416	#endif /* CONFIG_MPC823 */
	417	#ifdef CONFIG_MPC860T
	418	#define BCSR4_FETHCFG0 ((uint)0x04000000)
	419	#endif /* CONFIG_MPC860T */
	420	#ifdef CONFIG_MPC823
	421	#define BCSR4_VCCO ((uint)0x02000000)
	422	#endif /* CONFIG_MPC823 */
	423	#ifdef CONFIG_MPC860T
	424	#define BCSR4_FETHFDE ((uint)0x02000000)
	425	#endif /* CONFIG_MPC860T */
	426	#ifdef CONFIG_MPC823
	427	#define BCSR4_VIDEO_ON ((uint)0x00800000)
	428	#endif /* CONFIG_MPC823 */
	429	#ifdef CONFIG_MPC823
	430	#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
	431	#endif /* CONFIG_MPC823 */
	432	#ifdef CONFIG_MPC860T
	433	#define BCSR4_FETHCFG1 ((uint)0x00400000)
	434	#endif /* CONFIG_MPC860T */
	435	#ifdef CONFIG_MPC823
	436	#define BCSR4_VIDEO_RST ((uint)0x00200000)
	437	#endif /* CONFIG_MPC823 */
	438	#ifdef CONFIG_MPC860T
	439	#define BCSR4_FETHRST ((uint)0x00200000)
	440	#endif /* CONFIG_MPC860T */
	441	#ifdef CONFIG_MPC823
	442	#define BCSR4_MODEM_EN ((uint)0x00100000)
	443	#endif /* CONFIG_MPC823 */
	444	#ifdef CONFIG_MPC823
	445	#define BCSR4_DATA_VOICE ((uint)0x00080000)
	446	#endif /* CONFIG_MPC823 */
447	#ifdef CONFIG_MPC850
448	#define BCSR4_DATA_VOICE ((uint)0x00080000)
449	#endif /* CONFIG_MPC850 */
450
1114257c WD	451	/* BSCR5 exists on MPC86xADS and Duet ADS only */
	452
	453	#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
	454
	455	#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
	456
	457	#define BCSR5_MII2_EN 0x40
	458	#define BCSR5_MII2_RST 0x20
	459	#define BCSR5_T1_RST 0x10
	460	#define BCSR5_ATM155_RST 0x08
	461	#define BCSR5_ATM25_RST 0x04
	462	#define BCSR5_MII1_EN 0x02
	463	#define BCSR5_MII1_RST 0x01
	464
180d3f74 WD	465	/* We don't use the 8259.
	466	*/
	467	#define NR_8259_INTS 0
	468
	469	/* Machine type
	470	*/
	471	#define _MACH_8xx (_MACH_fads)
	472
	473	/*-----------------------------------------------------------------------
	474	* PCMCIA stuff
	475	*-----------------------------------------------------------------------
	476	*/
180d3f74 WD	477	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	478	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	479	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	480	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	481	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	482	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	483	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	484	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	485
	486	/*-----------------------------------------------------------------------
	487	* IDE/ATA stuff
	488	*-----------------------------------------------------------------------
	489	*/
	490	#define CONFIG_MAC_PARTITION 1
	491	#define CONFIG_DOS_PARTITION 1
	492	#define CONFIG_ISO_PARTITION 1
	493
	494	#undef CONFIG_ATAPI
	495	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	496	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	497	#undef CONFIG_IDE_LED /* LED for ide not supported */
	498	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	499
	500	#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
	501	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
	502
	503	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	504	#define CFG_ATA_IDE0_OFFSET 0x0000
	505
	506	/* Offset for data I/O */
	507	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	508	/* Offset for normal register accesses */
	509	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	510	/* Offset for alternate registers */
	511	#define CFG_ATA_ALT_OFFSET 0x0000
	512
	513	#define CONFIG_DISK_SPINUP_TIME 1000000
	514