[J-u-boot.git] / include / configs / t4qds.h

/*
 * Copyright 2011-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Corenet DS style board configuration file
 */
#ifndef __T4QDS_H
#define __T4QDS_H

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
#define CONFIG_MP			/* support multiple processors */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1			/* PCIE controller 1 */
#define CONFIG_PCIE2			/* PCIE controller 2 */
#define CONFIG_PCIE3			/* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */
#define CONFIG_SRIO2			/* SRIO port 2 */

#define CONFIG_ENV_OVERWRITE

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB			/* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_SYS_ALT_MEMTEST

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define CONFIG_SYS_L3_SIZE		(512 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
#endif
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)

#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	2
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE

#define CONFIG_DDR_SPD

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE	0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
#define CONFIG_MISC_INIT_R

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100

/*
 * RapidIO
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */

#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

#define CONFIG_LBA48
#endif

#ifdef CONFIG_FMAN_ENET
#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"FM1@DTSEC1"
#endif

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_HVBOOT				\
 "setenv bootargs config-addr=0x60000000; "	\
 "bootm 0x01000000 - 0x00f00000"

#endif	/* __CONFIG_H */
Commit	Line	Data
ee52b188 YS	1	/*
	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ee52b188 YS	5	*/
	6
	7	/*
	8	* Corenet DS style board configuration file
	9	*/
1cb19fbb YS	10	#ifndef __T4QDS_H
1cb19fbb YS	11	#define __T4QDS_H
69fdf900	12
ee52b188	13	/* High Level Configuration Options */
ee52b188	14	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
ee52b188 YS	15	#define CONFIG_MP /* support multiple processors */
ee52b188 YS	16
ee52b188 YS	17	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	18	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	19	#endif
	20
	21	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51370d56	22	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
b38eaec5 RD	23	#define CONFIG_PCIE1 /* PCIE controller 1 */
	24	#define CONFIG_PCIE2 /* PCIE controller 2 */
	25	#define CONFIG_PCIE3 /* PCIE controller 3 */
ee52b188 YS	26	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	27	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	28
	29	#define CONFIG_SYS_SRIO
	30	#define CONFIG_SRIO1 /* SRIO port 1 */
	31	#define CONFIG_SRIO2 /* SRIO port 2 */
	32
ee52b188 YS	33	#define CONFIG_ENV_OVERWRITE
ee52b188 YS	34
ee52b188 YS	35	/*
	36	* These can be toggled for performance analysis, otherwise use default.
	37	*/
	38	#define CONFIG_SYS_CACHE_STASHING
	39	#define CONFIG_BTB /* toggle branch predition */
ee52b188 YS	40	#ifdef CONFIG_DDR_ECC
	41	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	42	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	43	#endif
	44
	45	#define CONFIG_ENABLE_36BIT_PHYS
	46
ee52b188 YS	47	#define CONFIG_ADDR_MAP
ee52b188 YS	48	#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
ee52b188	49
ee52b188 YS	50	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	51	#define CONFIG_SYS_MEMTEST_END 0x00400000
	52	#define CONFIG_SYS_ALT_MEMTEST
ee52b188 YS	53
	54	/*
	55	* Config the L3 Cache as L3 SRAM
	56	*/
b6036993 SX	57	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	58	#define CONFIG_SYS_L3_SIZE (512 << 10)
	59	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
	60	#ifdef CONFIG_RAMBOOT_PBL
	61	#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
	62	#endif
	63	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	64	#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
	65	#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
	66	#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
ee52b188	67
ee52b188 YS	68	#define CONFIG_SYS_DCSRBAR 0xf0000000
ee52b188 YS	69	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
ee52b188	70
ee52b188 YS	71	/*
	72	* DDR Setup
	73	*/
	74	#define CONFIG_VERY_BIG_RAM
	75	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	76	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	77
ee52b188 YS	78	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	79	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	80	#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
	81
	82	#define CONFIG_DDR_SPD
ee52b188	83
ee52b188 YS	84	/*
	85	* IFC Definitions
	86	*/
	87	#define CONFIG_SYS_FLASH_BASE 0xe0000000
ee52b188	88	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
ee52b188	89
b6036993 SX	90	#ifdef CONFIG_SPL_BUILD
	91	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	92	#else
	93	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	94	#endif
ee52b188	95
ee52b188 YS	96	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
	97	#define CONFIG_MISC_INIT_R
	98
	99	#define CONFIG_HWCONFIG
	100
	101	/* define to use L1 as initial stack */
	102	#define CONFIG_L1_INIT_RAM
	103	#define CONFIG_SYS_INIT_RAM_LOCK
	104	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
ee52b188	105	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	106	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
ee52b188 YS	107	/* The assembler doesn't like typecast */
	108	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	109	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	110	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
ee52b188 YS	111	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	112
	113	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	114	GENERATED_GBL_DATA_SIZE)
	115	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	116
9307cbab	117	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
ee52b188 YS	118	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	119
	120	/* Serial Port - controlled on board with jumper J8
	121	* open - index 2
	122	* shorted - index 1
	123	*/
ee52b188 YS	124	#define CONFIG_SYS_NS16550_SERIAL
	125	#define CONFIG_SYS_NS16550_REG_SIZE 1
	126	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	127
	128	#define CONFIG_SYS_BAUDRATE_TABLE \
	129	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	130
	131	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	132	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	133	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	134	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	135
ee52b188	136	/* I2C */
00f792e0 HS	137	#define CONFIG_SYS_I2C
00f792e0 HS	138	#define CONFIG_SYS_I2C_FSL
00f792e0 HS	139	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
00f792e0 HS	140	#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
00f792e0 HS	141	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	142	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
	143
ee52b188 YS	144	/*
	145	* RapidIO
	146	*/
	147	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
ee52b188	148	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
ee52b188 YS	149	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
	150
	151	#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
ee52b188	152	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
ee52b188 YS	153	#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
ee52b188 YS	154
ee52b188 YS	155	/*
	156	* General PCI
	157	* Memory space is mapped 1-1, but I/O space must start from 0.
	158	*/
	159
	160	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	161	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
ee52b188 YS	162	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
ee52b188 YS	163	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
ee52b188 YS	164	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	165	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
	166	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
ee52b188	167	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
ee52b188 YS	168	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	169
	170	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	171	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
ee52b188 YS	172	#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
ee52b188 YS	173	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
ee52b188 YS	174	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	175	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
	176	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
ee52b188	177	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
ee52b188 YS	178	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	179
	180	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	181	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
ee52b188 YS	182	#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
ee52b188 YS	183	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
ee52b188 YS	184	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
	185	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
	186	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
ee52b188	187	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
ee52b188 YS	188	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
	189
	190	/* controller 4, Base address 203000 */
	191	#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
	192	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
	193	#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
	194	#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
	195	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
	196	#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
	197
ee52b188	198	#ifdef CONFIG_PCI
842033e6	199	#define CONFIG_PCI_INDIRECT_BRIDGE
ee52b188 YS	200
ee52b188 YS	201	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
ee52b188 YS	202	#endif /* CONFIG_PCI */
	203
	204	/* SATA */
	205	#ifdef CONFIG_FSL_SATA_V2
ee52b188 YS	206	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	207	#define CONFIG_SATA1
	208	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	209	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	210	#define CONFIG_SATA2
	211	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	212	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	213
	214	#define CONFIG_LBA48
ee52b188 YS	215	#endif
	216
	217	#ifdef CONFIG_FMAN_ENET
	218	#define CONFIG_MII /* MII PHY management */
	219	#define CONFIG_ETHPRIME "FM1@DTSEC1"
ee52b188 YS	220	#endif
	221
	222	/*
	223	* Environment
	224	*/
	225	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	226	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	227
	228	/*
	229	* Command line configuration.
	230	*/
ee52b188	231
ee52b188 YS	232	/*
	233	* Miscellaneous configurable options
	234	*/
ee52b188	235	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
ee52b188 YS	236
	237	/*
	238	* For booting Linux, the board info and command line data
	239	* have to be in the first 64 MB of memory, since this is
	240	* the maximum mapped by the Linux kernel during initialization.
	241	*/
	242	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	243	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	244
	245	#ifdef CONFIG_CMD_KGDB
	246	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
ee52b188 YS	247	#endif
	248
	249	/*
	250	* Environment Configuration
	251	*/
	252	#define CONFIG_ROOTPATH "/opt/nfsroot"
	253	#define CONFIG_BOOTFILE "uImage"
	254	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
	255
	256	/* default location for tftp and bootm */
	257	#define CONFIG_LOADADDR 1000000
	258
ee52b188 YS	259	#define CONFIG_HVBOOT \
	260	"setenv bootargs config-addr=0x60000000; " \
	261	"bootm 0x01000000 - 0x00f00000"
	262
ee52b188	263	#endif /* __CONFIG_H */