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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
730d2544 CF |
2 | /* |
3 | * Copyright (C) 2016 samtec automotive software & electronics gmbh | |
4 | * | |
5 | * Configuration settings for the Samtec VIN|ING 2000 board. | |
730d2544 CF |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #include "mx6_common.h" | |
12 | ||
13 | #ifdef CONFIG_SPL | |
14 | #include "imx6_spl.h" | |
15 | #endif | |
16 | ||
17 | /* Size of malloc() pool */ | |
18 | #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) | |
19 | ||
730d2544 CF |
20 | #define BOOT_TARGET_DEVICES(func) \ |
21 | func(MMC, mmc, 0) \ | |
22 | func(MMC, mmc, 1) \ | |
23 | func(USB, usb, 0) \ | |
24 | func(PXE, pxe, na) \ | |
25 | func(DHCP, dhcp, na) | |
26 | #include <config_distro_bootcmd.h> | |
27 | ||
28 | /* Miscellaneous configurable options */ | |
730d2544 | 29 | |
730d2544 | 30 | /* Physical Memory Map */ |
730d2544 CF |
31 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
32 | ||
33 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
34 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
35 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
36 | ||
37 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
38 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
39 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
40 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
41 | ||
42 | /* MMC Configuration */ | |
43 | #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR | |
44 | ||
45 | /* I2C Configs */ | |
46 | #define CONFIG_SYS_I2C | |
47 | #define CONFIG_SYS_I2C_MXC | |
48 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
49 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
50 | #define CONFIG_SYS_I2C_SPEED 100000 | |
51 | ||
52 | /* PMIC */ | |
53 | #define CONFIG_POWER | |
54 | #define CONFIG_POWER_I2C | |
55 | #define CONFIG_POWER_PFUZE100 | |
56 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
57 | ||
58 | /* Network */ | |
730d2544 CF |
59 | #define IMX_FEC_BASE ENET_BASE_ADDR |
60 | #define CONFIG_FEC_MXC_PHYADDR 0x0 | |
61 | ||
62 | #define CONFIG_FEC_XCV_TYPE RMII | |
63 | #define CONFIG_ETHPRIME "FEC" | |
64 | ||
730d2544 | 65 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
730d2544 CF |
66 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
67 | #define CONFIG_MXC_USB_FLAGS 0 | |
68 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
730d2544 | 69 | |
730d2544 CF |
70 | #ifdef CONFIG_CMD_PCI |
71 | #define CONFIG_PCI_SCAN_SHOW | |
72 | #define CONFIG_PCIE_IMX | |
73 | #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) | |
74 | #endif | |
75 | ||
76 | #define CONFIG_IMX_THERMAL | |
77 | ||
730d2544 | 78 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 |
730d2544 | 79 | |
730d2544 | 80 | #ifdef CONFIG_ENV_IS_IN_MMC |
730d2544 CF |
81 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ |
82 | /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ | |
83 | #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ | |
84 | #endif | |
85 | ||
7d84f446 MV |
86 | #ifdef CONFIG_SPL_BUILD |
87 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
88 | #endif | |
89 | ||
730d2544 | 90 | #endif /* __CONFIG_H */ |