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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c0dcece7 HS |
2 | /* |
3 | * siemens rut | |
4 | * (C) Copyright 2013 Siemens Schweiz AG | |
5 | * (C) Heiko Schocher, DENX Software Engineering, [email protected]. | |
6 | * | |
7 | * Based on: | |
8 | * U-Boot file:/include/configs/am335x_evm.h | |
9 | * | |
10 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
c0dcece7 HS |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_RUT_H | |
14 | #define __CONFIG_RUT_H | |
15 | ||
c0dcece7 HS |
16 | #define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT |
17 | ||
18 | #include "siemens-am33x-common.h" | |
19 | ||
c0dcece7 HS |
20 | #define RUT_IOCTRL_VAL 0x18b |
21 | #define DDR_PLL_FREQ 303 | |
22 | ||
23 | /* Physical Memory Map */ | |
24 | #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ | |
25 | ||
26 | /* I2C Configuration */ | |
27 | #define CONFIG_SYS_I2C_SPEED 100000 | |
28 | ||
29 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
30 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
31 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
32 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
33 | ||
c0dcece7 HS |
34 | #define CONFIG_FACTORYSET |
35 | ||
c0dcece7 HS |
36 | /* Watchdog */ |
37 | #define WATCHDOG_TRIGGER_GPIO 14 | |
38 | ||
39 | #ifndef CONFIG_SPL_BUILD | |
40 | ||
61159b76 | 41 | /* Use common default */ |
61159b76 | 42 | |
c0dcece7 HS |
43 | /* Default env settings */ |
44 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
45 | "hostname=rut\0" \ | |
6b3943f1 | 46 | "ubi_off=2048\0"\ |
56eb3da4 SE |
47 | "nand_img_size=0x500000\0" \ |
48 | "splashpos=m,m\0" \ | |
c0dcece7 | 49 | "optargs=fixrtc --no-log consoleblank=0 \0" \ |
61159b76 HS |
50 | CONFIG_ENV_SETTINGS_V1 \ |
51 | CONFIG_ENV_SETTINGS_NAND_V1 \ | |
c0dcece7 HS |
52 | "mmc_dev=0\0" \ |
53 | "mmc_root=/dev/mmcblk0p2 rw\0" \ | |
54 | "mmc_root_fs_type=ext4 rootwait\0" \ | |
55 | "mmc_load_uimage=" \ | |
56 | "mmc rescan; " \ | |
57 | "setenv bootfile uImage;" \ | |
58 | "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ | |
59 | "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ | |
60 | "importbootenv=echo Importing environment from mmc ...; " \ | |
61 | "env import -t $loadaddr $filesize\0" \ | |
62 | "mmc_args=run bootargs_defaults;" \ | |
63 | "mtdparts default;" \ | |
64 | "setenv bootargs ${bootargs} " \ | |
65 | "root=${mmc_root} ${mtdparts}" \ | |
66 | "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ | |
67 | "eth=${ethaddr} " \ | |
68 | "\0" \ | |
69 | "mmc_boot=run mmc_args; " \ | |
70 | "run mmc_load_uimage; " \ | |
71 | "bootm ${kloadaddr}\0" \ | |
72 | "" | |
73 | ||
74 | #ifndef CONFIG_RESTORE_FLASH | |
75 | /* set to negative value for no autoboot */ | |
c0dcece7 HS |
76 | |
77 | #define CONFIG_BOOTCOMMAND \ | |
78 | "if mmc rescan; then " \ | |
79 | "echo SD/MMC found on device ${mmc_dev};" \ | |
80 | "if run loadbootenv; then " \ | |
81 | "echo Loaded environment from ${bootenv};" \ | |
82 | "run importbootenv;" \ | |
83 | "fi;" \ | |
84 | "if test -n $uenvcmd; then " \ | |
85 | "echo Running uenvcmd ...;" \ | |
86 | "run uenvcmd;" \ | |
87 | "fi;" \ | |
88 | "if run mmc_load_uimage; then " \ | |
89 | "run mmc_args;" \ | |
90 | "bootm ${kloadaddr};" \ | |
91 | "fi;" \ | |
92 | "fi;" \ | |
93 | "run nand_boot;" \ | |
56eb3da4 | 94 | "reset;" |
c0dcece7 HS |
95 | |
96 | #else | |
c0dcece7 HS |
97 | |
98 | #define CONFIG_BOOTCOMMAND \ | |
99 | "setenv autoload no; " \ | |
100 | "dhcp; " \ | |
101 | "if tftp 80000000 debrick.scr; then " \ | |
102 | "source 80000000; " \ | |
103 | "fi" | |
104 | #endif | |
105 | ||
106 | #endif /* CONFIG_SPL_BUILD */ | |
107 | ||
c0dcece7 HS |
108 | #if defined(CONFIG_VIDEO) |
109 | #define CONFIG_VIDEO_DA8XX | |
c0dcece7 HS |
110 | #define CONFIG_SPLASH_SCREEN |
111 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
112 | #define CONFIG_VIDEO_LOGO | |
113 | #define CONFIG_VIDEO_BMP_RLE8 | |
114 | #define CONFIG_VIDEO_BMP_LOGO | |
c0dcece7 HS |
115 | #define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE |
116 | ||
c0dcece7 | 117 | #define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ |
c0dcece7 | 118 | #define CONFIG_FORMIKE |
56eb3da4 | 119 | #define DISPL_PLL_SPREAD_SPECTRUM |
c0dcece7 HS |
120 | #endif |
121 | ||
122 | #endif /* ! __CONFIG_RUT_H */ |