[J-u-boot.git] / include / configs / MPC8349ITX.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006.
 */

/*
 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file

 Memory map:

 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
 0xF001_0000-0xF001_FFFF Local bus expansion slot
 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)

 I2C address list:
						Align.	Board
 Bus	Addr	Part No.	Description	Length	Location
 ----------------------------------------------------------------
 I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64

 I2C1	0x20	PCF8574		I2C Expander	0	U8
 I2C1	0x21	PCF8574		I2C Expander	0	U10
 I2C1	0x38	PCF8574A	I2C Expander	0	U8
 I2C1	0x39	PCF8574A	I2C Expander	0	U10
 I2C1	0x51	(DDR)		DDR EEPROM	1	U1
 I2C1	0x68	DS1339		RTC		1	U68

 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MISC_INIT_F

/*
 * On-board devices
 */

#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
#endif

#include <linux/stringify.h>
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C

/*
 * Device configurations
 */

/* I2C */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */

#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */

/* Don't probe these addresses: */
#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
/* Bit definitions for the 8574[A] I2C expander */
				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
#define I2C_8574_REVISION	0x03
#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/

#endif

/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
#define CONFIG_SYS_ATA_REG_OFFSET	0
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
#define CONFIG_SYS_ATA_STRIDE		2

/* If a CF card is not inserted, time out quickly */
#define ATA_RESET_TIME	1

#endif

/*
 * SATA
 */
#ifdef CONFIG_SATA_SIL3114

#define CONFIG_SYS_SATA_MAX_DEVICE      4
#define CONFIG_LBA48

#endif

#ifdef CONFIG_SYS_USB_HOST
/*
 * Support USB
 */
#define CONFIG_USB_EHCI_FSL

/* Current USB implementation supports the only USB controller,
 * so we have to choose between the MPH or the DR ones */
#if 1
#define CONFIG_HAS_FSL_MPH_USB
#else
#define CONFIG_HAS_FSL_DR_USB
#endif

#endif

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_83XX_DDR_USES_CS0

#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)

#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)

#ifdef CONFIG_SYS_I2C
#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
#endif

/* No SPD? Then manually set up DDR parameters */
#ifndef CONFIG_SPD_EEPROM
    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)

    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
#endif

/*
 *Flash on the Local Bus
 */

#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* 127 64KB sectors + 8 8KB sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	\
		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */

/* Vitesse 7385 */

#ifdef CONFIG_VSC7385_ENET

#define CONFIG_TSEC2

/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFEFFE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192

#endif

/*
 * BRx, ORx, LBLAWBARx, and LBLAWARx
 */


/* Vitesse 7385 */

#define CONFIG_SYS_VSC7385_BASE	0xF8000000

#define CONFIG_SYS_LED_BASE	0xF9000000


/* Compact Flash */

#ifdef CONFIG_COMPACT_FLASH

#define CONFIG_SYS_CF_BASE	0xF0000000


#endif

/*
 * U-Boot memory configuration
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef	CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONSOLE			ttyS0

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * PCI
 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_MPC83XX_PCI2

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */

#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_PCI2_MEM_BASE	\
			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	\
			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		\
			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
#endif

#ifndef CONFIG_PCI_PNP
    #define PCI_ENET0_IOADDR	0x00000000
    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif

/* TSEC */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_TSEC1

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME  "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME  "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET	0x25000

#define TSEC2_PHY_ADDR		4
#define TSEC2_PHYIDX		0
#define TSEC2_FLAGS		TSEC_GIGABIT
#endif

#define CONFIG_ETHPRIME		"Freescale TSEC"

#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_LOADS_ECHO	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* Watchdog */
#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * System performance
 */
#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */

/*
 * System IO Config
 */
/* Needed for gigabit to work on TSEC 1 */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
				/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		"eth0"

/* Default path and filenames */
#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"

#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
#endif


#define CONFIG_EXTRA_ENV_SETTINGS \
	"console=" __stringify(CONSOLE) "\0"			\
	"netdev=" CONFIG_NETDEV "\0"					\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
	" console=$console,$baudrate $othbootargs; "			\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw"				\
	" console=$console,$baudrate $othbootargs; "			\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2ad6b513	2	/*
4c2e3da8	3	* Copyright (C) Freescale Semiconductor, Inc. 2006.
2ad6b513 TT	4	*/
	5
	6	/*
7a78f148	7	MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
2ad6b513 TT	8
	9	Memory map:
	10
	11	0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
	12	0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
	13	0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
	14	0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
	15	0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
	16	0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
7a78f148	17	0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
2ad6b513	18	0xF001_0000-0xF001_FFFF Local bus expansion slot
7a78f148 TT	19	0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
	20	0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
	21	0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
2ad6b513 TT	22
2ad6b513 TT	23	I2C address list:
dd520bf3 WD	24	Align. Board
dd520bf3 WD	25	Bus Addr Part No. Description Length Location
2ad6b513	26	----------------------------------------------------------------
dd520bf3	27	I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
2ad6b513	28
dd520bf3 WD	29	I2C1 0x20 PCF8574 I2C Expander 0 U8
	30	I2C1 0x21 PCF8574 I2C Expander 0 U10
	31	I2C1 0x38 PCF8574A I2C Expander 0 U8
	32	I2C1 0x39 PCF8574A I2C Expander 0 U10
	33	I2C1 0x51 (DDR) DDR EEPROM 1 U1
	34	I2C1 0x68 DS1339 RTC 1 U68
2ad6b513 TT	35
	36	Note that a given board has either a pair of 8574s or a pair of 8574As.
	37	*/
	38
	39	#ifndef __CONFIG_H
	40	#define __CONFIG_H
	41
89c7784e	42	#define CONFIG_MISC_INIT_F
7a78f148	43
89c7784e TT	44	/*
	45	* On-board devices
	46	*/
2ad6b513	47
4cb06d3e	48	#ifdef CONFIG_TARGET_MPC8349ITX
396abba2 JH	49	/* The CF card interface on the back of the board */
396abba2 JH	50	#define CONFIG_COMPACT_FLASH
89c7784e	51	#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
c31e1326	52	#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
7a78f148	53	#endif
2ad6b513	54
1af3c7f4	55	#include <linux/stringify.h>
7a78f148	56	#define CONFIG_RTC_DS1337
00f792e0	57	#define CONFIG_SYS_I2C
2ad6b513	58
7a78f148 TT	59	/*
	60	* Device configurations
	61	*/
	62
	63	/* I2C */
00f792e0 HS	64	#ifdef CONFIG_SYS_I2C
	65	#define CONFIG_SYS_I2C_FSL
	66	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	67	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	68	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	69	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	70	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	71	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
2ad6b513	72
6d0f6bcf	73	#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
b7be63ab	74	#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
6d0f6bcf JCPV	75
	76	#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
	77	#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
	78	#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
	79	#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
	80	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
396abba2 JH	81	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
396abba2 JH	82	#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
2ad6b513	83
2ad6b513	84	/* Don't probe these addresses: */
396abba2	85	#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
6d0f6bcf JCPV	86	{1, CONFIG_SYS_I2C_8574_ADDR2}, \
6d0f6bcf JCPV	87	{1, CONFIG_SYS_I2C_8574A_ADDR1}, \
396abba2	88	{1, CONFIG_SYS_I2C_8574A_ADDR2} }
2ad6b513	89	/* Bit definitions for the 8574[A] I2C expander */
396abba2 JH	90	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
396abba2 JH	91	#define I2C_8574_REVISION 0x03
2ad6b513 TT	92	#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
	93	#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
	94	#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
	95	#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
	96
2ad6b513 TT	97	#endif
2ad6b513 TT	98
7a78f148 TT	99	/* Compact Flash */
7a78f148 TT	100	#ifdef CONFIG_COMPACT_FLASH
2ad6b513	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	103	#define CONFIG_SYS_IDE_MAXDEVICE 1
2ad6b513	104
6d0f6bcf JCPV	105	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	106	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
	107	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
	108	#define CONFIG_SYS_ATA_REG_OFFSET 0
	109	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
	110	#define CONFIG_SYS_ATA_STRIDE 2
2ad6b513	111
396abba2 JH	112	/* If a CF card is not inserted, time out quickly */
396abba2 JH	113	#define ATA_RESET_TIME 1
2ad6b513	114
c9e34fe2 VG	115	#endif
	116
	117	/*
	118	* SATA
	119	*/
	120	#ifdef CONFIG_SATA_SIL3114
	121
	122	#define CONFIG_SYS_SATA_MAX_DEVICE 4
c9e34fe2	123	#define CONFIG_LBA48
2ad6b513	124
7a78f148	125	#endif
2ad6b513	126
c31e1326 VG	127	#ifdef CONFIG_SYS_USB_HOST
	128	/*
	129	* Support USB
	130	*/
c31e1326 VG	131	#define CONFIG_USB_EHCI_FSL
	132
	133	/* Current USB implementation supports the only USB controller,
	134	* so we have to choose between the MPH or the DR ones */
	135	#if 1
	136	#define CONFIG_HAS_FSL_MPH_USB
	137	#else
	138	#define CONFIG_HAS_FSL_DR_USB
	139	#endif
	140
	141	#endif
	142
2ad6b513	143	/*
7a78f148	144	* DDR Setup
2ad6b513	145	*/
8a81bfd2	146	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf	147	#define CONFIG_SYS_83XX_DDR_USES_CS0
6d0f6bcf	148
396abba2 JH	149	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
396abba2 JH	150	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
f64702b7	151
b7be63ab VG	152	#define CONFIG_VERY_BIG_RAM
	153	#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
	154
00f792e0	155	#ifdef CONFIG_SYS_I2C
7a78f148 TT	156	#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
	157	#endif
	158
396abba2 JH	159	/* No SPD? Then manually set up DDR parameters */
	160	#ifndef CONFIG_SPD_EEPROM
	161	#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
2e651b24	162	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
396abba2 JH	163	\| CSCONFIG_ROW_BIT_13 \
396abba2 JH	164	\| CSCONFIG_COL_BIT_10)
2ad6b513	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_DDR_TIMING_1 0x26242321
6d0f6bcf JCPV	167	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
2ad6b513 TT	168	#endif
2ad6b513 TT	169
7a78f148 TT	170	/*
	171	*Flash on the Local Bus
	172	*/
	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_EMPTY_INFO
396abba2 JH	176	/* 127 64KB sectors + 8 8KB sectors per device */
396abba2 JH	177	#define CONFIG_SYS_MAX_FLASH_SECT 135
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	179	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	180	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
7a78f148 TT	181
	182	/* The ITX has two flash chips, but the ITX-GP has only one. To support both
	183	boards, we say we have two, but don't display a message if we find only one. */
6d0f6bcf	184	#define CONFIG_SYS_FLASH_QUIET_TEST
396abba2 JH	185	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	186	#define CONFIG_SYS_FLASH_BANKS_LIST \
	187	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
	188	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
7a78f148	189
89c7784e TT	190	/* Vitesse 7385 */
	191
	192	#ifdef CONFIG_VSC7385_ENET
	193
	194	#define CONFIG_TSEC2
	195
	196	/* The flash address and size of the VSC7385 firmware image */
	197	#define CONFIG_VSC7385_IMAGE 0xFEFFE000
	198	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	199
	200	#endif
	201
7a78f148 TT	202	/*
	203	* BRx, ORx, LBLAWBARx, and LBLAWARx
	204	*/
	205
a8f97539	206
7a78f148	207	/* Vitesse 7385 */
2ad6b513	208
6d0f6bcf	209	#define CONFIG_SYS_VSC7385_BASE 0xF8000000
2ad6b513	210
396abba2	211	#define CONFIG_SYS_LED_BASE 0xF9000000
a8f97539	212
7a78f148 TT	213
7a78f148 TT	214	/* Compact Flash */
2ad6b513 TT	215
	216	#ifdef CONFIG_COMPACT_FLASH
	217
396abba2	218	#define CONFIG_SYS_CF_BASE 0xF0000000
2ad6b513	219
2ad6b513	220
2ad6b513 TT	221	#endif
2ad6b513 TT	222
7a78f148 TT	223	/*
	224	* U-Boot memory configuration
	225	*/
14d0a02a	226	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
2ad6b513	227
6d0f6bcf JCPV	228	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	229	#define CONFIG_SYS_RAMBOOT
2ad6b513	230	#else
6d0f6bcf	231	#undef CONFIG_SYS_RAMBOOT
2ad6b513 TT	232	#endif
2ad6b513 TT	233
6d0f6bcf	234	#define CONFIG_SYS_INIT_RAM_LOCK
396abba2 JH	235	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
396abba2 JH	236	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
2ad6b513	237
396abba2 JH	238	#define CONFIG_SYS_GBL_DATA_OFFSET \
396abba2 JH	239	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	240	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
2ad6b513	241
6d0f6bcf	242	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	243	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
c8a90646	244	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
2ad6b513	245
2ad6b513 TT	246	/*
	247	* Serial Port
	248	*/
6d0f6bcf JCPV	249	#define CONFIG_SYS_NS16550_SERIAL
	250	#define CONFIG_SYS_NS16550_REG_SIZE 1
	251	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
2ad6b513	252
6d0f6bcf	253	#define CONFIG_SYS_BAUDRATE_TABLE \
396abba2	254	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
7a78f148	255
83302fb8	256	#define CONSOLE ttyS0
2ad6b513	257
6d0f6bcf JCPV	258	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	259	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
2ad6b513	260
7a78f148 TT	261	/*
	262	* PCI
	263	*/
2ad6b513	264	#ifdef CONFIG_PCI
842033e6	265	#define CONFIG_PCI_INDIRECT_BRIDGE
2ad6b513 TT	266
	267	#define CONFIG_MPC83XX_PCI2
	268
	269	/*
	270	* General PCI
	271	* Addresses are mapped 1-1.
	272	*/
6d0f6bcf JCPV	273	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	274	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	275	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
396abba2 JH	276	#define CONFIG_SYS_PCI1_MMIO_BASE \
396abba2 JH	277	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
6d0f6bcf JCPV	278	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
6d0f6bcf JCPV	279	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
396abba2 JH	280	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	281	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	282	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
2ad6b513 TT	283
2ad6b513 TT	284	#ifdef CONFIG_MPC83XX_PCI2
396abba2 JH	285	#define CONFIG_SYS_PCI2_MEM_BASE \
396abba2 JH	286	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
6d0f6bcf JCPV	287	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
6d0f6bcf JCPV	288	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
396abba2 JH	289	#define CONFIG_SYS_PCI2_MMIO_BASE \
396abba2 JH	290	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
6d0f6bcf JCPV	291	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
6d0f6bcf JCPV	292	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
396abba2 JH	293	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	294	#define CONFIG_SYS_PCI2_IO_PHYS \
	295	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
	296	#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
2ad6b513 TT	297	#endif
2ad6b513 TT	298
2ad6b513 TT	299	#ifndef CONFIG_PCI_PNP
2ad6b513 TT	300	#define PCI_ENET0_IOADDR 0x00000000
6d0f6bcf	301	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
2ad6b513 TT	302	#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
	303	#endif
	304
	305	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	306
	307	#endif
	308
	309	/* TSEC */
	310
	311	#ifdef CONFIG_TSEC_ENET
255a3577	312	#define CONFIG_TSEC1
2ad6b513	313
255a3577	314	#ifdef CONFIG_TSEC1
10327dc5	315	#define CONFIG_HAS_ETH0
255a3577	316	#define CONFIG_TSEC1_NAME "TSEC0"
6d0f6bcf	317	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
dd520bf3	318	#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
2ad6b513	319	#define TSEC1_PHYIDX 0
3a79013e	320	#define TSEC1_FLAGS TSEC_GIGABIT
2ad6b513 TT	321	#endif
2ad6b513 TT	322
255a3577	323	#ifdef CONFIG_TSEC2
7a78f148	324	#define CONFIG_HAS_ETH1
255a3577	325	#define CONFIG_TSEC2_NAME "TSEC1"
6d0f6bcf	326	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
89c7784e	327
2ad6b513 TT	328	#define TSEC2_PHY_ADDR 4
2ad6b513 TT	329	#define TSEC2_PHYIDX 0
3a79013e	330	#define TSEC2_FLAGS TSEC_GIGABIT
2ad6b513 TT	331	#endif
	332
	333	#define CONFIG_ETHPRIME "Freescale TSEC"
	334
	335	#endif
	336
2ad6b513 TT	337	/*
	338	* Environment
	339	*/
7a78f148 TT	340	#define CONFIG_ENV_OVERWRITE
7a78f148 TT	341
2ad6b513	342	#define CONFIG_LOADS_ECHO /* echo on for serial download */
6d0f6bcf	343	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
2ad6b513	344
659e2f67 JL	345	/*
	346	* BOOTP options
	347	*/
	348	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	349
2ad6b513	350	/* Watchdog */
2ad6b513	351	#undef CONFIG_WATCHDOG /* watchdog disabled */
2ad6b513 TT	352
	353	/*
	354	* Miscellaneous configurable options
	355	*/
7a78f148	356
6d0f6bcf	357	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
05f91a65	358	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
7a78f148	359
2ad6b513 TT	360	/*
2ad6b513 TT	361	* For booting Linux, the board info and command line data
9f530d59	362	* have to be in the first 256 MB of memory, since this is
2ad6b513 TT	363	* the maximum mapped by the Linux kernel during initialization.
2ad6b513 TT	364	*/
396abba2 JH	365	/* Initial Memory map for Linux*/
396abba2 JH	366	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	367	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
2ad6b513	368
7a78f148 TT	369	/*
	370	* System performance
	371	*/
6d0f6bcf JCPV	372	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
6d0f6bcf JCPV	373	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
c31e1326 VG	374	#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
c31e1326 VG	375	#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
2ad6b513	376
7a78f148 TT	377	/*
	378	* System IO Config
	379	*/
396abba2 JH	380	/* Needed for gigabit to work on TSEC 1 */
	381	#define CONFIG_SYS_SICRH SICRH_TSOBI1
	382	/* USB DR as device + USB MPH as host */
	383	#define CONFIG_SYS_SICRL (SICRL_LDP_A \| SICRL_USB1)
2ad6b513	384
8ea5499a	385	#if defined(CONFIG_CMD_KGDB)
2ad6b513	386	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
2ad6b513 TT	387	#endif
2ad6b513 TT	388
2ad6b513 TT	389	/*
	390	* Environment Configuration
	391	*/
	392	#define CONFIG_ENV_OVERWRITE
	393
396abba2	394	#define CONFIG_NETDEV "eth0"
2ad6b513	395
7a78f148	396	/* Default path and filenames */
8b3637c6	397	#define CONFIG_ROOTPATH "/nfsroot/rootfs"
b3f44c21	398	#define CONFIG_BOOTFILE "uImage"
396abba2 JH	399	/* U-Boot image on TFTP server */
396abba2 JH	400	#define CONFIG_UBOOTPATH "u-boot.bin"
2ad6b513	401
4cb06d3e	402	#ifdef CONFIG_TARGET_MPC8349ITX
396abba2	403	#define CONFIG_FDTFILE "mpc8349emitx.dtb"
2ad6b513	404	#else
396abba2	405	#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
2ad6b513 TT	406	#endif
2ad6b513 TT	407
7a78f148	408
dd520bf3	409	#define CONFIG_EXTRA_ENV_SETTINGS \
83302fb8	410	"console=" __stringify(CONSOLE) "\0" \
396abba2 JH	411	"netdev=" CONFIG_NETDEV "\0" \
396abba2 JH	412	"uboot=" CONFIG_UBOOTPATH "\0" \
53677ef1	413	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	414	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	415	" +$filesize; " \
	416	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	417	" +$filesize; " \
	418	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	419	" $filesize; " \
	420	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	421	" +$filesize; " \
	422	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	423	" $filesize\0" \
05f91a65	424	"fdtaddr=780000\0" \
396abba2	425	"fdtfile=" CONFIG_FDTFILE "\0"
bf0b542d	426
dd520bf3	427	#define CONFIG_NFSBOOTCOMMAND \
7a78f148	428	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
396abba2	429	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
7a78f148 TT	430	" console=$console,$baudrate $othbootargs; " \
	431	"tftp $loadaddr $bootfile;" \
	432	"tftp $fdtaddr $fdtfile;" \
	433	"bootm $loadaddr - $fdtaddr"
bf0b542d	434
dd520bf3	435	#define CONFIG_RAMBOOTCOMMAND \
7a78f148 TT	436	"setenv bootargs root=/dev/ram rw" \
	437	" console=$console,$baudrate $othbootargs; " \
	438	"tftp $ramdiskaddr $ramdiskfile;" \
	439	"tftp $loadaddr $bootfile;" \
	440	"tftp $fdtaddr $fdtfile;" \
	441	"bootm $loadaddr $ramdiskaddr $fdtaddr"
2ad6b513	442
2ad6b513	443	#endif