[J-u-boot.git] / board / freescale / common / pixis.c

/*
 * Copyright 2006,2010 Freescale Semiconductor
 * Jeff Brown
 * Srikanth Srinivasan ([email protected])
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <asm/io.h>

#define pixis_base (u8 *)PIXIS_BASE

/*
 * Simple board reset.
 */
void pixis_reset(void)
{
	out_8(pixis_base + PIXIS_RST, 0);

	while (1);
}

/*
 * Per table 27, page 58 of MPC8641HPCN spec.
 */
static int set_px_sysclk(unsigned long sysclk)
{
	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;

	switch (sysclk) {
	case 33:
		sysclk_s = 0x04;
		sysclk_r = 0x04;
		sysclk_v = 0x07;
		sysclk_aux = 0x00;
		break;
	case 40:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x20;
		sysclk_aux = 0x01;
		break;
	case 50:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x2A;
		sysclk_aux = 0x02;
		break;
	case 66:
		sysclk_s = 0x01;
		sysclk_r = 0x04;
		sysclk_v = 0x04;
		sysclk_aux = 0x03;
		break;
	case 83:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x04;
		break;
	case 100:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x5C;
		sysclk_aux = 0x05;
		break;
	case 134:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x3B;
		sysclk_aux = 0x06;
		break;
	case 166:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x07;
		break;
	default:
		printf("Unsupported SYSCLK frequency.\n");
		return 0;
	}

	vclkh = (sysclk_s << 5) | sysclk_r;
	vclkl = sysclk_v;

	out_8(pixis_base + PIXIS_VCLKH, vclkh);
	out_8(pixis_base + PIXIS_VCLKL, vclkl);

	out_8(pixis_base + PIXIS_AUX, sysclk_aux);

	return 1;
}

/* Set the CFG_SYSPLL bits
 *
 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
 * read_from_px_regs() is called.
 */
static int set_px_mpxpll(unsigned long mpxpll)
{
	switch (mpxpll) {
	case 2:
	case 4:
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
	case 16:
		clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
		return 1;
	}

	printf("Unsupported MPXPLL ratio.\n");
	return 0;
}

static int set_px_corepll(unsigned long corepll)
{
	u8 val;

	switch (corepll) {
	case 20:
		val = 0x08;
		break;
	case 25:
		val = 0x0C;
		break;
	case 30:
		val = 0x10;
		break;
	case 35:
		val = 0x1C;
		break;
	case 40:
		val = 0x14;
		break;
	case 45:
		val = 0x0E;
		break;
	default:
		printf("Unsupported COREPLL ratio.\n");
		return 0;
	}

	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
	return 1;
}

#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
#endif

/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
 *
 * The PIXIS can be programmed to look at either the on-board dip switches
 * or various other PIXIS registers to determine the values for COREPLL,
 * MPXPLL, and SYSCLK.
 *
 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
 * register that tells the pixis to use the various PIXIS register.
 */
static void read_from_px_regs(int set)
{
	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);

	if (set)
		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
	else
		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;

	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}

/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
 */
#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
#endif

/* Configure the source of the boot location
 *
 * The PIXIS can be programmed to look at either the on-board dip switches
 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
 *
 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
 */
static void read_from_px_regs_altbank(int set)
{
	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);

	if (set)
		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
	else
		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;

	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}

/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
 * tells the PIXIS what the alternate flash bank is.
 *
 * Note that it's not really a mask.  It contains the actual LBMAP bits that
 * must be set to select the alternate bank.  This code assumes that the
 * primary bank has these bits set to 0, and the alternate bank has these
 * bits set to 1.
 */
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
#endif

/* Tell the PIXIS to boot from the default flash bank
 *
 * Program the default flash bank into the VBOOT register.  This register is
 * used only if PX_VCFGEN1[FLASH]=1.
 */
static void clear_altbank(void)
{
	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}

/* Tell the PIXIS to boot from the alternate flash bank
 *
 * Program the alternate flash bank into the VBOOT register.  This register is
 * used only if PX_VCFGEN1[FLASH]=1.
 */
static void set_altbank(void)
{
	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}

/* Reset the board with watchdog disabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go(void)
{
	/* Disable the VELA sequencer and watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	/* Reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x1);

	while (1);
}

/* Reset the board with watchdog enabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go_with_watchdog(void)
{
	/* Disable the VELA sequencer */
	clrbits_8(pixis_base + PIXIS_VCTL, 1);

	/* Enable the watchdog and reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x9);

	while (1);
}

/* Disable the watchdog
 *
 */
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
				      char * const argv[])
{
	/* Disable the VELA sequencer and the watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	return 0;
}

U_BOOT_CMD(
	diswd, 1, 0, pixis_disable_watchdog_cmd,
	"Disable watchdog timer",
	""
);

#ifdef CONFIG_PIXIS_SGMII_CMD

/* Enable or disable SGMII mode for a TSEC
 */
static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int which_tsec = -1;
	unsigned char mask;
	unsigned char switch_mask;

	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
		which_tsec = simple_strtoul(argv[1], NULL, 0);

	switch (which_tsec) {
#ifdef CONFIG_TSEC1
	case 1:
		mask = PIXIS_VSPEED2_TSEC1SER;
		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
		break;
#endif
#ifdef CONFIG_TSEC2
	case 2:
		mask = PIXIS_VSPEED2_TSEC2SER;
		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
		break;
#endif
#ifdef CONFIG_TSEC3
	case 3:
		mask = PIXIS_VSPEED2_TSEC3SER;
		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
		break;
#endif
#ifdef CONFIG_TSEC4
	case 4:
		mask = PIXIS_VSPEED2_TSEC4SER;
		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
		break;
#endif
	default:
		mask = PIXIS_VSPEED2_MASK;
		switch_mask = PIXIS_VCFGEN1_MASK;
		break;
	}

	/* Toggle whether the switches or FPGA control the settings */
	if (!strcmp(argv[argc - 1], "switch"))
		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
	else
		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);

	/* If it's not the switches, enable or disable SGMII, as specified */
	if (!strcmp(argv[argc - 1], "on"))
		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
	else if (!strcmp(argv[argc - 1], "off"))
		setbits_8(pixis_base + PIXIS_VSPEED2, mask);

	return 0;
}

U_BOOT_CMD(
	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
	"pixis_set_sgmii"
	" - Enable or disable SGMII mode for a given TSEC \n",
	"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
	"    TSEC num: 1,2,3,4 or 'all'.  'all' is default.\n"
	"    on - enables SGMII\n"
	"    off - disables SGMII\n"
	"    switch - use switch settings"
);

#endif

/*
 * This function takes the non-integral cpu:mpx pll ratio
 * and converts it to an integer that can be used to assign
 * FPGA register values.
 * input: strptr i.e. argv[2]
 */
static unsigned long strfractoint(char *strptr)
{
	int i, j;
	int mulconst;
	int intarr_len, no_dec = 0;
	unsigned long intval = 0, decval = 0;
	char intarr[3], decarr[3];

	/* Assign the integer part to intarr[]
	 * If there is no decimal point i.e.
	 * if the ratio is an integral value
	 * simply create the intarr.
	 */
	i = 0;
	while (strptr[i] != '.') {
		if (strptr[i] == 0) {
			no_dec = 1;
			break;
		}
		intarr[i] = strptr[i];
		i++;
	}

	/* Assign length of integer part to intarr_len. */
	intarr_len = i;
	intarr[i] = '\0';

	if (no_dec) {
		/* Currently needed only for single digit corepll ratios */
		mulconst = 10;
		decval = 0;
	} else {
		j = 0;
		i++;		/* Skipping the decimal point */
		while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
			decarr[j] = strptr[i];
			i++;
			j++;
		}

		decarr[j] = '\0';

		mulconst = 1;
		for (i = 0; i < j; i++)
			mulconst *= 10;
		decval = simple_strtoul(decarr, NULL, 10);
	}

	intval = simple_strtoul(intarr, NULL, 10);
	intval = intval * mulconst;

	return intval + decval;
}

static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	unsigned int i;
	char *p_cf = NULL;
	char *p_cf_sysclk = NULL;
	char *p_cf_corepll = NULL;
	char *p_cf_mpxpll = NULL;
	char *p_altbank = NULL;
	char *p_wd = NULL;
	int unknown_param = 0;

	/*
	 * No args is a simple reset request.
	 */
	if (argc <= 1) {
		pixis_reset();
		/* not reached */
	}

	for (i = 1; i < argc; i++) {
		if (strcmp(argv[i], "cf") == 0) {
			p_cf = argv[i];
			if (i + 3 >= argc) {
				break;
			}
			p_cf_sysclk = argv[i+1];
			p_cf_corepll = argv[i+2];
			p_cf_mpxpll = argv[i+3];
			i += 3;
			continue;
		}

		if (strcmp(argv[i], "altbank") == 0) {
			p_altbank = argv[i];
			continue;
		}

		if (strcmp(argv[i], "wd") == 0) {
			p_wd = argv[i];
			continue;
		}

		unknown_param = 1;
	}

	/*
	 * Check that cf has all required parms
	 */
	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
	    ||	unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
		puts(cmdtp->help);
#endif
		return 1;
	}

	/*
	 * PIXIS seems to be sensitive to the ordering of
	 * the registers that are touched.
	 */
	read_from_px_regs(0);

	if (p_altbank)
		read_from_px_regs_altbank(0);

	clear_altbank();

	/*
	 * Clock configuration specified.
	 */
	if (p_cf) {
		unsigned long sysclk;
		unsigned long corepll;
		unsigned long mpxpll;

		sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
		corepll = strfractoint(p_cf_corepll);
		mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);

		if (!(set_px_sysclk(sysclk)
		      && set_px_corepll(corepll)
		      && set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
			puts(cmdtp->help);
#endif
			return 1;
		}
		read_from_px_regs(1);
	}

	/*
	 * Altbank specified
	 *
	 * NOTE CHANGE IN BEHAVIOR: previous code would default
	 * to enabling watchdog if altbank is specified.
	 * Now the watchdog must be enabled explicitly using 'wd'.
	 */
	if (p_altbank) {
		set_altbank();
		read_from_px_regs_altbank(1);
	}

	/*
	 * Reset with watchdog specified.
	 */
	if (p_wd)
		set_px_go_with_watchdog();
	else
		set_px_go();

	/*
	 * Shouldn't be reached.
	 */
	return 0;
}


U_BOOT_CMD(
	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
	"Reset the board using the FPGA sequencer",
	"    pixis_reset\n"
	"    pixis_reset [altbank]\n"
	"    pixis_reset altbank wd\n"
	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
);
Commit	Line	Data
126aa70f	1	/*
2feb4af0	2	* Copyright 2006,2010 Freescale Semiconductor
126aa70f JL	3	* Jeff Brown
	4	* Srikanth Srinivasan ([email protected])
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
126aa70f	26	#include <command.h>
5a8a163a	27	#include <asm/io.h>
ad8f8687	28
2feb4af0	29	#define pixis_base (u8 *)PIXIS_BASE
3d98b858 HW	30
	31	/*
	32	* Simple board reset.
	33	*/
	34	void pixis_reset(void)
	35	{
048e7efe	36	out_8(pixis_base + PIXIS_RST, 0);
3d98b858	37
2feb4af0 TT	38	while (1);
2feb4af0 TT	39	}
3d98b858	40
126aa70f JL	41	/*
	42	* Per table 27, page 58 of MPC8641HPCN spec.
	43	*/
2feb4af0	44	static int set_px_sysclk(unsigned long sysclk)
126aa70f JL	45	{
	46	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
	47
	48	switch (sysclk) {
	49	case 33:
	50	sysclk_s = 0x04;
	51	sysclk_r = 0x04;
	52	sysclk_v = 0x07;
	53	sysclk_aux = 0x00;
	54	break;
	55	case 40:
	56	sysclk_s = 0x01;
	57	sysclk_r = 0x1F;
	58	sysclk_v = 0x20;
	59	sysclk_aux = 0x01;
	60	break;
	61	case 50:
	62	sysclk_s = 0x01;
	63	sysclk_r = 0x1F;
	64	sysclk_v = 0x2A;
	65	sysclk_aux = 0x02;
	66	break;
	67	case 66:
	68	sysclk_s = 0x01;
	69	sysclk_r = 0x04;
	70	sysclk_v = 0x04;
	71	sysclk_aux = 0x03;
	72	break;
	73	case 83:
	74	sysclk_s = 0x01;
	75	sysclk_r = 0x1F;
	76	sysclk_v = 0x4B;
	77	sysclk_aux = 0x04;
	78	break;
	79	case 100:
	80	sysclk_s = 0x01;
	81	sysclk_r = 0x1F;
	82	sysclk_v = 0x5C;
	83	sysclk_aux = 0x05;
	84	break;
	85	case 134:
	86	sysclk_s = 0x06;
	87	sysclk_r = 0x1F;
	88	sysclk_v = 0x3B;
	89	sysclk_aux = 0x06;
	90	break;
	91	case 166:
	92	sysclk_s = 0x06;
	93	sysclk_r = 0x1F;
	94	sysclk_v = 0x4B;
	95	sysclk_aux = 0x07;
	96	break;
	97	default:
	98	printf("Unsupported SYSCLK frequency.\n");
	99	return 0;
	100	}
	101
80e955c7	102	vclkh = (sysclk_s << 5) \| sysclk_r;
126aa70f JL	103	vclkl = sysclk_v;
126aa70f JL	104
048e7efe KG	105	out_8(pixis_base + PIXIS_VCLKH, vclkh);
048e7efe KG	106	out_8(pixis_base + PIXIS_VCLKL, vclkl);
126aa70f	107
048e7efe	108	out_8(pixis_base + PIXIS_AUX, sysclk_aux);
126aa70f JL	109
	110	return 1;
	111	}
	112
2feb4af0 TT	113	/* Set the CFG_SYSPLL bits
	114	*
	115	* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
	116	* read_from_px_regs() is called.
	117	*/
	118	static int set_px_mpxpll(unsigned long mpxpll)
126aa70f	119	{
126aa70f JL	120	switch (mpxpll) {
	121	case 2:
	122	case 4:
	123	case 6:
	124	case 8:
	125	case 10:
	126	case 12:
	127	case 14:
	128	case 16:
2feb4af0 TT	129	clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
2feb4af0 TT	130	return 1;
126aa70f JL	131	}
126aa70f JL	132
2feb4af0 TT	133	printf("Unsupported MPXPLL ratio.\n");
2feb4af0 TT	134	return 0;
126aa70f JL	135	}
126aa70f JL	136
2feb4af0	137	static int set_px_corepll(unsigned long corepll)
126aa70f	138	{
126aa70f JL	139	u8 val;
126aa70f JL	140
2feb4af0	141	switch (corepll) {
126aa70f JL	142	case 20:
	143	val = 0x08;
	144	break;
	145	case 25:
	146	val = 0x0C;
	147	break;
	148	case 30:
	149	val = 0x10;
	150	break;
	151	case 35:
	152	val = 0x1C;
	153	break;
	154	case 40:
	155	val = 0x14;
	156	break;
	157	case 45:
	158	val = 0x0E;
	159	break;
	160	default:
	161	printf("Unsupported COREPLL ratio.\n");
	162	return 0;
	163	}
	164
2feb4af0	165	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
126aa70f JL	166	return 1;
	167	}
	168
2feb4af0 TT	169	#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
	170	#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
	171	#endif
126aa70f	172
2feb4af0 TT	173	/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
	174	*
	175	* The PIXIS can be programmed to look at either the on-board dip switches
	176	* or various other PIXIS registers to determine the values for COREPLL,
	177	* MPXPLL, and SYSCLK.
	178	*
	179	* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
	180	* register that tells the pixis to use the various PIXIS register.
	181	*/
	182	static void read_from_px_regs(int set)
126aa70f	183	{
048e7efe	184	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
126aa70f JL	185
126aa70f JL	186	if (set)
2feb4af0	187	tmp = tmp \| CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
126aa70f	188	else
2feb4af0 TT	189	tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
2feb4af0 TT	190
048e7efe	191	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
126aa70f JL	192	}
126aa70f JL	193
2feb4af0 TT	194	/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
	195	* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
	196	*/
	197	#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
	198	#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
	199	#endif
126aa70f	200
2feb4af0 TT	201	/* Configure the source of the boot location
	202	*
	203	* The PIXIS can be programmed to look at either the on-board dip switches
	204	* or the PX_VBOOT[LBMAP] register to determine where we should boot.
	205	*
	206	* If we want to boot from the alternate boot bank, we need to tell the PIXIS
	207	* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
	208	*/
	209	static void read_from_px_regs_altbank(int set)
126aa70f	210	{
048e7efe	211	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
126aa70f JL	212
126aa70f JL	213	if (set)
2feb4af0	214	tmp = tmp \| CONFIG_SYS_PIXIS_VBOOT_ENABLE;
126aa70f	215	else
2feb4af0 TT	216	tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
2feb4af0 TT	217
048e7efe	218	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
126aa70f JL	219	}
126aa70f JL	220
2feb4af0 TT	221	/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
	222	* tells the PIXIS what the alternate flash bank is.
	223	*
	224	* Note that it's not really a mask. It contains the actual LBMAP bits that
	225	* must be set to select the alternate bank. This code assumes that the
	226	* primary bank has these bits set to 0, and the alternate bank has these
	227	* bits set to 1.
	228	*/
6d0f6bcf JCPV	229	#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
6d0f6bcf JCPV	230	#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
db74b3c1	231	#endif
126aa70f	232
2feb4af0 TT	233	/* Tell the PIXIS to boot from the default flash bank
	234	*
	235	* Program the default flash bank into the VBOOT register. This register is
	236	* used only if PX_VCFGEN1[FLASH]=1.
	237	*/
	238	static void clear_altbank(void)
16c3cde0	239	{
2feb4af0	240	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
16c3cde0 JY	241	}
16c3cde0 JY	242
2feb4af0 TT	243	/* Tell the PIXIS to boot from the alternate flash bank
	244	*
	245	* Program the alternate flash bank into the VBOOT register. This register is
	246	* used only if PX_VCFGEN1[FLASH]=1.
	247	*/
	248	static void set_altbank(void)
126aa70f	249	{
2feb4af0	250	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
126aa70f JL	251	}
126aa70f JL	252
2feb4af0 TT	253	/* Reset the board with watchdog disabled.
	254	*
	255	* This respects the altbank setting.
	256	*/
	257	static void set_px_go(void)
126aa70f	258	{
2feb4af0 TT	259	/* Disable the VELA sequencer and watchdog */
2feb4af0 TT	260	clrbits_8(pixis_base + PIXIS_VCTL, 9);
126aa70f	261
2feb4af0 TT	262	/* Reboot by starting the VELA sequencer */
2feb4af0 TT	263	setbits_8(pixis_base + PIXIS_VCTL, 0x1);
126aa70f	264
2feb4af0	265	while (1);
126aa70f JL	266	}
126aa70f JL	267
2feb4af0 TT	268	/* Reset the board with watchdog enabled.
	269	*
	270	* This respects the altbank setting.
	271	*/
	272	static void set_px_go_with_watchdog(void)
126aa70f	273	{
2feb4af0 TT	274	/* Disable the VELA sequencer */
2feb4af0 TT	275	clrbits_8(pixis_base + PIXIS_VCTL, 1);
126aa70f	276
2feb4af0 TT	277	/* Enable the watchdog and reboot by starting the VELA sequencer */
2feb4af0 TT	278	setbits_8(pixis_base + PIXIS_VCTL, 0x9);
126aa70f	279
2feb4af0	280	while (1);
126aa70f JL	281	}
126aa70f JL	282
2feb4af0 TT	283	/* Disable the watchdog
	284	*
	285	*/
	286	static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
54841ab5	287	char * const argv[])
126aa70f	288	{
2feb4af0 TT	289	/* Disable the VELA sequencer and the watchdog */
2feb4af0 TT	290	clrbits_8(pixis_base + PIXIS_VCTL, 9);
126aa70f JL	291
	292	return 0;
	293	}
	294
126aa70f	295	U_BOOT_CMD(
a89c33db WD	296	diswd, 1, 0, pixis_disable_watchdog_cmd,
	297	"Disable watchdog timer",
	298	""
	299	);
126aa70f	300
bff188ba	301	#ifdef CONFIG_PIXIS_SGMII_CMD
2feb4af0 TT	302
	303	/* Enable or disable SGMII mode for a TSEC
	304	*/
54841ab5	305	static int pixis_set_sgmii(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
5a8a163a AF	306	{
5a8a163a AF	307	int which_tsec = -1;
2feb4af0 TT	308	unsigned char mask;
2feb4af0 TT	309	unsigned char switch_mask;
5a8a163a	310
2feb4af0 TT	311	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
2feb4af0 TT	312	which_tsec = simple_strtoul(argv[1], NULL, 0);
5a8a163a AF	313
5a8a163a AF	314	switch (which_tsec) {
bff188ba	315	#ifdef CONFIG_TSEC1
5a8a163a AF	316	case 1:
	317	mask = PIXIS_VSPEED2_TSEC1SER;
	318	switch_mask = PIXIS_VCFGEN1_TSEC1SER;
	319	break;
bff188ba LY	320	#endif
	321	#ifdef CONFIG_TSEC2
	322	case 2:
	323	mask = PIXIS_VSPEED2_TSEC2SER;
	324	switch_mask = PIXIS_VCFGEN1_TSEC2SER;
	325	break;
	326	#endif
	327	#ifdef CONFIG_TSEC3
5a8a163a AF	328	case 3:
	329	mask = PIXIS_VSPEED2_TSEC3SER;
	330	switch_mask = PIXIS_VCFGEN1_TSEC3SER;
	331	break;
bff188ba LY	332	#endif
	333	#ifdef CONFIG_TSEC4
	334	case 4:
	335	mask = PIXIS_VSPEED2_TSEC4SER;
	336	switch_mask = PIXIS_VCFGEN1_TSEC4SER;
	337	break;
	338	#endif
5a8a163a	339	default:
bff188ba LY	340	mask = PIXIS_VSPEED2_MASK;
bff188ba LY	341	switch_mask = PIXIS_VCFGEN1_MASK;
5a8a163a AF	342	break;
	343	}
	344
	345	/* Toggle whether the switches or FPGA control the settings */
	346	if (!strcmp(argv[argc - 1], "switch"))
048e7efe	347	clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
5a8a163a	348	else
048e7efe	349	setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
5a8a163a AF	350
	351	/* If it's not the switches, enable or disable SGMII, as specified */
	352	if (!strcmp(argv[argc - 1], "on"))
048e7efe	353	clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
5a8a163a	354	else if (!strcmp(argv[argc - 1], "off"))
048e7efe	355	setbits_8(pixis_base + PIXIS_VSPEED2, mask);
5a8a163a AF	356
	357	return 0;
	358	}
	359
	360	U_BOOT_CMD(
a89c33db WD	361	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
	362	"pixis_set_sgmii"
	363	" - Enable or disable SGMII mode for a given TSEC \n",
	364	"\npixis_set_sgmii [TSEC num] <on\|off\|switch>\n"
	365	" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
	366	" on - enables SGMII\n"
	367	" off - disables SGMII\n"
	368	" switch - use switch settings"
	369	);
2feb4af0	370
5a8a163a AF	371	#endif
5a8a163a AF	372
126aa70f JL	373	/*
	374	* This function takes the non-integral cpu:mpx pll ratio
	375	* and converts it to an integer that can be used to assign
	376	* FPGA register values.
	377	* input: strptr i.e. argv[2]
	378	*/
2feb4af0	379	static unsigned long strfractoint(char *strptr)
126aa70f	380	{
2feb4af0	381	int i, j;
126aa70f	382	int mulconst;
2feb4af0 TT	383	int intarr_len, no_dec = 0;
	384	unsigned long intval = 0, decval = 0;
	385	char intarr[3], decarr[3];
126aa70f JL	386
	387	/* Assign the integer part to intarr[]
	388	* If there is no decimal point i.e.
	389	* if the ratio is an integral value
	390	* simply create the intarr.
	391	*/
	392	i = 0;
16c3cde0	393	while (strptr[i] != '.') {
126aa70f JL	394	if (strptr[i] == 0) {
	395	no_dec = 1;
	396	break;
	397	}
	398	intarr[i] = strptr[i];
	399	i++;
	400	}
	401
	402	/* Assign length of integer part to intarr_len. */
	403	intarr_len = i;
	404	intarr[i] = '\0';
	405
	406	if (no_dec) {
	407	/* Currently needed only for single digit corepll ratios */
80e955c7	408	mulconst = 10;
126aa70f JL	409	decval = 0;
	410	} else {
	411	j = 0;
80e955c7	412	i++; /* Skipping the decimal point */
16c3cde0	413	while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
126aa70f JL	414	decarr[j] = strptr[i];
	415	i++;
	416	j++;
	417	}
	418
126aa70f JL	419	decarr[j] = '\0';
	420
	421	mulconst = 1;
2feb4af0	422	for (i = 0; i < j; i++)
126aa70f	423	mulconst *= 10;
2feb4af0	424	decval = simple_strtoul(decarr, NULL, 10);
126aa70f JL	425	}
126aa70f JL	426
2feb4af0	427	intval = simple_strtoul(intarr, NULL, 10);
126aa70f JL	428	intval = intval * mulconst;
126aa70f JL	429
2feb4af0	430	return intval + decval;
126aa70f	431	}
3d98b858	432
54841ab5	433	static int pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
3d98b858	434	{
16c3cde0 JY	435	unsigned int i;
	436	char *p_cf = NULL;
	437	char *p_cf_sysclk = NULL;
	438	char *p_cf_corepll = NULL;
	439	char *p_cf_mpxpll = NULL;
	440	char *p_altbank = NULL;
	441	char *p_wd = NULL;
2feb4af0	442	int unknown_param = 0;
3d98b858 HW	443
	444	/*
	445	* No args is a simple reset request.
	446	*/
	447	if (argc <= 1) {
	448	pixis_reset();
	449	/* not reached */
	450	}
	451
16c3cde0 JY	452	for (i = 1; i < argc; i++) {
	453	if (strcmp(argv[i], "cf") == 0) {
	454	p_cf = argv[i];
	455	if (i + 3 >= argc) {
	456	break;
	457	}
	458	p_cf_sysclk = argv[i+1];
	459	p_cf_corepll = argv[i+2];
	460	p_cf_mpxpll = argv[i+3];
	461	i += 3;
	462	continue;
	463	}
3d98b858	464
16c3cde0 JY	465	if (strcmp(argv[i], "altbank") == 0) {
	466	p_altbank = argv[i];
	467	continue;
3d98b858 HW	468	}
3d98b858 HW	469
16c3cde0 JY	470	if (strcmp(argv[i], "wd") == 0) {
	471	p_wd = argv[i];
	472	continue;
3d98b858 HW	473	}
3d98b858 HW	474
16c3cde0 JY	475	unknown_param = 1;
16c3cde0 JY	476	}
3d98b858	477
16c3cde0 JY	478	/*
	479	* Check that cf has all required parms
	480	*/
	481	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
53677ef1	482	\|\| unknown_param) {
f7fecc3e	483	#ifdef CONFIG_SYS_LONGHELP
16c3cde0	484	puts(cmdtp->help);
f7fecc3e	485	#endif
16c3cde0 JY	486	return 1;
	487	}
	488
	489	/*
	490	* PIXIS seems to be sensitive to the ordering of
	491	* the registers that are touched.
	492	*/
	493	read_from_px_regs(0);
	494
2feb4af0	495	if (p_altbank)
16c3cde0	496	read_from_px_regs_altbank(0);
2feb4af0	497
16c3cde0 JY	498	clear_altbank();
	499
	500	/*
	501	* Clock configuration specified.
	502	*/
	503	if (p_cf) {
	504	unsigned long sysclk;
	505	unsigned long corepll;
	506	unsigned long mpxpll;
	507
	508	sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
2feb4af0	509	corepll = strfractoint(p_cf_corepll);
16c3cde0 JY	510	mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
	511
	512	if (!(set_px_sysclk(sysclk)
	513	&& set_px_corepll(corepll)
	514	&& set_px_mpxpll(mpxpll))) {
f7fecc3e	515	#ifdef CONFIG_SYS_LONGHELP
16c3cde0	516	puts(cmdtp->help);
f7fecc3e	517	#endif
3d98b858 HW	518	return 1;
3d98b858 HW	519	}
16c3cde0 JY	520	read_from_px_regs(1);
16c3cde0 JY	521	}
3d98b858	522
16c3cde0 JY	523	/*
	524	* Altbank specified
	525	*
	526	* NOTE CHANGE IN BEHAVIOR: previous code would default
	527	* to enabling watchdog if altbank is specified.
	528	* Now the watchdog must be enabled explicitly using 'wd'.
	529	*/
	530	if (p_altbank) {
	531	set_altbank();
	532	read_from_px_regs_altbank(1);
	533	}
	534
	535	/*
	536	* Reset with watchdog specified.
	537	*/
2feb4af0	538	if (p_wd)
16c3cde0	539	set_px_go_with_watchdog();
2feb4af0	540	else
16c3cde0	541	set_px_go();
3d98b858	542
16c3cde0 JY	543	/*
	544	* Shouldn't be reached.
	545	*/
3d98b858 HW	546	return 0;
	547	}
	548
	549
	550	U_BOOT_CMD(
6d0f6bcf	551	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
2fb2604d	552	"Reset the board using the FPGA sequencer",
3d98b858 HW	553	" pixis_reset\n"
	554	" pixis_reset [altbank]\n"
	555	" pixis_reset altbank wd\n"
	556	" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
a89c33db WD	557	" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
a89c33db WD	558	);