[J-u-boot.git] / include / configs / MPC8548CDS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
 * Copyright 2020 NXP
 */

/*
 * mpc8548cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI1		/* PCI controller 1 */
#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#ifndef __ASSEMBLY__
#include <linux/stringify.h>
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

/*
 * Physical Address Map
 *
 * 32bit:
 * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
 * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
 * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
 * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
 * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
 * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 * 36bit:
 * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
 * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
 * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
 * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
 * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
 * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
 * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
 */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_BR0_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
#define CONFIG_SYS_BR1_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)

#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
#define	CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST \
	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_HWCONFIG			/* enable hwconfig */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
#else
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
	| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows	OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *		    or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL	  = BR[24:26] = 000
 *    Valid		  = BR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT		  OR[20]    = 1
 *    ACS		  OR[21:22] = 11
 *    XACS		  OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA		  OR[28]    = 0
 *    TRLX		  OR[29]    = 1
 *    EHTR		  OR[30]    = 1
 *    EAD extra time	  OR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#ifdef CONFIG_PHYS_64BIT
#define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
#else
#define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
#endif
#define CONFIG_SYS_BR3_PRELIM \
	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#else
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
#endif

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_CCID

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#else
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#endif
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
#endif
#endif

/*
 * RapidIO MMU
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME	"eTSEC3"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC3_PHY_ADDR		2
#define TSEC4_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC4_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME		"eTSEC0"
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR	 192.168.1.253

#define CONFIG_HOSTNAME	 "unknown"
#define CONFIG_ROOTPATH	 "/nfsroot"
#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	 255.255.255.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:ecc=off\0"		\
	"netdev=eth0\0"				\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot; "	\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"consoledev=ttyS1\0"			\
	"ramdiskaddr=2000000\0"			\
	"ramdiskfile=ramdisk.uboot\0"		\
	"fdtaddr=1e00000\0"			\
	"fdtfile=mpc8548cds.dtb\0"

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
d9b94f28	2	/*
8b47d7ec	3	* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
01d97d5f	4	* Copyright 2020 NXP
d9b94f28 JL	5	*/
	6
	7	/*
	8	* mpc8548cds board configuration file
	9	*
	10	* Please refer to doc/README.mpc85xxcds for more info.
	11	*
	12	*/
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
8b47d7ec KG	16	#define CONFIG_SYS_SRIO
	17	#define CONFIG_SRIO1 /* SRIO port 1 */
	18
f2cff6b1	19	#define CONFIG_PCI1 /* PCI controller 1 */
b38eaec5	20	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
f2cff6b1	21	#undef CONFIG_PCI2
0151cbac	22	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
f2cff6b1	23
f2cff6b1	24	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
d9b94f28	25
d9b94f28	26	#ifndef __ASSEMBLY__
1af3c7f4	27	#include <linux/stringify.h>
d9b94f28 JL	28	extern unsigned long get_clock_freq(void);
	29	#endif
	30	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	31
	32	/*
	33	* These can be toggled for performance analysis, otherwise use default.
	34	*/
f2cff6b1 ES	35	#define CONFIG_L2_CACHE /* toggle L2 cache */
f2cff6b1 ES	36	#define CONFIG_BTB /* toggle branch predition */
d9b94f28 JL	37
	38	/*
	39	* Only possible on E500 Version 2 or newer cores.
	40	*/
	41	#define CONFIG_ENABLE_36BIT_PHYS 1
	42
e46fedfe TT	43	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	44	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
d9b94f28	45
e31d2c1e	46	/* DDR Setup */
e31d2c1e JL	47	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
e31d2c1e JL	48	#define CONFIG_DDR_SPD
e31d2c1e	49
867b06f4	50	#define CONFIG_DDR_ECC
9b0ad1b1	51	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
e31d2c1e JL	52	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
e31d2c1e JL	53
6d0f6bcf JCPV	54	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	55	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
d9b94f28	56
e31d2c1e JL	57	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
e31d2c1e JL	58	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
d9b94f28	59
e31d2c1e JL	60	/* I2C addresses of SPD EEPROMs */
	61	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	62
	63	/* Make sure required options are set */
d9b94f28 JL	64	#ifndef CONFIG_SPD_EEPROM
	65	#error ("CONFIG_SPD_EEPROM is required")
	66	#endif
	67
fff80975	68	/*
	69	* Physical Address Map
	70	*
	71	* 32bit:
	72	* 0x0000_0000 0x7fff_ffff DDR 2G cacheable
	73	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
	74	* 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
	75	* 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
	76	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	77	* 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
	78	* 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
	79	* 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
	80	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
	81	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	82	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	83	*
b76aef60	84	* 36bit:
	85	* 0x00000_0000 0x07fff_ffff DDR 2G cacheable
	86	* 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
	87	* 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
	88	* 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
	89	* 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
	90	* 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
	91	* 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
	92	* 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
	93	* 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
	94	* 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
	95	* 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
	96	*
fff80975	97	*/
fff80975	98
d9b94f28 JL	99	/*
	100	* Local Bus Definitions
	101	*/
	102
	103	/*
	104	* FLASH on the Local Bus
	105	* Two banks, 8M each, using the CFI driver.
	106	* Boot from BR0/OR0 bank at 0xff00_0000
	107	* Alternate BR1/OR1 bank at 0xff80_0000
	108	*
	109	* BR0, BR1:
	110	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	111	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	112	* Port Size = 16 bits = BRx[19:20] = 10
	113	* Use GPCM = BRx[24:26] = 000
	114	* Valid = BRx[31] = 1
	115	*
f2cff6b1 ES	116	* 0 4 8 12 16 20 24 28
	117	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	118	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
d9b94f28 JL	119	*
	120	* OR0, OR1:
	121	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	122	* Reserved ORx[17:18] = 11, confusion here?
	123	* CSNT = ORx[20] = 1
	124	* ACS = half cycle delay = ORx[21:22] = 11
	125	* SCY = 6 = ORx[24:27] = 0110
	126	* TRLX = use relaxed timing = ORx[29] = 1
	127	* EAD = use external address latch delay = OR[31] = 1
	128	*
f2cff6b1 ES	129	* 0 4 8 12 16 20 24 28
f2cff6b1 ES	130	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
d9b94f28 JL	131	*/
d9b94f28 JL	132
fff80975	133	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
b76aef60	134	#ifdef CONFIG_PHYS_64BIT
	135	#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
	136	#else
fff80975	137	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
b76aef60	138	#endif
d9b94f28	139
fff80975	140	#define CONFIG_SYS_BR0_PRELIM \
7ee41107	141	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) \| BR_PS_16 \| BR_V)
fff80975	142	#define CONFIG_SYS_BR1_PRELIM \
fff80975	143	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| BR_PS_16 \| BR_V)
d9b94f28	144
6d0f6bcf JCPV	145	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	146	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
d9b94f28	147
fff80975	148	#define CONFIG_SYS_FLASH_BANKS_LIST \
fff80975	149	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
6d0f6bcf JCPV	150	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	151	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	152	#undef CONFIG_SYS_FLASH_CHECKSUM
	153	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	154	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
d9b94f28	155
14d0a02a	156	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
d9b94f28	157
6d0f6bcf	158	#define CONFIG_SYS_FLASH_EMPTY_INFO
d9b94f28	159
867b06f4	160	#define CONFIG_HWCONFIG /* enable hwconfig */
d9b94f28 JL	161
	162	/*
	163	* SDRAM on the Local Bus
	164	*/
fff80975	165	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
b76aef60	166	#ifdef CONFIG_PHYS_64BIT
	167	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
	168	#else
fff80975	169	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
b76aef60	170	#endif
6d0f6bcf	171	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
d9b94f28 JL	172
	173	/*
	174	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	175	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
d9b94f28 JL	176	*
	177	* For BR2, need:
	178	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	179	* port-size = 32-bits = BR2[19:20] = 11
	180	* no parity checking = BR2[21:22] = 00
	181	* SDRAM for MSEL = BR2[24:26] = 011
	182	* Valid = BR[31] = 1
	183	*
f2cff6b1	184	* 0 4 8 12 16 20 24 28
d9b94f28 JL	185	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
d9b94f28 JL	186	*
6d0f6bcf	187	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
d9b94f28 JL	188	* FIXME: the top 17 bits of BR2.
	189	*/
	190
fff80975	191	#define CONFIG_SYS_BR2_PRELIM \
	192	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
	193	\| BR_PS_32 \| (3<<BR_MSEL_SHIFT) \| BR_V)
d9b94f28 JL	194
d9b94f28 JL	195	/*
6d0f6bcf	196	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
d9b94f28 JL	197	*
	198	* For OR2, need:
	199	* 64MB mask for AM, OR2[0:7] = 1111 1100
	200	* XAM, OR2[17:18] = 11
	201	* 9 columns OR2[19-21] = 010
f2cff6b1	202	* 13 rows OR2[23-25] = 100
d9b94f28 JL	203	* EAD set for extra time OR[31] = 1
d9b94f28 JL	204	*
f2cff6b1	205	* 0 4 8 12 16 20 24 28
d9b94f28 JL	206	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	207	*/
	208
6d0f6bcf	209	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
d9b94f28	210
6d0f6bcf JCPV	211	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	212	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	213	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	214	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
d9b94f28	215
d9b94f28 JL	216	/*
	217	* Common settings for all Local Bus SDRAM commands.
	218	* At run time, either BSMA1516 (for CPU 1.1)
f2cff6b1	219	* or BSMA1617 (for CPU 1.0) (old)
d9b94f28 JL	220	* is OR'ed in too.
d9b94f28 JL	221	*/
b0fe93ed KG	222	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	223	\| LSDMR_PRETOACT7 \
	224	\| LSDMR_ACTTORW7 \
	225	\| LSDMR_BL8 \
	226	\| LSDMR_WRC4 \
	227	\| LSDMR_CL3 \
	228	\| LSDMR_RFEN \
d9b94f28 JL	229	)
	230
	231	/*
	232	* The CADMUS registers are connected to CS3 on CDS.
	233	* The new memory map places CADMUS at 0xf8000000.
	234	*
	235	* For BR3, need:
	236	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	237	* port-size = 8-bits = BR[19:20] = 01
	238	* no parity checking = BR[21:22] = 00
f2cff6b1 ES	239	* GPMC for MSEL = BR[24:26] = 000
f2cff6b1 ES	240	* Valid = BR[31] = 1
d9b94f28	241	*
f2cff6b1	242	* 0 4 8 12 16 20 24 28
d9b94f28 JL	243	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	244	*
	245	* For OR3, need:
f2cff6b1	246	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
d9b94f28	247	* disable buffer ctrl OR[19] = 0
f2cff6b1 ES	248	* CSNT OR[20] = 1
	249	* ACS OR[21:22] = 11
	250	* XACS OR[23] = 1
d9b94f28	251	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
f2cff6b1 ES	252	* SETA OR[28] = 0
	253	* TRLX OR[29] = 1
	254	* EHTR OR[30] = 1
	255	* EAD extra time OR[31] = 1
d9b94f28	256	*
f2cff6b1	257	* 0 4 8 12 16 20 24 28
d9b94f28 JL	258	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	259	*/
	260
25eedb2c JL	261	#define CONFIG_FSL_CADMUS
25eedb2c JL	262
d9b94f28	263	#define CADMUS_BASE_ADDR 0xf8000000
b76aef60	264	#ifdef CONFIG_PHYS_64BIT
	265	#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
	266	#else
fff80975	267	#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
b76aef60	268	#endif
fff80975	269	#define CONFIG_SYS_BR3_PRELIM \
fff80975	270	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) \| BR_PS_8 \| BR_V)
6d0f6bcf	271	#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
d9b94f28	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	274	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	275	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
f2cff6b1	276
25ddd1fb	277	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	278	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d9b94f28	279
7bb72855	280	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
867b06f4	281	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
d9b94f28 JL	282
d9b94f28 JL	283	/* Serial Port */
6d0f6bcf JCPV	284	#define CONFIG_SYS_NS16550_SERIAL
	285	#define CONFIG_SYS_NS16550_REG_SIZE 1
	286	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
d9b94f28	287
6d0f6bcf	288	#define CONFIG_SYS_BAUDRATE_TABLE \
d9b94f28 JL	289	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
d9b94f28 JL	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	292	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
d9b94f28	293
20476726 JL	294	/*
	295	* I2C
	296	*/
2147a169	297	#if !CONFIG_IS_ENABLED(DM_I2C)
00f792e0	298	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
01d97d5f BL	299	#else
	300	#define CONFIG_SYS_SPD_BUS_NUM 0
	301	#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
	302	#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
	303	#endif
d9b94f28	304
e8d18541	305	/* EEPROM */
6d0f6bcf	306	#define CONFIG_SYS_I2C_EEPROM_CCID
e8d18541	307
d9b94f28 JL	308	/*
d9b94f28 JL	309	* General PCI
362dd830	310	* Memory space is mapped 1-1, but I/O space must start from 0.
d9b94f28	311	*/
5af0fdd8	312	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
b76aef60	313	#ifdef CONFIG_PHYS_64BIT
	314	#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
	315	#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
	316	#else
10795f42	317	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	318	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
b76aef60	319	#endif
6d0f6bcf	320	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	321	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	322	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
b76aef60	323	#ifdef CONFIG_PHYS_64BIT
	324	#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
	325	#else
6d0f6bcf	326	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
b76aef60	327	#endif
6d0f6bcf	328	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
d9b94f28	329
f2cff6b1	330	#ifdef CONFIG_PCIE1
5af0fdd8	331	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
b76aef60	332	#ifdef CONFIG_PHYS_64BIT
b76aef60	333	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
b76aef60	334	#else
5af0fdd8	335	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
b76aef60	336	#endif
aca5f018	337	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
b76aef60	338	#ifdef CONFIG_PHYS_64BIT
	339	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
	340	#else
6d0f6bcf	341	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
b76aef60	342	#endif
f2cff6b1	343	#endif
d9b94f28	344
41fb7e0f ZR	345	/*
	346	* RapidIO MMU
	347	*/
fff80975	348	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
b76aef60	349	#ifdef CONFIG_PHYS_64BIT
	350	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
	351	#else
fff80975	352	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
b76aef60	353	#endif
8b47d7ec	354	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
d9b94f28	355
7f3f2bd2 RV	356	#ifdef CONFIG_LEGACY
	357	#define BRIDGE_ID 17
	358	#define VIA_ID 2
	359	#else
	360	#define BRIDGE_ID 28
	361	#define VIA_ID 4
	362	#endif
	363
d9b94f28	364	#if defined(CONFIG_PCI)
867b06f4	365	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
d9b94f28 JL	366	#endif /* CONFIG_PCI */
d9b94f28 JL	367
d9b94f28 JL	368	#if defined(CONFIG_TSEC_ENET)
d9b94f28 JL	369
255a3577 KP	370	#define CONFIG_TSEC1 1
	371	#define CONFIG_TSEC1_NAME "eTSEC0"
	372	#define CONFIG_TSEC2 1
	373	#define CONFIG_TSEC2_NAME "eTSEC1"
	374	#define CONFIG_TSEC3 1
	375	#define CONFIG_TSEC3_NAME "eTSEC2"
f2cff6b1	376	#define CONFIG_TSEC4
255a3577	377	#define CONFIG_TSEC4_NAME "eTSEC3"
d9b94f28 JL	378	#undef CONFIG_MPC85XX_FEC
	379
	380	#define TSEC1_PHY_ADDR 0
	381	#define TSEC2_PHY_ADDR 1
	382	#define TSEC3_PHY_ADDR 2
	383	#define TSEC4_PHY_ADDR 3
d9b94f28 JL	384
	385	#define TSEC1_PHYIDX 0
	386	#define TSEC2_PHYIDX 0
	387	#define TSEC3_PHYIDX 0
	388	#define TSEC4_PHYIDX 0
3a79013e AF	389	#define TSEC1_FLAGS TSEC_GIGABIT
	390	#define TSEC2_FLAGS TSEC_GIGABIT
	391	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	392	#define TSEC4_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
d9b94f28 JL	393
	394	/* Options are: eTSEC[0-3] */
	395	#define CONFIG_ETHPRIME "eTSEC0"
d9b94f28 JL	396	#endif /* CONFIG_TSEC_ENET */
	397
	398	/*
	399	* Environment
	400	*/
d9b94f28 JL	401
d9b94f28 JL	402	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	403	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d9b94f28	404
659e2f67 JL	405	/*
	406	* BOOTP options
	407	*/
	408	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	409
d9b94f28 JL	410	#undef CONFIG_WATCHDOG /* watchdog disabled */
	411
	412	/*
	413	* Miscellaneous configurable options
	414	*/
6d0f6bcf	415	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
d9b94f28 JL	416
	417	/*
	418	* For booting Linux, the board info and command line data
a832ac41	419	* have to be in the first 64 MB of memory, since this is
d9b94f28 JL	420	* the maximum mapped by the Linux kernel during initialization.
d9b94f28 JL	421	*/
a832ac41 KG	422	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	423	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
d9b94f28	424
2835e518	425	#if defined(CONFIG_CMD_KGDB)
d9b94f28	426	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
d9b94f28 JL	427	#endif
	428
	429	/*
	430	* Environment Configuration
	431	*/
d9b94f28	432	#if defined(CONFIG_TSEC_ENET)
10327dc5	433	#define CONFIG_HAS_ETH0
d9b94f28	434	#define CONFIG_HAS_ETH1
d9b94f28	435	#define CONFIG_HAS_ETH2
09f3e09e	436	#define CONFIG_HAS_ETH3
d9b94f28 JL	437	#endif
d9b94f28 JL	438
f2cff6b1	439	#define CONFIG_IPADDR 192.168.1.253
d9b94f28	440
5bc0543d	441	#define CONFIG_HOSTNAME "unknown"
8b3637c6	442	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	443	#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
f2cff6b1	444	#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
d9b94f28	445
f2cff6b1	446	#define CONFIG_SERVERIP 192.168.1.1
d9b94f28	447	#define CONFIG_GATEWAYIP 192.168.1.1
f2cff6b1	448	#define CONFIG_NETMASK 255.255.255.0
d9b94f28	449
f2cff6b1	450	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
d9b94f28	451
867b06f4	452	#define CONFIG_EXTRA_ENV_SETTINGS \
	453	"hwconfig=fsl_ddr:ecc=off\0" \
	454	"netdev=eth0\0" \
5368c55d	455	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
867b06f4	456	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	457	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	458	" +$filesize; " \
	459	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	460	" +$filesize; " \
	461	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	462	" $filesize; " \
	463	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	464	" +$filesize; " \
	465	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	466	" $filesize\0" \
867b06f4	467	"consoledev=ttyS1\0" \
	468	"ramdiskaddr=2000000\0" \
	469	"ramdiskfile=ramdisk.uboot\0" \
b24a4f62	470	"fdtaddr=1e00000\0" \
867b06f4	471	"fdtfile=mpc8548cds.dtb\0"
f2cff6b1 ES	472
	473	#define CONFIG_NFSBOOTCOMMAND \
	474	"setenv bootargs root=/dev/nfs rw " \
	475	"nfsroot=$serverip:$rootpath " \
d9b94f28	476	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
f2cff6b1 ES	477	"console=$consoledev,$baudrate $othbootargs;" \
f2cff6b1 ES	478	"tftp $loadaddr $bootfile;" \
4bf4abb8 ES	479	"tftp $fdtaddr $fdtfile;" \
4bf4abb8 ES	480	"bootm $loadaddr - $fdtaddr"
8272dc2f	481
d9b94f28	482	#define CONFIG_RAMBOOTCOMMAND \
f2cff6b1 ES	483	"setenv bootargs root=/dev/ram rw " \
	484	"console=$consoledev,$baudrate $othbootargs;" \
	485	"tftp $ramdiskaddr $ramdiskfile;" \
	486	"tftp $loadaddr $bootfile;" \
4bf4abb8 ES	487	"tftp $fdtaddr $fdtfile;" \
4bf4abb8 ES	488	"bootm $loadaddr $ramdiskaddr $fdtaddr"
f2cff6b1 ES	489
f2cff6b1 ES	490	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
d9b94f28 JL	491
d9b94f28 JL	492	#endif /* __CONFIG_H */