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f4863a7a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Masami Komiya <[email protected]> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /* | |
22 | * Config header file for TANBAC TB0229 board using an VR4131 CPU module | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
28 | #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ | |
29 | #define CONFIG_TB0229 1 /* on a TB0229 Board */ | |
30 | ||
31 | #ifndef CPU_CLOCK_RATE | |
32 | #define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ | |
33 | #endif | |
34 | #define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ | |
35 | ||
36 | #define CONFIG_CONS_INDEX 1 | |
37 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
38 | ||
39 | #define CONFIG_BAUDRATE 115200 | |
40 | ||
6d0f6bcf | 41 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
f4863a7a WD |
42 | |
43 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
44 | ||
45 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 WD |
46 | "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \ |
47 | "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \ | |
48 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
49 | "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \ | |
f4863a7a WD |
50 | "echo" |
51 | ||
52 | #undef CONFIG_BOOTARGS | |
53 | ||
54 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
55 | "netboot=dhcp;tftp;run netargs; bootm\0" \ | |
56 | "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ | |
57 | "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ | |
fe126d8b WD |
58 | "addmisc=setenv bootargs ${bootargs} " \ |
59 | "console=ttyS0,${baudrate} " \ | |
f4863a7a WD |
60 | "read-only=readonly\0" \ |
61 | "netargs=run nfsargs addmisc\0" \ | |
62 | "flash_nfs=run nfsargs addmisc;" \ | |
fe126d8b | 63 | "bootm ${kernel_addr}\0" \ |
f4863a7a | 64 | "flash_local=run localargs addmisc;" \ |
fe126d8b | 65 | "bootm ${kernel_addr}\0" \ |
f4863a7a WD |
66 | "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ |
67 | "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ | |
68 | "run addmisc;" \ | |
69 | "bootm 80400000 80600000\0" \ | |
70 | "rootpath=/export/miniroot-mipsel\0" \ | |
71 | "autoload=no\0" \ | |
72 | "kernel_addr=BFC60000\0" \ | |
73 | "ramdisk_addr=B0100000\0" \ | |
74 | "u-boot=u-boot.bin\0" \ | |
75 | "bootfile=uImage\0" \ | |
fe126d8b WD |
76 | "load=dhcp;tftp 80400000 ${u-boot}\0" \ |
77 | "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ | |
f4863a7a WD |
78 | "update_uboot=run load;" \ |
79 | "protect off BFC00000 BFC3FFFF;" \ | |
80 | "erase BFC00000 BFC3FFFF;" \ | |
fe126d8b | 81 | "cp.b 80400000 BFC00000 ${filesize}\0" \ |
f4863a7a WD |
82 | "update_kernel=run load_kernel;" \ |
83 | "erase BFC60000 BFD5FFFF;" \ | |
fe126d8b | 84 | "cp.b 80400000 BFC60000 ${filesize}\0" \ |
f4863a7a WD |
85 | "initenv=erase bfc40000 bfc5ffff\0" \ |
86 | "" | |
cd37d9e6 | 87 | /*#define CONFIG_BOOTCOMMAND "run flash_local" */ |
f4863a7a WD |
88 | #define CONFIG_BOOTCOMMAND "run netboot" |
89 | ||
6c18eb98 | 90 | |
079a136c JL |
91 | /* |
92 | * BOOTP options | |
93 | */ | |
94 | #define CONFIG_BOOTP_BOOTFILESIZE | |
95 | #define CONFIG_BOOTP_BOOTPATH | |
96 | #define CONFIG_BOOTP_GATEWAY | |
97 | #define CONFIG_BOOTP_HOSTNAME | |
98 | ||
99 | ||
6c18eb98 JL |
100 | /* |
101 | * Command line configuration. | |
102 | */ | |
103 | #include <config_cmd_default.h> | |
104 | ||
105 | #define CONFIG_CMD_ASKENV | |
106 | #define CONFIG_CMD_DHCP | |
107 | #define CONFIG_CMD_PING | |
108 | #define CONFIG_CMD_PCI | |
109 | #define CONFIG_CMD_ELF | |
110 | ||
f4863a7a WD |
111 | |
112 | /* | |
113 | * Miscellaneous configurable options | |
114 | */ | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
116 | #define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ | |
117 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
118 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
119 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
f4863a7a | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
f4863a7a | 122 | |
6d0f6bcf | 123 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
f4863a7a | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) |
a55d4817 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_HZ 1000 |
f4863a7a | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
f4863a7a | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ |
f4863a7a | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
134 | #define CONFIG_SYS_MEMTEST_END 0x80800000 | |
f4863a7a WD |
135 | |
136 | /*----------------------------------------------------------------------- | |
137 | * FLASH and environment organization | |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
140 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
f4863a7a WD |
141 | |
142 | #define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ | |
143 | ||
144 | /* The following #defines are needed to get flash environment right */ | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
146 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) | |
f4863a7a | 147 | |
6d0f6bcf | 148 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
f4863a7a | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
f4863a7a WD |
151 | |
152 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
154 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
f4863a7a | 155 | |
5a1aceb0 | 156 | #define CONFIG_ENV_IS_IN_FLASH 1 |
f4863a7a WD |
157 | |
158 | /* Address and size of Primary Environment Sector */ | |
0e8d1586 JCPV |
159 | #define CONFIG_ENV_ADDR 0xBFC40000 |
160 | #define CONFIG_ENV_SIZE 0x20000 | |
f4863a7a | 161 | |
6d0f6bcf | 162 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
f4863a7a WD |
163 | |
164 | #define CONFIG_NR_DRAM_BANKS 1 | |
165 | ||
166 | /*----------------------------------------------------------------------- | |
167 | * Cache Configuration | |
168 | */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
170 | #define CONFIG_SYS_ICACHE_SIZE 16384 | |
171 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
f4863a7a WD |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * Serial Configuration | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_NS16550 |
177 | #define CONFIG_SYS_NS16550_SERIAL | |
178 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
179 | #define CONFIG_SYS_NS16550_CLK 18432000 | |
180 | #define CONFIG_SYS_NS16550_COM1 0xaf000800 | |
f4863a7a WD |
181 | |
182 | /*----------------------------------------------------------------------- | |
183 | * PCI stuff | |
184 | */ | |
185 | #define CONFIG_PCI | |
186 | #define CONFIG_PCI_PNP | |
187 | #define CONFIG_NET_MULTI | |
188 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 189 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
f4863a7a WD |
190 | |
191 | #define CONFIG_RTL8139 | |
192 | ||
193 | #endif /* __CONFIG_H */ |