[J-u-boot.git] / include / configs / cmc_pu2.h

/*
 * 2004-2005 Gary Jennejohn <[email protected]>
 *
 * Configuration settings for the CMC PU2 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board		*/
#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
#define USE_920T_MMU		1

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
/* flash */
#define MC_PUIA_VAL	0x00000000
#define MC_PUP_VAL	0x00000000
#define MC_PUER_VAL	0x00000000
#define MC_ASR_VAL	0x00000000
#define MC_AASR_VAL	0x00000000
#define EBI_CFGR_VAL	0x00000000
#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */

/* sdram */
#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL	0x00000000
#define PIOC_PDR_VAL	0xFFFF0000
#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
#define SDRAM		0x20000000 /* address of the SDRAM */
#define SDRAM1		0x20000080 /* address of the SDRAM */
#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL	0x00000002 /* Precharge All */
#define SDRC_MR_VAL1	0x00000004 /* refresh */
#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

#define CONFIG_BAUDRATE		9600

/*
 * Hardware drivers
 */

/* define one of these to choose the DBGU, USART0  or USART1 as console */
#undef CONFIG_DBGU
#define CONFIG_USART0
#undef CONFIG_USART1

#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/

#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */

#define CONFIG_HARD_I2C

#ifdef CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		0	/* not used */
#define CONFIG_SYS_I2C_SLAVE		0	/* not used */
#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
#define CONFIG_SYS_I2C_RTC_ADDR	0x32
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
#else
#define CONFIG_TIMESTAMP
#endif
/* still about 20 kB free with this defined */
#define CONFIG_SYS_LONGHELP

#define CONFIG_BOOTDELAY      1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC

#if defined(CONFIG_HARD_I2C)
    #define CONFIG_CMD_DATE
    #define CONFIG_CMD_EEPROM
    #define CONFIG_CMD_I2C
#endif


#define CONFIG_SYS_LONGHELP

#define AT91_SMART_MEDIA_ALE	(1 << 22)	/* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE	(1 << 21)	/* our CLE is AD21 */

#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE		0x1000000	/* 16 megs */

#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144

#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_AT91C_USE_RMII

#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_FLASH_ERASE_TOUT		(11 * CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT		( 2 * CONFIG_SYS_HZ)	/* Timeout for Flash Write */

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_OFFSET			0x20000		/* after u-boot.bin */
#define CONFIG_ENV_SECT_SIZE		(64 << 10)	/* sectors are 64 kB */
#define CONFIG_ENV_SIZE			(16 << 10)	/* Use only 16 kB */

#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }

#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS		32		/* max number of command args */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */

#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
						/* AT91C_TC_TIMER_DIV1_CLOCK */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS	\
	"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
		"addmtd;bootm\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw " \
		"nfsroot=${serverip}:${rootpath}\0" \
	"net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
		"addcons addmtd; bootm\0" \
	"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
	"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
		"${hostname}::off\0" \
	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
		"64k(environment),768k(linux),4096k(root),-\0" \
	"load=tftp ${loadaddr} ${loadfile}\0" \
	"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
		"cp.b ${loadaddr} 10000000 ${filesize};" \
		"protect on 10000000 1001ffff\0" \
	"updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
		"cp.b ${loadaddr} 10030000 ${filesize}\0" \
	"updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
		"cp.b ${loadaddr} 100f0000 ${filesize}\0" \
	"updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
		"cp.b ${loadaddr} 104f0000 ${filesize}\0" \
	"cramfsimage=cramfs_cmc-pu2.img\0" \
	"jffsimage=jffs2_cmc-pu2.img\0" \
	"loadfile=u-boot_cmc-pu2.bin\0" \
	"bootfile=uImage_cmc-pu2\0" \
	"loadaddr=0x20800000\0" \
	"hostname=CMC-TC-PU2\0" \
	"bootcmd=run dhcp_start;run flash_cramfs\0" \
	"autoload=n\0" \
	"dhcp_start=echo no DHCP\0" \
	"ipaddr=192.168.0.190\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
2cbe571a	1	/*
414eec35	2	* 2004-2005 Gary Jennejohn <[email protected]>
2cbe571a	3	*
9d5028c2	4	* Configuration settings for the CMC PU2 board.
2cbe571a WD	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
45ea3fca	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2cbe571a WD	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
2cbe571a	28	/* ARM asynchronous clock */
df3c7c8f	29	#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
101e8dfa	30	#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
2cbe571a WD	31
	32	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	33
a85f9f21 WD	34	#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
a85f9f21 WD	35	#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
a85f9f21 WD	36	#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
	37	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	38	#define USE_920T_MMU 1
	39
2cbe571a WD	40	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	41	#define CONFIG_SETUP_MEMORY_TAGS 1
	42	#define CONFIG_INITRD_TAG 1
	43
8aa1a2d1	44	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
6d0f6bcf	45	#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
ef2807c6 WD	46	/* flash */
	47	#define MC_PUIA_VAL 0x00000000
	48	#define MC_PUP_VAL 0x00000000
	49	#define MC_PUER_VAL 0x00000000
	50	#define MC_ASR_VAL 0x00000000
	51	#define MC_AASR_VAL 0x00000000
	52	#define EBI_CFGR_VAL 0x00000000
480ed1de	53	#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
ef2807c6 WD	54
ef2807c6 WD	55	/* clocks */
df3c7c8f	56	#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
ef2807c6 WD	57	#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
	58	#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
	59
	60	/* sdram */
	61	#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
	62	#define PIOC_BSR_VAL 0x00000000
	63	#define PIOC_PDR_VAL 0xFFFF0000
	64	#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	65	#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
	66	#define SDRAM 0x20000000 /* address of the SDRAM */
	67	#define SDRAM1 0x20000080 /* address of the SDRAM */
	68	#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
	69	#define SDRC_MR_VAL 0x00000002 /* Precharge All */
	70	#define SDRC_MR_VAL1 0x00000004 /* refresh */
	71	#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	72	#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	73	#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
8aa1a2d1	74	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
ef2807c6	75
2cbe571a WD	76	/*
	77	* Size of malloc() pool
	78	*/
6d0f6bcf JCPV	79	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
6d0f6bcf JCPV	80	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
2cbe571a	81
45ea3fca	82	#define CONFIG_BAUDRATE 9600
2cbe571a	83
2cbe571a WD	84	/*
	85	* Hardware drivers
	86	*/
	87
	88	/* define one of these to choose the DBGU, USART0 or USART1 as console */
	89	#undef CONFIG_DBGU
9d5028c2 WD	90	#define CONFIG_USART0
9d5028c2 WD	91	#undef CONFIG_USART1
2cbe571a WD	92
	93	#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
	94
	95	#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
	96
9d5028c2	97	#define CONFIG_HARD_I2C
2cbe571a WD	98
2cbe571a WD	99	#ifdef CONFIG_HARD_I2C
6d0f6bcf JCPV	100	#define CONFIG_SYS_I2C_SPEED 0 /* not used */
6d0f6bcf JCPV	101	#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
45ea3fca	102	#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
6d0f6bcf JCPV	103	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
	104	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	105	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	106	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
37e4f24b JL	107	#else
37e4f24b JL	108	#define CONFIG_TIMESTAMP
2cbe571a	109	#endif
ed54e621	110	/* still about 20 kB free with this defined */
6d0f6bcf	111	#define CONFIG_SYS_LONGHELP
2cbe571a	112
1ac7e17e	113	#define CONFIG_BOOTDELAY 1
2cbe571a	114
37e4f24b	115
80ff4f99 JL	116	/*
	117	* BOOTP options
	118	*/
	119	#define CONFIG_BOOTP_BOOTFILESIZE
	120	#define CONFIG_BOOTP_BOOTPATH
	121	#define CONFIG_BOOTP_GATEWAY
	122	#define CONFIG_BOOTP_HOSTNAME
	123
	124
37e4f24b JL	125	/*
	126	* Command line configuration.
	127	*/
	128	#include <config_cmd_default.h>
	129
	130	#define CONFIG_CMD_DHCP
	131	#define CONFIG_CMD_NFS
	132	#define CONFIG_CMD_SNTP
	133
	134	#undef CONFIG_CMD_FPGA
	135	#undef CONFIG_CMD_MISC
	136
	137	#if defined(CONFIG_HARD_I2C)
	138	#define CONFIG_CMD_DATE
	139	#define CONFIG_CMD_EEPROM
	140	#define CONFIG_CMD_I2C
2cbe571a WD	141	#endif
2cbe571a WD	142
37e4f24b	143
6d0f6bcf	144	#define CONFIG_SYS_LONGHELP
2cbe571a	145
45ea3fca WD	146	#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
45ea3fca WD	147	#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
2cbe571a	148
45ea3fca WD	149	#define CONFIG_NR_DRAM_BANKS 1
45ea3fca WD	150	#define PHYS_SDRAM 0x20000000
2c5260f7	151	#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
2cbe571a	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
6d0f6bcf JCPV	154	#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
2cbe571a WD	155
	156	#define CONFIG_DRIVER_ETHER
	157	#define CONFIG_NET_RETRY_COUNT 20
	158	#define CONFIG_AT91C_USE_RMII
	159
6d0f6bcf JCPV	160	#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
	161	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
	162	#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
	163	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
	164	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
2cbe571a WD	165
2cbe571a WD	166	#define PHYS_FLASH_1 0x10000000
9d5028c2	167	#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
6d0f6bcf JCPV	168	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	169	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	170	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	171	#define CONFIG_SYS_MAX_FLASH_SECT 256
	172	#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
	173	#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
2cbe571a	174
5a1aceb0	175	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	176	#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
	177	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
	178	#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */
2cbe571a	179
6d0f6bcf	180	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
2cbe571a	181
6d0f6bcf	182	#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
2cbe571a	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	185	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	186	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	187	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
2cbe571a	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_HZ 1000
6d0f6bcf JCPV	190	#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
59acc296	191	/* AT91C_TC_TIMER_DIV1_CLOCK */
2cbe571a WD	192
	193	#define CONFIG_STACKSIZE (321024) / regular stack */
	194
	195	#ifdef CONFIG_USE_IRQ
	196	#error CONFIG_USE_IRQ not supported
	197	#endif
	198
3dd7f0f0	199	#define CONFIG_EXTRA_ENV_SETTINGS \
fe126d8b	200	"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
3dd7f0f0 WD	201	"addmtd;bootm\0" \
3dd7f0f0 WD	202	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b WD	203	"nfsroot=${serverip}:${rootpath}\0" \
fe126d8b WD	204	"net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
3dd7f0f0 WD	205	"addcons addmtd; bootm\0" \
	206	"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
	207	"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
fe126d8b WD	208	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
	209	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
	210	"${hostname}::off\0" \
	211	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	212	"addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
3dd7f0f0	213	"64k(environment),768k(linux),4096k(root),-\0" \
fe126d8b	214	"load=tftp ${loadaddr} ${loadfile}\0" \
3dd7f0f0	215	"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
fe126d8b	216	"cp.b ${loadaddr} 10000000 ${filesize};" \
3dd7f0f0	217	"protect on 10000000 1001ffff\0" \
fe126d8b WD	218	"updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
	219	"cp.b ${loadaddr} 10030000 ${filesize}\0" \
	220	"updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
	221	"cp.b ${loadaddr} 100f0000 ${filesize}\0" \
	222	"updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
	223	"cp.b ${loadaddr} 104f0000 ${filesize}\0" \
3dd7f0f0 WD	224	"cramfsimage=cramfs_cmc-pu2.img\0" \
	225	"jffsimage=jffs2_cmc-pu2.img\0" \
	226	"loadfile=u-boot_cmc-pu2.bin\0" \
	227	"bootfile=uImage_cmc-pu2\0" \
	228	"loadaddr=0x20800000\0" \
	229	"hostname=CMC-TC-PU2\0" \
	230	"bootcmd=run dhcp_start;run flash_cramfs\0" \
	231	"autoload=n\0" \
	232	"dhcp_start=echo no DHCP\0" \
	233	"ipaddr=192.168.0.190\0"
45ea3fca	234	#endif /* __CONFIG_H */