projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 62534beb SR |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Stefan Roese, DENX Software Engineering, [email protected]. | |
| 4 | * | |
| 5 | * (C) Copyright 2006 | |
| 6 | * DAVE Srl <www.dave-tech.it> | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | #ifndef _SDRAM_H_ | |
| 28 | #define _SDRAM_H_ | |
| 29 | ||
| 30 | #include <config.h> | |
| 31 | ||
| 62534beb SR |
32 | #define ONE_BILLION 1000000000 |
| 33 | ||
| 34 | struct sdram_conf_s { | |
| 35 | unsigned long size; | |
| 36 | int rows; | |
| 37 | unsigned long reg; | |
| 38 | }; | |
| 39 | ||
| 40 | typedef struct sdram_conf_s sdram_conf_t; | |
| 41 | ||
| 42 | /* Bitfields offsets */ | |
| 43 | #define SDRAM0_TR_CASL (31 - 8) | |
| 44 | #define SDRAM0_TR_PTA (31 - 13) | |
| 45 | #define SDRAM0_TR_CTP (31 - 15) | |
| 46 | #define SDRAM0_TR_LDF (31 - 17) | |
| 47 | #define SDRAM0_TR_RFTA (31 - 29) | |
| 48 | #define SDRAM0_TR_RCD (31 - 31) | |
| 49 | ||
| 6d0f6bcf | 50 | #ifdef CONFIG_SYS_SDRAM_CL |
| 62534beb | 51 | /* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */ |
| 6d0f6bcf JCPV |
52 | #define CONFIG_SYS_SDRAM_CASL CONFIG_SYS_SDRAM_CL |
| 53 | #define CONFIG_SYS_SDRAM_PTA CONFIG_SYS_SDRAM_tRP | |
| 54 | #define CONFIG_SYS_SDRAM_CTP (CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP) | |
| 55 | #define CONFIG_SYS_SDRAM_LDF 0 | |
| 56 | #ifdef CONFIG_SYS_SDRAM_tRFC | |
| 57 | #define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRFC | |
| 62534beb | 58 | #else |
| 6d0f6bcf | 59 | #define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRC |
| 62534beb | 60 | #endif |
| 6d0f6bcf JCPV |
61 | #define CONFIG_SYS_SDRAM_RCD CONFIG_SYS_SDRAM_tRCD |
| 62 | #endif /* #ifdef CONFIG_SYS_SDRAM_CL */ | |
| 62534beb SR |
63 | |
| 64 | /* | |
| 65 | * Some defines for the 440 DDR controller | |
| 66 | */ | |
| 67 | #define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */ | |
| 68 | #define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/ | |
| 69 | #define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */ | |
| 70 | #define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */ | |
| 71 | #define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */ | |
| 72 | #define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */ | |
| 73 | #define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */ | |
| 74 | #define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */ | |
| 75 | ||
| 76 | #endif |