[J-u-boot.git] / cpu / at32ap / cpu.c

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <command.h>

#include <asm/io.h>
#include <asm/sections.h>
#include <asm/sysreg.h>

#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>

#include "hsmc3.h"

/* Sanity checks */
#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB)		\
	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA)	\
	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
#endif
#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
# error Invalid PLL multiplier and/or divider
#endif

DECLARE_GLOBAL_DATA_PTR;

int cpu_init(void)
{
	extern void _evba(void);

	gd->cpu_hz = CONFIG_SYS_OSC0_HZ;

	/* TODO: Move somewhere else, but needs to be run before we
	 * increase the clock frequency. */
	hsmc3_writel(MODE0, 0x00031103);
	hsmc3_writel(CYCLE0, 0x000c000d);
	hsmc3_writel(PULSE0, 0x0b0a0906);
	hsmc3_writel(SETUP0, 0x00010002);

	clk_init();

	/* Update the CPU speed according to the PLL configuration */
	gd->cpu_hz = get_cpu_clk_rate();

	/* Set up the exception handler table and enable exceptions */
	sysreg_write(EVBA, (unsigned long)&_evba);
	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));

	if(gclk_init)
		gclk_init();

	return 0;
}

void prepare_to_boot(void)
{
	/* Flush both caches and the write buffer */
	asm volatile("cache  %0[4], 010\n\t"
		     "cache  %0[0], 000\n\t"
		     "sync   0" : : "r"(0) : "memory");
}

int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	/* This will reset the CPU core, caches, MMU and all internal busses */
	__builtin_mtdr(8, 1 << 13);	/* set DC:DBE */
	__builtin_mtdr(8, 1 << 30);	/* set DC:RES */

	/* Flush the pipeline before we declare it a failure */
	asm volatile("sub   pc, pc, -4");

	return -1;
}
Commit	Line	Data
72a087e0 WD	1	/*
	2	* Copyright (C) 2005-2006 Atmel Corporation
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22	#include <common.h>
	23	#include <command.h>
	24
	25	#include <asm/io.h>
	26	#include <asm/sections.h>
	27	#include <asm/sysreg.h>
	28
df548d3c	29	#include <asm/arch/clk.h>
72a087e0	30	#include <asm/arch/memory-map.h>
72a087e0 WD	31
72a087e0 WD	32	#include "hsmc3.h"
df548d3c HS	33
df548d3c HS	34	/* Sanity checks */
6d0f6bcf JCPV	35	#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
	36	\|\| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
	37	\|\| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
df548d3c HS	38	# error Constraint fCPU >= fHSB >= fPB{A,B} violated
df548d3c HS	39	#endif
6d0f6bcf	40	#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) \|\| (CONFIG_SYS_PLL0_DIV < 1))
df548d3c HS	41	# error Invalid PLL multiplier and/or divider
df548d3c HS	42	#endif
72a087e0 WD	43
	44	DECLARE_GLOBAL_DATA_PTR;
	45
	46	int cpu_init(void)
	47	{
72a087e0	48	extern void _evba(void);
72a087e0	49
6d0f6bcf	50	gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
72a087e0	51
df548d3c HS	52	/* TODO: Move somewhere else, but needs to be run before we
	53	* increase the clock frequency. */
	54	hsmc3_writel(MODE0, 0x00031103);
	55	hsmc3_writel(CYCLE0, 0x000c000d);
	56	hsmc3_writel(PULSE0, 0x0b0a0906);
	57	hsmc3_writel(SETUP0, 0x00010002);
72a087e0	58
3ace2527 HS	59	clk_init();
	60
	61	/* Update the CPU speed according to the PLL configuration */
	62	gd->cpu_hz = get_cpu_clk_rate();
72a087e0	63
3ace2527	64	/* Set up the exception handler table and enable exceptions */
72a087e0 WD	65	sysreg_write(EVBA, (unsigned long)&_evba);
72a087e0 WD	66	asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
72a087e0	67
5c374c9e JM	68	if(gclk_init)
	69	gclk_init();
	70
72a087e0 WD	71	return 0;
	72	}
	73
	74	void prepare_to_boot(void)
	75	{
	76	/* Flush both caches and the write buffer */
	77	asm volatile("cache %0[4], 010\n\t"
	78	"cache %0[0], 000\n\t"
	79	"sync 0" : : "r"(0) : "memory");
	80	}
	81
	82	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	83	{
	84	/* This will reset the CPU core, caches, MMU and all internal busses */
	85	__builtin_mtdr(8, 1 << 13); /* set DC:DBE */
	86	__builtin_mtdr(8, 1 << 30); /* set DC:RES */
	87
	88	/* Flush the pipeline before we declare it a failure */
	89	asm volatile("sub pc, pc, -4");
	90
	91	return -1;
	92	}