[J-u-boot.git] / board / trizepsiv / lowlevel_init.S

/*
 * This was originally from the Lubbock u-boot port.
 *
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

/* wait for coprocessor write complete */
   .macro CPWAIT reg
   mrc	p15,0,\reg,c2,c0,0
   mov	\reg,\reg
   sub	pc,pc,#4
   .endm


/*
 *	Memory setup
 */

.globl lowlevel_init
lowlevel_init:

	/* Set up GPIO pins first ----------------------------------------- */

	ldr		r0,	=GPSR0
	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR1
	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR2
	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR3
	ldr		r1,	=CONFIG_SYS_GPSR3_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR0
	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR1
	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR2
	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR3
	ldr		r1,	=CONFIG_SYS_GPCR3_VAL
	str		r1,   [r0]

	ldr		r0,	=GRER0
	ldr		r1,	=CONFIG_SYS_GRER0_VAL
	str		r1,   [r0]

	ldr		r0,	=GRER1
	ldr		r1,	=CONFIG_SYS_GRER1_VAL
	str		r1,   [r0]

	ldr		r0,	=GRER2
	ldr		r1,	=CONFIG_SYS_GRER2_VAL
	str		r1,   [r0]

	ldr		r0,	=GRER3
	ldr		r1,	=CONFIG_SYS_GRER3_VAL
	str		r1,   [r0]

	ldr		r0,	=GFER0
	ldr		r1,	=CONFIG_SYS_GFER0_VAL
	str		r1,   [r0]

	ldr		r0,	=GFER1
	ldr		r1,	=CONFIG_SYS_GFER1_VAL
	str		r1,   [r0]

	ldr		r0,	=GFER2
	ldr		r1,	=CONFIG_SYS_GFER2_VAL
	str		r1,   [r0]

	ldr		r0,	=GFER3
	ldr		r1,	=CONFIG_SYS_GFER3_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR0
	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR1
	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR2
	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR3
	ldr		r1,	=CONFIG_SYS_GPDR3_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_L
	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_U
	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_L
	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_U
	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_L
	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_U
	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR3_L
	ldr		r1,	=CONFIG_SYS_GAFR3_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR3_U
	ldr		r1,	=CONFIG_SYS_GAFR3_U_VAL
	str		r1,   [r0]

	ldr		r0,	=PSSR		/* enable GPIO pins */
	ldr		r1,	=CONFIG_SYS_PSSR_VAL
	str		r1,   [r0]

	/* ---------------------------------------------------------------- */
	/* Enable memory interface					    */
	/*								    */
	/* The sequence below is based on the recommended init steps	    */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.							    */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
	/*	   clocks to settle. Only necessary after hard reset...	    */
	/*	   FIXME: can be optimized later			    */
	/* ---------------------------------------------------------------- */

	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
	mov r2, #0
	str r2, [r3]
	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty	    */
1:
	ldr r2, [r3]
	cmp r4, r2
	bgt 1b

mem_init:

	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller	    */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type			    */

	/* MSC0: nCS(0,1)						    */
	ldr	r2,   =CONFIG_SYS_MSC0_VAL
	str	r2,   [r1, #MSC0_OFFSET]
	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
						/* that data latches	    */
	/* MSC1: nCS(2,3)						    */
	ldr	r2,  =CONFIG_SYS_MSC1_VAL
	str	r2,  [r1, #MSC1_OFFSET]
	ldr	r2,  [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)						    */
	ldr	r2,  =CONFIG_SYS_MSC2_VAL
	str	r2,  [r1, #MSC2_OFFSET]
	ldr	r2,  [r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface				    */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register				    */
	ldr	r2,  =CONFIG_SYS_MECR_VAL
	str	r2,  [r1, #MECR_OFFSET]
	ldr	r2,	[r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing				    */
	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
	str	r2,  [r1, #MCMEM0_OFFSET]
	ldr	r2,	[r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing				    */
	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
	str	r2,  [r1, #MCMEM1_OFFSET]
	ldr	r2,	[r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
	str	r2,  [r1, #MCATT0_OFFSET]
	ldr	r2,	[r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
	str	r2,  [r1, #MCATT1_OFFSET]
	ldr	r2,	[r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
	str	r2,  [r1, #MCIO0_OFFSET]
	ldr	r2,	[r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
	str	r2,  [r1, #MCIO1_OFFSET]
	ldr	r2,	[r1, #MCIO1_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
	/* ---------------------------------------------------------------- */
	ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
	str	r2,  [r1, #FLYCNFG_OFFSET]
	str	r2,	[r1, #FLYCNFG_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
	/* this to power on defaults + DRI field.			    */

	ldr	r4,	[r1, #MDREFR_OFFSET]
	ldr	r2,	=0xFFF
	bic	r4,	r4, r2

	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
	and	r3,	r3,  r2

	orr	r4,	r4, r3
	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */

	orr	r4,  r4, #MDREFR_K0RUN
	orr	r4,  r4, #MDREFR_K0DB4
	orr	r4,  r4, #MDREFR_K0FREE
	orr	r4,  r4, #MDREFR_K0DB2
	orr	r4,  r4, #MDREFR_K1DB2
	bic	r4,  r4, #MDREFR_K1FREE
	bic	r4,  r4, #MDREFR_K2FREE

	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
	ldr	r4,  [r1, #MDREFR_OFFSET]

	/* Note: preserve the mdrefr value in r4			    */


	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits		    */

	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.						    */

	ldr	r2,  =CONFIG_SYS_SXCNFG_VAL
	str	r2,  [r1, #SXCNFG_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM					    */
	/* ---------------------------------------------------------------- */

	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)

	orr	r4, r4, #MDREFR_K1RUN
	bic	r4, r4, #MDREFR_K2DB2
	str	r4, [r1, #MDREFR_OFFSET]
	ldr	r4, [r1, #MDREFR_OFFSET]

	bic	r4, r4, #MDREFR_SLFRSH
	str	r4, [r1, #MDREFR_OFFSET]
	ldr	r4, [r1, #MDREFR_OFFSET]

	orr	r4, r4, #MDREFR_E1PIN
	str	r4, [r1, #MDREFR_OFFSET]
	ldr	r4, [r1, #MDREFR_OFFSET]

	nop
	nop


	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
	/*	    configure but not enable each SDRAM partition pair.	    */

	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)

	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
	ldr	r4,	[r1, #MDCNFG_OFFSET]


	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
Commit	Line	Data
5e5803e1 SB	1	/*
	2	* This was originally from the Lubbock u-boot port.
	3	*
	4	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	5	*
	6	* NOTE: I haven't clean this up considerably, just enough to get it
	7	* running. See hal_platform_setup.h for the source. See
	8	* board/cradle/lowlevel_init.S for another PXA250 setup that is
	9	* much cleaner.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <config.h>
	31	#include <version.h>
	32	#include <asm/arch/pxa-regs.h>
	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41
	42	/*
	43	* Memory setup
	44	*/
	45
	46	.globl lowlevel_init
	47	lowlevel_init:
	48
	49	/* Set up GPIO pins first ----------------------------------------- */
	50
	51	ldr r0, =GPSR0
6d0f6bcf	52	ldr r1, =CONFIG_SYS_GPSR0_VAL
5e5803e1 SB	53	str r1, [r0]
	54
	55	ldr r0, =GPSR1
6d0f6bcf	56	ldr r1, =CONFIG_SYS_GPSR1_VAL
5e5803e1 SB	57	str r1, [r0]
	58
	59	ldr r0, =GPSR2
6d0f6bcf	60	ldr r1, =CONFIG_SYS_GPSR2_VAL
5e5803e1 SB	61	str r1, [r0]
	62
	63	ldr r0, =GPSR3
6d0f6bcf	64	ldr r1, =CONFIG_SYS_GPSR3_VAL
5e5803e1 SB	65	str r1, [r0]
	66
	67	ldr r0, =GPCR0
6d0f6bcf	68	ldr r1, =CONFIG_SYS_GPCR0_VAL
5e5803e1 SB	69	str r1, [r0]
	70
	71	ldr r0, =GPCR1
6d0f6bcf	72	ldr r1, =CONFIG_SYS_GPCR1_VAL
5e5803e1 SB	73	str r1, [r0]
	74
	75	ldr r0, =GPCR2
6d0f6bcf	76	ldr r1, =CONFIG_SYS_GPCR2_VAL
5e5803e1 SB	77	str r1, [r0]
	78
	79	ldr r0, =GPCR3
6d0f6bcf	80	ldr r1, =CONFIG_SYS_GPCR3_VAL
5e5803e1 SB	81	str r1, [r0]
	82
	83	ldr r0, =GRER0
6d0f6bcf	84	ldr r1, =CONFIG_SYS_GRER0_VAL
5e5803e1 SB	85	str r1, [r0]
	86
	87	ldr r0, =GRER1
6d0f6bcf	88	ldr r1, =CONFIG_SYS_GRER1_VAL
5e5803e1 SB	89	str r1, [r0]
	90
	91	ldr r0, =GRER2
6d0f6bcf	92	ldr r1, =CONFIG_SYS_GRER2_VAL
5e5803e1 SB	93	str r1, [r0]
	94
	95	ldr r0, =GRER3
6d0f6bcf	96	ldr r1, =CONFIG_SYS_GRER3_VAL
5e5803e1 SB	97	str r1, [r0]
	98
	99	ldr r0, =GFER0
6d0f6bcf	100	ldr r1, =CONFIG_SYS_GFER0_VAL
5e5803e1 SB	101	str r1, [r0]
	102
	103	ldr r0, =GFER1
6d0f6bcf	104	ldr r1, =CONFIG_SYS_GFER1_VAL
5e5803e1 SB	105	str r1, [r0]
	106
	107	ldr r0, =GFER2
6d0f6bcf	108	ldr r1, =CONFIG_SYS_GFER2_VAL
5e5803e1 SB	109	str r1, [r0]
	110
	111	ldr r0, =GFER3
6d0f6bcf	112	ldr r1, =CONFIG_SYS_GFER3_VAL
5e5803e1 SB	113	str r1, [r0]
	114
	115	ldr r0, =GPDR0
6d0f6bcf	116	ldr r1, =CONFIG_SYS_GPDR0_VAL
5e5803e1 SB	117	str r1, [r0]
	118
	119	ldr r0, =GPDR1
6d0f6bcf	120	ldr r1, =CONFIG_SYS_GPDR1_VAL
5e5803e1 SB	121	str r1, [r0]
	122
	123	ldr r0, =GPDR2
6d0f6bcf	124	ldr r1, =CONFIG_SYS_GPDR2_VAL
5e5803e1 SB	125	str r1, [r0]
	126
	127	ldr r0, =GPDR3
6d0f6bcf	128	ldr r1, =CONFIG_SYS_GPDR3_VAL
5e5803e1 SB	129	str r1, [r0]
	130
	131	ldr r0, =GAFR0_L
6d0f6bcf	132	ldr r1, =CONFIG_SYS_GAFR0_L_VAL
5e5803e1 SB	133	str r1, [r0]
	134
	135	ldr r0, =GAFR0_U
6d0f6bcf	136	ldr r1, =CONFIG_SYS_GAFR0_U_VAL
5e5803e1 SB	137	str r1, [r0]
	138
	139	ldr r0, =GAFR1_L
6d0f6bcf	140	ldr r1, =CONFIG_SYS_GAFR1_L_VAL
5e5803e1 SB	141	str r1, [r0]
	142
	143	ldr r0, =GAFR1_U
6d0f6bcf	144	ldr r1, =CONFIG_SYS_GAFR1_U_VAL
5e5803e1 SB	145	str r1, [r0]
	146
	147	ldr r0, =GAFR2_L
6d0f6bcf	148	ldr r1, =CONFIG_SYS_GAFR2_L_VAL
5e5803e1 SB	149	str r1, [r0]
	150
	151	ldr r0, =GAFR2_U
6d0f6bcf	152	ldr r1, =CONFIG_SYS_GAFR2_U_VAL
5e5803e1 SB	153	str r1, [r0]
	154
	155	ldr r0, =GAFR3_L
6d0f6bcf	156	ldr r1, =CONFIG_SYS_GAFR3_L_VAL
5e5803e1 SB	157	str r1, [r0]
	158
	159	ldr r0, =GAFR3_U
6d0f6bcf	160	ldr r1, =CONFIG_SYS_GAFR3_U_VAL
5e5803e1 SB	161	str r1, [r0]
	162
	163	ldr r0, =PSSR /* enable GPIO pins */
6d0f6bcf	164	ldr r1, =CONFIG_SYS_PSSR_VAL
5e5803e1 SB	165	str r1, [r0]
	166
	167	/* ---------------------------------------------------------------- */
	168	/* Enable memory interface */
	169	/* */
	170	/* The sequence below is based on the recommended init steps */
	171	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	172	/* Chapter 10. */
	173	/* ---------------------------------------------------------------- */
	174
	175	/* ---------------------------------------------------------------- */
	176	/* Step 1: Wait for at least 200 microsedonds to allow internal */
	177	/* clocks to settle. Only necessary after hard reset... */
	178	/* FIXME: can be optimized later */
	179	/* ---------------------------------------------------------------- */
	180
	181	ldr r3, =OSCR /* reset the OS Timer Count to zero */
	182	mov r2, #0
	183	str r2, [r3]
	184	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
	185	/* so 0x300 should be plenty */
	186	1:
	187	ldr r2, [r3]
	188	cmp r4, r2
	189	bgt 1b
	190
	191	mem_init:
	192
	193	ldr r1, =MEMC_BASE /* get memory controller base addr. */
	194
	195	/* ---------------------------------------------------------------- */
	196	/* Step 2a: Initialize Asynchronous static memory controller */
	197	/* ---------------------------------------------------------------- */
	198
	199	/* MSC registers: timing, bus width, mem type */
	200
	201	/* MSC0: nCS(0,1) */
6d0f6bcf	202	ldr r2, =CONFIG_SYS_MSC0_VAL
5e5803e1 SB	203	str r2, [r1, #MSC0_OFFSET]
	204	ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
	205	/* that data latches */
	206	/* MSC1: nCS(2,3) */
6d0f6bcf	207	ldr r2, =CONFIG_SYS_MSC1_VAL
5e5803e1 SB	208	str r2, [r1, #MSC1_OFFSET]
	209	ldr r2, [r1, #MSC1_OFFSET]
	210
	211	/* MSC2: nCS(4,5) */
6d0f6bcf	212	ldr r2, =CONFIG_SYS_MSC2_VAL
5e5803e1 SB	213	str r2, [r1, #MSC2_OFFSET]
	214	ldr r2, [r1, #MSC2_OFFSET]
	215
	216	/* ---------------------------------------------------------------- */
	217	/* Step 2b: Initialize Card Interface */
	218	/* ---------------------------------------------------------------- */
	219
	220	/* MECR: Memory Expansion Card Register */
6d0f6bcf	221	ldr r2, =CONFIG_SYS_MECR_VAL
5e5803e1 SB	222	str r2, [r1, #MECR_OFFSET]
	223	ldr r2, [r1, #MECR_OFFSET]
	224
	225	/* MCMEM0: Card Interface slot 0 timing */
6d0f6bcf	226	ldr r2, =CONFIG_SYS_MCMEM0_VAL
5e5803e1 SB	227	str r2, [r1, #MCMEM0_OFFSET]
	228	ldr r2, [r1, #MCMEM0_OFFSET]
	229
	230	/* MCMEM1: Card Interface slot 1 timing */
6d0f6bcf	231	ldr r2, =CONFIG_SYS_MCMEM1_VAL
5e5803e1 SB	232	str r2, [r1, #MCMEM1_OFFSET]
	233	ldr r2, [r1, #MCMEM1_OFFSET]
	234
	235	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
6d0f6bcf	236	ldr r2, =CONFIG_SYS_MCATT0_VAL
5e5803e1 SB	237	str r2, [r1, #MCATT0_OFFSET]
	238	ldr r2, [r1, #MCATT0_OFFSET]
	239
	240	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
6d0f6bcf	241	ldr r2, =CONFIG_SYS_MCATT1_VAL
5e5803e1 SB	242	str r2, [r1, #MCATT1_OFFSET]
	243	ldr r2, [r1, #MCATT1_OFFSET]
	244
	245	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
6d0f6bcf	246	ldr r2, =CONFIG_SYS_MCIO0_VAL
5e5803e1 SB	247	str r2, [r1, #MCIO0_OFFSET]
	248	ldr r2, [r1, #MCIO0_OFFSET]
	249
	250	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
6d0f6bcf	251	ldr r2, =CONFIG_SYS_MCIO1_VAL
5e5803e1 SB	252	str r2, [r1, #MCIO1_OFFSET]
	253	ldr r2, [r1, #MCIO1_OFFSET]
	254
	255	/* ---------------------------------------------------------------- */
	256	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
	257	/* ---------------------------------------------------------------- */
6d0f6bcf	258	ldr r2, =CONFIG_SYS_FLYCNFG_VAL
5e5803e1 SB	259	str r2, [r1, #FLYCNFG_OFFSET]
	260	str r2, [r1, #FLYCNFG_OFFSET]
	261
	262	/* ---------------------------------------------------------------- */
	263	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
	264	/* ---------------------------------------------------------------- */
	265
	266	/* Before accessing MDREFR we need a valid DRI field, so we set */
	267	/* this to power on defaults + DRI field. */
	268
	269	ldr r4, [r1, #MDREFR_OFFSET]
	270	ldr r2, =0xFFF
	271	bic r4, r4, r2
	272
6d0f6bcf	273	ldr r3, =CONFIG_SYS_MDREFR_VAL
5e5803e1 SB	274	and r3, r3, r2
	275
	276	orr r4, r4, r3
	277	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	278
	279	orr r4, r4, #MDREFR_K0RUN
	280	orr r4, r4, #MDREFR_K0DB4
	281	orr r4, r4, #MDREFR_K0FREE
	282	orr r4, r4, #MDREFR_K0DB2
	283	orr r4, r4, #MDREFR_K1DB2
	284	bic r4, r4, #MDREFR_K1FREE
	285	bic r4, r4, #MDREFR_K2FREE
	286
	287	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	288	ldr r4, [r1, #MDREFR_OFFSET]
	289
	290	/* Note: preserve the mdrefr value in r4 */
	291
	292
	293	/* ---------------------------------------------------------------- */
	294	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	295	/* ---------------------------------------------------------------- */
	296
	297	/* Initialize SXCNFG register. Assert the enable bits */
	298
	299	/* Write SXMRS to cause an MRS command to all enabled banks of */
	300	/* synchronous static memory. Note that SXLCR need not be written */
	301	/* at this time. */
	302
6d0f6bcf	303	ldr r2, =CONFIG_SYS_SXCNFG_VAL
5e5803e1 SB	304	str r2, [r1, #SXCNFG_OFFSET]
	305
	306	/* ---------------------------------------------------------------- */
	307	/* Step 4: Initialize SDRAM */
	308	/* ---------------------------------------------------------------- */
	309
	310	bic r4, r4, #(MDREFR_K2FREE \|MDREFR_K1FREE \| MDREFR_K0FREE)
	311
	312	orr r4, r4, #MDREFR_K1RUN
	313	bic r4, r4, #MDREFR_K2DB2
	314	str r4, [r1, #MDREFR_OFFSET]
	315	ldr r4, [r1, #MDREFR_OFFSET]
	316
	317	bic r4, r4, #MDREFR_SLFRSH
	318	str r4, [r1, #MDREFR_OFFSET]
	319	ldr r4, [r1, #MDREFR_OFFSET]
	320
	321	orr r4, r4, #MDREFR_E1PIN
	322	str r4, [r1, #MDREFR_OFFSET]
	323	ldr r4, [r1, #MDREFR_OFFSET]
	324
	325	nop
	326	nop
	327
	328
	329	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
	330	/* configure but not enable each SDRAM partition pair. */
	331
6d0f6bcf	332	ldr r4, =CONFIG_SYS_MDCNFG_VAL
5e5803e1 SB	333	bic r4, r4, #(MDCNFG_DE0\|MDCNFG_DE1)
	334	bic r4, r4, #(MDCNFG_DE2\|MDCNFG_DE3)
	335
	336	str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
	337	ldr r4, [r1, #MDCNFG_OFFSET]
	338
	339
	340	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	341