[J-u-boot.git] / board / amcc / makalu / makalu.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <ppc405.h>
#include <libfdt.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <fdt_support.h>

#if defined(CONFIG_PCI)
#include <pci.h>
#include <asm/4xx_pcie.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

/*
 * Board early initialization function
 */
int board_early_init_f (void)
{
	u32 val;

	/*--------------------------------------------------------------------+
	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
	 +--------------------------------------------------------------------+
	+---------------------------------------------------------------------+
	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
	+---------+-----------------------------------+-------+-------+-------+
	| IRQ 00  | UART0                             | High  | Level | Non   |
	| IRQ 01  | UART1                             | High  | Level | Non   |
	| IRQ 02  | IIC0                              | High  | Level | Non   |
	| IRQ 03  | TBD                               | High  | Level | Non   |
	| IRQ 04  | TBD                               | High  | Level | Non   |
	| IRQ 05  | EBM                               | High  | Level | Non   |
	| IRQ 06  | BGI                               | High  | Level | Non   |
	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
	|----------------------------------------------------------------------
	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
	| IRQ 38  | NDFC                              | High  | Level | Non   |
	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
	|----------------------------------------------------------------------
	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
	|---------------------------------------------------------------------
	+---------+-----------------------------------+-------+-------+------*/
	/*--------------------------------------------------------------------+
	 | Initialise UIC registers.  Clear all interrupts.  Disable all
	 | interrupts.
	 | Set critical interrupt values.  Set interrupt polarities.  Set
	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
	 | interrupts again.
	 +-------------------------------------------------------------------*/

	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
	mtdcr (uic2pr, 0xf7ffffff);	/* Set Interrupt Polarities */
	mtdcr (uic2tr, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */

	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
	mtdcr (uic1pr, 0xfffac785);	/* Set Interrupt Polarities */
	mtdcr (uic1tr, 0x001d0040);	/* Set Interrupt Trigger Levels */
	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */

	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic0er, 0x0000000a);	/* Disable all interrupts */
					/* Except cascade UIC0 and UIC1 */
	mtdcr (uic0cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
	mtdcr (uic0pr, 0xffbfefef);	/* Set Interrupt Polarities */
	mtdcr (uic0tr, 0x00007000);	/* Set Interrupt Trigger Levels */
	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */

	/*
	 * Note: Some cores are still in reset when the chip starts, so
	 * take them out of reset
	 */
	mtsdr(SDR0_SRST, 0);

	/* Reset PCIe slots */
	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
	udelay(100);
	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);

	/*
	 * Configure PFC (Pin Function Control) registers
	 * -> Enable USB
	 */
	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
	mtsdr(SDR0_PFC1, val);

	return 0;
}

int misc_init_r(void)
{
#ifdef CONFIG_ENV_IS_IN_FLASH
	/* Monitor protection ON by default */
	flash_protect(FLAG_PROTECT_SET,
		      -CONFIG_SYS_MONITOR_LEN,
		      0xffffffff,
		      &flash_info[0]);
#endif

	return 0;
}

int checkboard (void)
{
	char *s = getenv("serial#");

	printf("Board: Makalu - AMCC PPC405EX Evaluation Board");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *      Different boards may wish to customize the pci controller structure
 *      (add regions, override default access routines, etc) or perform
 *      certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
	return 0;
}
#endif  /* defined(CONFIG_PCI) */

#ifdef CONFIG_PCI
static struct pci_controller pcie_hose[2] = {{0},{0}};

void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	int ret = 0;
	bus = busno;
	char *env;
	unsigned int delay;

	for (i = 0; i < 2; i++) {

		if (is_end_point(i))
			ret = ppc4xx_init_pcie_endport(i);
		else
			ret = ppc4xx_init_pcie_rootport(i);
		if (ret) {
			printf("PCIE%d: initialization as %s failed\n", i,
			       is_end_point(i) ? "endpoint" : "root-complex");
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
			       CONFIG_SYS_PCIE_MEMSIZE,
			       PCI_REGION_MEM);
		hose->region_count = 1;
		pci_register_hose(hose);

		if (is_end_point(i)) {
			ppc4xx_setup_pcie_endpoint(hose, i);
			/*
			 * Reson for no scanning is endpoint can not generate
			 * upstream configuration accesses.
			 */
		} else {
			ppc4xx_setup_pcie_rootpoint(hose, i);
			env = getenv ("pciscandelay");
			if (env != NULL) {
				delay = simple_strtoul(env, NULL, 10);
				if (delay > 5)
					printf("Warning, expect noticable delay before "
					       "PCIe scan due to 'pciscandelay' value!\n");
				mdelay(delay * 1000);
			}

			/*
			 * Config access can only go down stream
			 */
			hose->last_busno = pci_hose_scan(hose);
			bus = hose->last_busno + 1;
		}
	}
}
#endif

#if defined(CONFIG_POST)
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return 0;	/* No hotkeys supported */
}
#endif /* CONFIG_POST */
Commit	Line	Data
211ea91a SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <ppc4xx.h>
	26	#include <ppc405.h>
	27	#include <libfdt.h>
	28	#include <asm/processor.h>
ecdcbd4f SR	29	#include <asm/gpio.h>
ecdcbd4f SR	30	#include <asm/io.h>
6eb3fb15	31	#include <fdt_support.h>
211ea91a SR	32
	33	#if defined(CONFIG_PCI)
	34	#include <pci.h>
	35	#include <asm/4xx_pcie.h>
	36	#endif
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
6d0f6bcf	40	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
211ea91a SR	41
	42	/*
	43	* Board early initialization function
	44	*/
	45	int board_early_init_f (void)
	46	{
7cfc12a7 SR	47	u32 val;
7cfc12a7 SR	48
211ea91a SR	49	/*--------------------------------------------------------------------+
	50	\| Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
	51	+--------------------------------------------------------------------+
	52	+---------------------------------------------------------------------+
	53	\|Interrupt\| Source \| Pol. \| Sensi.\| Crit. \|
	54	+---------+-----------------------------------+-------+-------+-------+
	55	\| IRQ 00 \| UART0 \| High \| Level \| Non \|
	56	\| IRQ 01 \| UART1 \| High \| Level \| Non \|
	57	\| IRQ 02 \| IIC0 \| High \| Level \| Non \|
	58	\| IRQ 03 \| TBD \| High \| Level \| Non \|
	59	\| IRQ 04 \| TBD \| High \| Level \| Non \|
	60	\| IRQ 05 \| EBM \| High \| Level \| Non \|
	61	\| IRQ 06 \| BGI \| High \| Level \| Non \|
	62	\| IRQ 07 \| IIC1 \| Rising\| Edge \| Non \|
	63	\| IRQ 08 \| SPI \| High \| Lvl/ed\| Non \|
	64	\| IRQ 09 \| External IRQ 0 - (PCI-Express) \| pgm H \| Pgm \| Non \|
	65	\| IRQ 10 \| MAL TX EOB \| High \| Level \| Non \|
	66	\| IRQ 11 \| MAL RX EOB \| High \| Level \| Non \|
	67	\| IRQ 12 \| DMA Channel 0 FIFO Full \| High \| Level \| Non \|
	68	\| IRQ 13 \| DMA Channel 0 Stat FIFO \| High \| Level \| Non \|
	69	\| IRQ 14 \| DMA Channel 1 FIFO Full \| High \| Level \| Non \|
	70	\| IRQ 15 \| DMA Channel 1 Stat FIFO \| High \| Level \| Non \|
	71	\| IRQ 16 \| PCIE0 AL \| high \| Level \| Non \|
	72	\| IRQ 17 \| PCIE0 VPD access \| rising\| Edge \| Non \|
	73	\| IRQ 18 \| PCIE0 hot reset request \| rising\| Edge \| Non \|
	74	\| IRQ 19 \| PCIE0 hot reset request \| faling\| Edge \| Non \|
	75	\| IRQ 20 \| PCIE0 TCR \| High \| Level \| Non \|
	76	\| IRQ 21 \| PCIE0 MSI level0 \| High \| Level \| Non \|
	77	\| IRQ 22 \| PCIE0 MSI level1 \| High \| Level \| Non \|
	78	\| IRQ 23 \| Security EIP-94 \| High \| Level \| Non \|
	79	\| IRQ 24 \| EMAC0 interrupt \| High \| Level \| Non \|
	80	\| IRQ 25 \| EMAC1 interrupt \| High \| Level \| Non \|
	81	\| IRQ 26 \| PCIE0 MSI level2 \| High \| Level \| Non \|
	82	\| IRQ 27 \| External IRQ 4 \| pgm H \| Pgm \| Non \|
	83	\| IRQ 28 \| UIC2 Non-critical Int. \| High \| Level \| Non \|
	84	\| IRQ 29 \| UIC2 Critical Interrupt \| High \| Level \| Crit. \|
	85	\| IRQ 30 \| UIC1 Non-critical Int. \| High \| Level \| Non \|
	86	\| IRQ 31 \| UIC1 Critical Interrupt \| High \| Level \| Crit. \|
	87	\|----------------------------------------------------------------------
	88	\| IRQ 32 \| MAL Serr \| High \| Level \| Non \|
	89	\| IRQ 33 \| MAL Txde \| High \| Level \| Non \|
	90	\| IRQ 34 \| MAL Rxde \| High \| Level \| Non \|
	91	\| IRQ 35 \| PCIE0 bus master VC0 \|falling\| Edge \| Non \|
	92	\| IRQ 36 \| PCIE0 DCR Error \| High \| Level \| Non \|
	93	\| IRQ 37 \| EBC \| High \|Lvl Edg\| Non \|
	94	\| IRQ 38 \| NDFC \| High \| Level \| Non \|
	95	\| IRQ 39 \| GPT Compare Timer 8 \| Risin \| Edge \| Non \|
	96	\| IRQ 40 \| GPT Compare Timer 9 \| Risin \| Edge \| Non \|
	97	\| IRQ 41 \| PCIE1 AL \| high \| Level \| Non \|
	98	\| IRQ 42 \| PCIE1 VPD access \| rising\| edge \| Non \|
	99	\| IRQ 43 \| PCIE1 hot reset request \| rising\| Edge \| Non \|
	100	\| IRQ 44 \| PCIE1 hot reset request \| faling\| Edge \| Non \|
	101	\| IRQ 45 \| PCIE1 TCR \| High \| Level \| Non \|
	102	\| IRQ 46 \| PCIE1 bus master VC0 \|falling\| Edge \| Non \|
	103	\| IRQ 47 \| GPT Compare Timer 3 \| Risin \| Edge \| Non \|
	104	\| IRQ 48 \| GPT Compare Timer 4 \| Risin \| Edge \| Non \|
	105	\| IRQ 49 \| Ext. IRQ 7 \|pgm/Fal\|pgm/Lvl\| Non \|
	106	\| IRQ 50 \| Ext. IRQ 8 - \|pgm (H)\|pgm/Lvl\| Non \|
	107	\| IRQ 51 \| Ext. IRQ 9 \|pgm (H)\|pgm/Lvl\| Non \|
	108	\| IRQ 52 \| GPT Compare Timer 5 \| high \| Edge \| Non \|
	109	\| IRQ 53 \| GPT Compare Timer 6 \| high \| Edge \| Non \|
	110	\| IRQ 54 \| GPT Compare Timer 7 \| high \| Edge \| Non \|
	111	\| IRQ 55 \| Serial ROM \| High \| Level \| Non \|
	112	\| IRQ 56 \| GPT Decrement Pulse \| High \| Level \| Non \|
113	\| IRQ 57 \| Ext. IRQ 2 \|pgm/Fal\|pgm/Lvl\| Non \|
114	\| IRQ 58 \| Ext. IRQ 5 \|pgm/Fal\|pgm/Lvl\| Non \|
115	\| IRQ 59 \| Ext. IRQ 6 \|pgm/Fal\|pgm/Lvl\| Non \|
116	\| IRQ 60 \| EMAC0 Wake-up \| High \| Level \| Non \|
117	\| IRQ 61 \| Ext. IRQ 1 \|pgm/Fal\|pgm/Lvl\| Non \|
118	\| IRQ 62 \| EMAC1 Wake-up \| High \| Level \| Non \|
119	\|----------------------------------------------------------------------
120	\| IRQ 64 \| PE0 AL \| High \| Level \| Non \|
121	\| IRQ 65 \| PE0 VPD Access \| Risin \| Edge \| Non \|
122	\| IRQ 66 \| PE0 Hot Reset Request \| Risin \| Edge \| Non \|
123	\| IRQ 67 \| PE0 Hot Reset Request \| Falli \| Edge \| Non \|
124	\| IRQ 68 \| PE0 TCR \| High \| Level \| Non \|
125	\| IRQ 69 \| PE0 BusMaster VCO \| Falli \| Edge \| Non \|
126	\| IRQ 70 \| PE0 DCR Error \| High \| Level \| Non \|
127	\| IRQ 71 \| Reserved \| N/A \| N/A \| Non \|
128	\| IRQ 72 \| PE1 AL \| High \| Level \| Non \|
129	\| IRQ 73 \| PE1 VPD Access \| Risin \| Edge \| Non \|
130	\| IRQ 74 \| PE1 Hot Reset Request \| Risin \| Edge \| Non \|
131	\| IRQ 75 \| PE1 Hot Reset Request \| Falli \| Edge \| Non \|
132	\| IRQ 76 \| PE1 TCR \| High \| Level \| Non \|
133	\| IRQ 77 \| PE1 BusMaster VCO \| Falli \| Edge \| Non \|
134	\| IRQ 78 \| PE1 DCR Error \| High \| Level \| Non \|
135	\| IRQ 79 \| Reserved \| N/A \| N/A \| Non \|
136	\| IRQ 80 \| PE2 AL \| High \| Level \| Non \|
137	\| IRQ 81 \| PE2 VPD Access \| Risin \| Edge \| Non \|
138	\| IRQ 82 \| PE2 Hot Reset Request \| Risin \| Edge \| Non \|
139	\| IRQ 83 \| PE2 Hot Reset Request \| Falli \| Edge \| Non \|
140	\| IRQ 84 \| PE2 TCR \| High \| Level \| Non \|
141	\| IRQ 85 \| PE2 BusMaster VCO \| Falli \| Edge \| Non \|
142	\| IRQ 86 \| PE2 DCR Error \| High \| Level \| Non \|
143	\| IRQ 87 \| Reserved \| N/A \| N/A \| Non \|
144	\| IRQ 88 \| External IRQ(5) \| Progr \| Progr \| Non \|
145	\| IRQ 89 \| External IRQ 4 - Ethernet \| Progr \| Progr \| Non \|
146	\| IRQ 90 \| External IRQ 3 - PCI-X \| Progr \| Progr \| Non \|
147	\| IRQ 91 \| External IRQ 2 - PCI-X \| Progr \| Progr \| Non \|
148	\| IRQ 92 \| External IRQ 1 - PCI-X \| Progr \| Progr \| Non \|
149	\| IRQ 93 \| External IRQ 0 - PCI-X \| Progr \| Progr \| Non \|
150	\| IRQ 94 \| Reserved \| N/A \| N/A \| Non \|
151	\| IRQ 95 \| Reserved \| N/A \| N/A \| Non \|
152	\|---------------------------------------------------------------------
153	+---------+-----------------------------------+-------+-------+------*/
154	/*--------------------------------------------------------------------+
155	\| Initialise UIC registers. Clear all interrupts. Disable all
156	\| interrupts.
157	\| Set critical interrupt values. Set interrupt polarities. Set
158	\| interrupt trigger levels. Make bit 0 High priority. Clear all
159	\| interrupts again.
160	+-------------------------------------------------------------------*/
161
162	mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
163	mtdcr (uic2er, 0x00000000); /* disable all interrupts */
164	mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
165	mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
166	mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
167	mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
168	mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
169	mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
170
171	mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
172	mtdcr (uic1er, 0x00000000); /* disable all interrupts */
173	mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
174	mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
175	mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
176	mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
177	mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
178	mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
179
180	mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
181	mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
182	/* Except cascade UIC0 and UIC1 */
183	mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
184	mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
185	mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
186	mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
187	mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
188	mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
189
190	/*
191	* Note: Some cores are still in reset when the chip starts, so
192	* take them out of reset
193	*/
194	mtsdr(SDR0_SRST, 0);
195
ecdcbd4f	196	/* Reset PCIe slots */
6d0f6bcf	197	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
ecdcbd4f	198	udelay(100);
6d0f6bcf	199	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
ecdcbd4f	200
7cfc12a7 SR	201	/*
	202	* Configure PFC (Pin Function Control) registers
	203	* -> Enable USB
	204	*/
	205	val = SDR0_PFC1_USBEN \| SDR0_PFC1_USBBIGEN \| SDR0_PFC1_GPT_FREQ;
	206	mtsdr(SDR0_PFC1, val);
	207
211ea91a SR	208	return 0;
	209	}
	210
	211	int misc_init_r(void)
	212	{
5a1aceb0	213	#ifdef CONFIG_ENV_IS_IN_FLASH
211ea91a SR	214	/* Monitor protection ON by default */
211ea91a SR	215	flash_protect(FLAG_PROTECT_SET,
6d0f6bcf	216	-CONFIG_SYS_MONITOR_LEN,
211ea91a SR	217	0xffffffff,
	218	&flash_info[0]);
	219	#endif
	220
	221	return 0;
	222	}
	223
	224	int checkboard (void)
	225	{
	226	char *s = getenv("serial#");
	227
	228	printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
	229
	230	if (s != NULL) {
	231	puts(", serial# ");
	232	puts(s);
	233	}
	234	putc('\n');
	235
	236	return (0);
	237	}
	238
	239	/*************************************************************************
	240	* pci_pre_init
	241	*
	242	* This routine is called just prior to registering the hose and gives
	243	* the board the opportunity to check things. Returning a value of zero
	244	* indicates that things are bad & PCI initialization should be aborted.
	245	*
	246	* Different boards may wish to customize the pci controller structure
	247	* (add regions, override default access routines, etc) or perform
	248	* certain pre-initialization actions.
	249	*
	250	************************************************************************/
	251	#if defined(CONFIG_PCI)
	252	int pci_pre_init(struct pci_controller * hose )
	253	{
	254	return 0;
	255	}
	256	#endif /* defined(CONFIG_PCI) */
	257
211ea91a SR	258	#ifdef CONFIG_PCI
	259	static struct pci_controller pcie_hose[2] = {{0},{0}};
	260
	261	void pcie_setup_hoses(int busno)
	262	{
	263	struct pci_controller *hose;
	264	int i, bus;
	265	int ret = 0;
	266	bus = busno;
	267	char *env;
	268	unsigned int delay;
	269
	270	for (i = 0; i < 2; i++) {
	271
ecdcbd4f	272	if (is_end_point(i))
211ea91a	273	ret = ppc4xx_init_pcie_endport(i);
ecdcbd4f	274	else
211ea91a	275	ret = ppc4xx_init_pcie_rootport(i);
211ea91a	276	if (ret) {
ecdcbd4f SR	277	printf("PCIE%d: initialization as %s failed\n", i,
ecdcbd4f SR	278	is_end_point(i) ? "endpoint" : "root-complex");
211ea91a SR	279	continue;
	280	}
	281
	282	hose = &pcie_hose[i];
	283	hose->first_busno = bus;
	284	hose->last_busno = bus;
	285	hose->current_busno = bus;
	286
	287	/* setup mem resource */
	288	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	289	CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
	290	CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
	291	CONFIG_SYS_PCIE_MEMSIZE,
211ea91a SR	292	PCI_REGION_MEM);
	293	hose->region_count = 1;
	294	pci_register_hose(hose);
	295
	296	if (is_end_point(i)) {
53677ef1	297	ppc4xx_setup_pcie_endpoint(hose, i);
211ea91a SR	298	/*
	299	* Reson for no scanning is endpoint can not generate
	300	* upstream configuration accesses.
53677ef1	301	*/
211ea91a	302	} else {
53677ef1	303	ppc4xx_setup_pcie_rootpoint(hose, i);
211ea91a	304	env = getenv ("pciscandelay");
53677ef1 WD	305	if (env != NULL) {
53677ef1 WD	306	delay = simple_strtoul(env, NULL, 10);
211ea91a	307	if (delay > 5)
53677ef1	308	printf("Warning, expect noticable delay before "
211ea91a SR	309	"PCIe scan due to 'pciscandelay' value!\n");
	310	mdelay(delay * 1000);
	311	}
	312
53677ef1 WD	313	/*
	314	* Config access can only go down stream
	315	*/
	316	hose->last_busno = pci_hose_scan(hose);
	317	bus = hose->last_busno + 1;
211ea91a SR	318	}
	319	}
	320	}
	321	#endif
	322
	323	#if defined(CONFIG_POST)
	324	/*
	325	* Returns 1 if keys pressed to start the power-on long-running tests
	326	* Called from board_init_f().
	327	*/
	328	int post_hotkeys_pressed(void)
	329	{
	330	return 0; /* No hotkeys supported */
	331	}
	332	#endif /* CONFIG_POST */