[J-u-boot.git] / drivers / clk / renesas / r8a77995-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2017 Glider bvba
 *
 * Based on r8a7795-cpg-mssr.c
 *
 * Copyright (C) 2015 Glider bvba
 * Copyright (C) 2015 Renesas Electronics Corp.
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <linux/bitops.h>

#include <dt-bindings/clock/r8a77995-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,

	/* External Input Clocks */
	CLK_EXTAL,

	/* Internal Core Clocks */
	CLK_MAIN,
	CLK_PLL0,
	CLK_PLL1,
	CLK_PLL3,
	CLK_PLL0D2,
	CLK_PLL0D3,
	CLK_PLL0D5,
	CLK_PLL1D2,
	CLK_PE,
	CLK_S0,
	CLK_S1,
	CLK_S2,
	CLK_S3,
	CLK_SDSRC,
	CLK_RPCSRC,
	CLK_RINT,
	CLK_OCO,

	/* Module Clocks */
	MOD_CLK_BASE
};

static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
	/* External Clock Inputs */
	DEF_INPUT("extal",     CLK_EXTAL),

	/* Internal Core Clocks */
	DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
	DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
	DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),

	DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,	   4, 250),
	DEF_FIXED(".pll0d2",   CLK_PLL0D2,         CLK_PLL0,       2, 1),
	DEF_FIXED(".pll0d3",   CLK_PLL0D3,         CLK_PLL0,       3, 1),
	DEF_FIXED(".pll0d5",   CLK_PLL0D5,         CLK_PLL0,       5, 1),
	DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
	DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D3,     4, 1),
	DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
	DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
	DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),

	DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),

	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),

	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),

	/* Core Clock Outputs */
	DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,     2, 1),
	DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
	DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
	DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
	DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),
	DEF_FIXED("s0d1",      R8A77995_CLK_S0D1,  CLK_S0,         1, 1),
	DEF_FIXED("s1d1",      R8A77995_CLK_S1D1,  CLK_S1,         1, 1),
	DEF_FIXED("s1d2",      R8A77995_CLK_S1D2,  CLK_S1,         2, 1),
	DEF_FIXED("s1d4",      R8A77995_CLK_S1D4,  CLK_S1,         4, 1),
	DEF_FIXED("s2d1",      R8A77995_CLK_S2D1,  CLK_S2,         1, 1),
	DEF_FIXED("s2d2",      R8A77995_CLK_S2D2,  CLK_S2,         2, 1),
	DEF_FIXED("s2d4",      R8A77995_CLK_S2D4,  CLK_S2,         4, 1),
	DEF_FIXED("s3d1",      R8A77995_CLK_S3D1,  CLK_S3,         1, 1),
	DEF_FIXED("s3d2",      R8A77995_CLK_S3D2,  CLK_S3,         2, 1),
	DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),

	DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
	DEF_FIXED("cr",        R8A77995_CLK_CR,    CLK_PLL1D2,     2, 1),
	DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
	DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),

	DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),

	DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
	DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
	DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
	DEF_GEN3_PE("s3d4c",   R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),

	DEF_GEN3_SDH("sd0h",   R8A77995_CLK_SD0H,  CLK_SDSRC,         0x268),
	DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,   R8A77995_CLK_SD0H, 0x268),

	DEF_BASE("rpc",        R8A77995_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
	DEF_BASE("rpcd2",      R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),

	DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
	DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),

	DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};

static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
	DEF_MOD("tmu4",			 121,	R8A77995_CLK_S1D4C),
	DEF_MOD("tmu3",			 122,	R8A77995_CLK_S3D2C),
	DEF_MOD("tmu2",			 123,	R8A77995_CLK_S3D2C),
	DEF_MOD("tmu1",			 124,	R8A77995_CLK_S3D2C),
	DEF_MOD("tmu0",			 125,	R8A77995_CLK_CP),
	DEF_MOD("scif5",		 202,	R8A77995_CLK_S3D4C),
	DEF_MOD("scif4",		 203,	R8A77995_CLK_S3D4C),
	DEF_MOD("scif3",		 204,	R8A77995_CLK_S3D4C),
	DEF_MOD("scif1",		 206,	R8A77995_CLK_S3D4C),
	DEF_MOD("scif0",		 207,	R8A77995_CLK_S3D4C),
	DEF_MOD("msiof3",		 208,	R8A77995_CLK_MSO),
	DEF_MOD("msiof2",		 209,	R8A77995_CLK_MSO),
	DEF_MOD("msiof1",		 210,	R8A77995_CLK_MSO),
	DEF_MOD("msiof0",		 211,	R8A77995_CLK_MSO),
	DEF_MOD("sys-dmac2",		 217,	R8A77995_CLK_S3D1),
	DEF_MOD("sys-dmac1",		 218,	R8A77995_CLK_S3D1),
	DEF_MOD("sys-dmac0",		 219,	R8A77995_CLK_S3D1),
	DEF_MOD("sceg-pub",		 229,	R8A77995_CLK_CR),
	DEF_MOD("cmt3",			 300,	R8A77995_CLK_R),
	DEF_MOD("cmt2",			 301,	R8A77995_CLK_R),
	DEF_MOD("cmt1",			 302,	R8A77995_CLK_R),
	DEF_MOD("cmt0",			 303,	R8A77995_CLK_R),
	DEF_MOD("scif2",		 310,	R8A77995_CLK_S3D4C),
	DEF_MOD("emmc0",		 312,	R8A77995_CLK_SD0),
	DEF_MOD("usb-dmac0",		 330,	R8A77995_CLK_S3D1),
	DEF_MOD("usb-dmac1",		 331,	R8A77995_CLK_S3D1),
	DEF_MOD("rwdt",			 402,	R8A77995_CLK_R),
	DEF_MOD("intc-ex",		 407,	R8A77995_CLK_CP),
	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S1D2),
	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S1D2),
	DEF_MOD("hscif3",		 517,	R8A77995_CLK_S3D1C),
	DEF_MOD("hscif0",		 520,	R8A77995_CLK_S3D1C),
	DEF_MOD("thermal",		 522,	R8A77995_CLK_CP),
	DEF_MOD("pwm",			 523,	R8A77995_CLK_S3D4C),
	DEF_MOD("fcpvd1",		 602,	R8A77995_CLK_S1D2),
	DEF_MOD("fcpvd0",		 603,	R8A77995_CLK_S1D2),
	DEF_MOD("fcpvbs",		 607,	R8A77995_CLK_S0D1),
	DEF_MOD("vspd1",		 622,	R8A77995_CLK_S1D2),
	DEF_MOD("vspd0",		 623,	R8A77995_CLK_S1D2),
	DEF_MOD("vspbs",		 627,	R8A77995_CLK_S0D1),
	DEF_MOD("ehci0",		 703,	R8A77995_CLK_S3D2),
	DEF_MOD("hsusb",		 704,	R8A77995_CLK_S3D2),
	DEF_MOD("cmm1",			 710,	R8A77995_CLK_S1D1),
	DEF_MOD("cmm0",			 711,	R8A77995_CLK_S1D1),
	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),
	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),
	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),
	DEF_MOD("mlp",			 802,	R8A77995_CLK_S2D1),
	DEF_MOD("vin4",			 807,	R8A77995_CLK_S3D1),
	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),
	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),
	DEF_MOD("gpio6",		 906,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio5",		 907,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio4",		 908,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio3",		 909,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio2",		 910,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio1",		 911,	R8A77995_CLK_S3D4),
	DEF_MOD("gpio0",		 912,	R8A77995_CLK_S3D4),
	DEF_MOD("can-fd",		 914,	R8A77995_CLK_S3D2),
	DEF_MOD("can-if1",		 915,	R8A77995_CLK_S3D4),
	DEF_MOD("can-if0",		 916,	R8A77995_CLK_S3D4),
	DEF_MOD("rpc-if",		 917,	R8A77995_CLK_RPCD2),
	DEF_MOD("i2c3",			 928,	R8A77995_CLK_S3D2),
	DEF_MOD("i2c2",			 929,	R8A77995_CLK_S3D2),
	DEF_MOD("i2c1",			 930,	R8A77995_CLK_S3D2),
	DEF_MOD("i2c0",			 931,	R8A77995_CLK_S3D2),
	DEF_MOD("ssi-all",		1005,	R8A77995_CLK_S3D4),
	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
	DEF_MOD("scu-all",		1017,	R8A77995_CLK_S3D4),
	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
};

/*
 * CPG Clock Data
 */

/*
 * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
 *--------------------------------------------------------------------
 * 0		48 x 1		x250/4		x100/3		x100/3
 * 1		48 x 1		x250/4		x100/3		x58/3
 */
#define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)

static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
	{ 1,		100,	3,	100,	3,	},
	{ 1,		100,	3,	58,	3,	},
};

static const struct mstp_stop_table r8a77995_mstp_table[] = {
	{ 0x00210000, 0x0, 0x00210000, 0 },
	{ 0x03e01000, 0x0, 0x03e01000, 0 },
	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
	{ 0xc00014df, 0x400, 0xc00014df, 0 },
	{ 0x80000004, 0x180, 0x80000004, 0 },
	{ 0x40d20004, 0x0, 0x40d20004, 0 },
	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
	{ 0x09941c18, 0x0, 0x09941c18, 0 },
	{ 0x00801087, 0x0, 0x00801087, 0 },
	{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
	{ 0x063e1820, 0x0, 0x063e1820, 0 },
	{ 0x00000000, 0x0, 0x00000000, 0 },
};

static const void *r8a77995_get_pll_config(const u32 cpg_mode)
{
	return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}

static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
	.core_clk		= r8a77995_core_clks,
	.core_clk_size		= ARRAY_SIZE(r8a77995_core_clks),
	.mod_clk		= r8a77995_mod_clks,
	.mod_clk_size		= ARRAY_SIZE(r8a77995_mod_clks),
	.mstp_table		= r8a77995_mstp_table,
	.mstp_table_size	= ARRAY_SIZE(r8a77995_mstp_table),
	.reset_node		= "renesas,r8a77995-rst",
	.reset_modemr_offset	= CPG_RST_MODEMR,
	.mod_clk_base		= MOD_CLK_BASE,
	.clk_extal_id		= CLK_EXTAL,
	.clk_extalr_id		= ~0,
	.get_pll_config		= r8a77995_get_pll_config,
};

static const struct udevice_id r8a77995_cpg_ids[] = {
	{
		.compatible	= "renesas,r8a77995-cpg-mssr",
		.data		= (ulong)&r8a77995_cpg_mssr_info
	},
	{ }
};

U_BOOT_DRIVER(cpg_r8a77995) = {
	.name		= "cpg_r8a77995",
	.id		= UCLASS_NOP,
	.of_match	= r8a77995_cpg_ids,
	.bind		= gen3_cpg_bind,
};
Commit	Line	Data
72242e54	1	// SPDX-License-Identifier: GPL-2.0
f77b5a4c	2	/*
72242e54	3	* r8a77995 Clock Pulse Generator / Module Standby and Software Reset
f77b5a4c	4	*
72242e54	5	* Copyright (C) 2017 Glider bvba
f77b5a4c	6	*
72242e54	7	* Based on r8a7795-cpg-mssr.c
f77b5a4c	8	*
72242e54 MV	9	* Copyright (C) 2015 Glider bvba
72242e54 MV	10	* Copyright (C) 2015 Renesas Electronics Corp.
f77b5a4c MV	11	*/
	12
	13	#include <common.h>
	14	#include <clk-uclass.h>
	15	#include <dm.h>
cd93d625	16	#include <linux/bitops.h>
f77b5a4c MV	17
	18	#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
	19
	20	#include "renesas-cpg-mssr.h"
58f1788f	21	#include "rcar-gen3-cpg.h"
f77b5a4c	22
f11c9679 MV	23	enum clk_ids {
f11c9679 MV	24	/* Core Clock Outputs exported to DT */
72242e54	25	LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
f11c9679 MV	26
	27	/* External Input Clocks */
	28	CLK_EXTAL,
	29
	30	/* Internal Core Clocks */
	31	CLK_MAIN,
	32	CLK_PLL0,
	33	CLK_PLL1,
	34	CLK_PLL3,
	35	CLK_PLL0D2,
	36	CLK_PLL0D3,
	37	CLK_PLL0D5,
	38	CLK_PLL1D2,
	39	CLK_PE,
	40	CLK_S0,
	41	CLK_S1,
	42	CLK_S2,
	43	CLK_S3,
	44	CLK_SDSRC,
ccc2c9aa	45	CLK_RPCSRC,
72242e54 MV	46	CLK_RINT,
72242e54 MV	47	CLK_OCO,
f11c9679 MV	48
	49	/* Module Clocks */
	50	MOD_CLK_BASE
	51	};
	52
501a4ebb	53	static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
f77b5a4c MV	54	/* External Clock Inputs */
	55	DEF_INPUT("extal", CLK_EXTAL),
	56
	57	/* Internal Core Clocks */
	58	DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
	59	DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
	60	DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
	61
	62	DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
	63	DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
	64	DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
	65	DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
	66	DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
	67	DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
	68	DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
	69	DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
	70	DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
	71	DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
	72	DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
	73
4fc053f1	74	DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
ccc2c9aa	75
72242e54 MV	76	DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
	77
	78	DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
	79
f77b5a4c	80	/* Core Clock Outputs */
4fc053f1	81	DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
f77b5a4c MV	82	DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
	83	DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
	84	DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
	85	DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
	86	DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
	87	DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
	88	DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
	89	DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
	90	DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
	91	DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
	92	DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
	93	DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
	94	DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
	95	DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
	96
	97	DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
f7b4e4c0	98	DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
f77b5a4c	99	DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
72242e54 MV	100	DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
	101
	102	DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
f77b5a4c MV	103
	104	DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
	105	DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
	106	DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
	107	DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
	108
4fc053f1 MV	109	DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
	110	DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
	111
	112	DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
	113	DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
72242e54 MV	114
	115	DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
	116	DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
	117
	118	DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
f77b5a4c MV	119	};
f77b5a4c MV	120
501a4ebb	121	static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
f7b4e4c0 MV	122	DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
	123	DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
	124	DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
	125	DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
	126	DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
f77b5a4c MV	127	DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
	128	DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
	129	DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
	130	DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
	131	DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
	132	DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
	133	DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
	134	DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
	135	DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
	136	DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
	137	DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
	138	DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
f7b4e4c0	139	DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
f77b5a4c MV	140	DEF_MOD("cmt3", 300, R8A77995_CLK_R),
	141	DEF_MOD("cmt2", 301, R8A77995_CLK_R),
	142	DEF_MOD("cmt1", 302, R8A77995_CLK_R),
	143	DEF_MOD("cmt0", 303, R8A77995_CLK_R),
	144	DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
	145	DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
	146	DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
	147	DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
	148	DEF_MOD("rwdt", 402, R8A77995_CLK_R),
	149	DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
72242e54	150	DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
f7b4e4c0	151	DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
f77b5a4c MV	152	DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
	153	DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
	154	DEF_MOD("thermal", 522, R8A77995_CLK_CP),
	155	DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
	156	DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
	157	DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
	158	DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
	159	DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
	160	DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
	161	DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
	162	DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
	163	DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
f7b4e4c0 MV	164	DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
f7b4e4c0 MV	165	DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
72242e54 MV	166	DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
72242e54 MV	167	DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
f77b5a4c	168	DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
4fc053f1	169	DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
501a4ebb	170	DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
f77b5a4c MV	171	DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
	172	DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
	173	DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
	174	DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
	175	DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
	176	DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
	177	DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
	178	DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
	179	DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
	180	DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
	181	DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
	182	DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
4fc053f1	183	DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
f77b5a4c MV	184	DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
	185	DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
	186	DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
	187	DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
	188	DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
	189	DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
	190	DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
	191	DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
	192	DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
	193	DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
	194	DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
	195	DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
	196	DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
	197	DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
	198	};
	199
7c885563 MV	200	/*
	201	* CPG Clock Data
	202	*/
	203
	204	/*
	205	* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
	206	*--------------------------------------------------------------------
	207	* 0 48 x 1 x250/4 x100/3 x100/3
72242e54	208	* 1 48 x 1 x250/4 x100/3 x58/3
7c885563 MV	209	*/
	210	#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
	211
501a4ebb	212	static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
7c885563 MV	213	/* EXTAL div PLL1 mult/div PLL3 mult/div */
7c885563 MV	214	{ 1, 100, 3, 100, 3, },
72242e54	215	{ 1, 100, 3, 58, 3, },
7c885563 MV	216	};
7c885563 MV	217
f77b5a4c	218	static const struct mstp_stop_table r8a77995_mstp_table[] = {
3934b41b MV	219	{ 0x00210000, 0x0, 0x00210000, 0 },
	220	{ 0x03e01000, 0x0, 0x03e01000, 0 },
	221	{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
	222	{ 0xc00014df, 0x400, 0xc00014df, 0 },
	223	{ 0x80000004, 0x180, 0x80000004, 0 },
	224	{ 0x40d20004, 0x0, 0x40d20004, 0 },
	225	{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
	226	{ 0x09941c18, 0x0, 0x09941c18, 0 },
	227	{ 0x00801087, 0x0, 0x00801087, 0 },
	228	{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
	229	{ 0x063e1820, 0x0, 0x063e1820, 0 },
	230	{ 0x00000000, 0x0, 0x00000000, 0 },
f77b5a4c MV	231	};
f77b5a4c MV	232
7c885563 MV	233	static const void *r8a77995_get_pll_config(const u32 cpg_mode)
	234	{
	235	return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
	236	}
	237
f77b5a4c MV	238	static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
	239	.core_clk = r8a77995_core_clks,
	240	.core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
	241	.mod_clk = r8a77995_mod_clks,
	242	.mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
	243	.mstp_table = r8a77995_mstp_table,
	244	.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
	245	.reset_node = "renesas,r8a77995-rst",
e9354091	246	.reset_modemr_offset = CPG_RST_MODEMR,
f11c9679 MV	247	.mod_clk_base = MOD_CLK_BASE,
	248	.clk_extal_id = CLK_EXTAL,
	249	.clk_extalr_id = ~0,
7c885563	250	.get_pll_config = r8a77995_get_pll_config,
f77b5a4c MV	251	};
f77b5a4c MV	252
326e05c5	253	static const struct udevice_id r8a77995_cpg_ids[] = {
f77b5a4c MV	254	{
	255	.compatible = "renesas,r8a77995-cpg-mssr",
	256	.data = (ulong)&r8a77995_cpg_mssr_info
	257	},
	258	{ }
	259	};
	260
326e05c5 MV	261	U_BOOT_DRIVER(cpg_r8a77995) = {
	262	.name = "cpg_r8a77995",
	263	.id = UCLASS_NOP,
	264	.of_match = r8a77995_cpg_ids,
	265	.bind = gen3_cpg_bind,
f77b5a4c	266	};