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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
69018ce2 KG |
2 | /* |
3 | * Copyright 2008 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
69018ce2 KG |
7 | */ |
8 | ||
9 | #include <common.h> | |
401d1c4f | 10 | #include <asm/global_data.h> |
b08c8c48 | 11 | #include <linux/libfdt.h> |
69018ce2 | 12 | #include <fdt_support.h> |
2459afb1 | 13 | #include <fsl_qe.h> |
69018ce2 | 14 | |
93d33204 | 15 | #ifdef CONFIG_QE |
69018ce2 KG |
16 | DECLARE_GLOBAL_DATA_PTR; |
17 | ||
18 | /* | |
19 | * If a QE firmware has been uploaded, then add the 'firmware' node under | |
20 | * the 'qe' node. | |
21 | */ | |
22 | void fdt_fixup_qe_firmware(void *blob) | |
23 | { | |
24 | struct qe_firmware_info *qe_fw_info; | |
25 | int node, ret; | |
26 | ||
27 | qe_fw_info = qe_get_firmware_info(); | |
28 | if (!qe_fw_info) | |
29 | return; | |
30 | ||
31 | node = fdt_path_offset(blob, "/qe"); | |
32 | if (node < 0) | |
33 | return; | |
34 | ||
35 | /* We assume the node doesn't exist yet */ | |
36 | node = fdt_add_subnode(blob, node, "firmware"); | |
37 | if (node < 0) | |
38 | return; | |
39 | ||
40 | ret = fdt_setprop(blob, node, "extended-modes", | |
41 | &qe_fw_info->extended_modes, sizeof(u64)); | |
42 | if (ret < 0) | |
43 | goto error; | |
44 | ||
45 | ret = fdt_setprop_string(blob, node, "id", qe_fw_info->id); | |
46 | if (ret < 0) | |
47 | goto error; | |
48 | ||
49 | ret = fdt_setprop(blob, node, "virtual-traps", qe_fw_info->vtraps, | |
50 | sizeof(qe_fw_info->vtraps)); | |
51 | if (ret < 0) | |
52 | goto error; | |
53 | ||
54 | return; | |
55 | ||
56 | error: | |
57 | fdt_del_node(blob, node); | |
58 | } | |
59 | ||
60 | void ft_qe_setup(void *blob) | |
61 | { | |
69018ce2 | 62 | do_fixup_by_prop_u32(blob, "device_type", "qe", 4, |
45bae2e3 | 63 | "bus-frequency", gd->arch.qe_clk, 1); |
69018ce2 | 64 | do_fixup_by_prop_u32(blob, "device_type", "qe", 4, |
1206c184 | 65 | "brg-frequency", gd->arch.brg_clk, 1); |
69018ce2 | 66 | do_fixup_by_compat_u32(blob, "fsl,qe", |
45bae2e3 | 67 | "clock-frequency", gd->arch.qe_clk, 1); |
69018ce2 | 68 | do_fixup_by_compat_u32(blob, "fsl,qe", |
45bae2e3 | 69 | "bus-frequency", gd->arch.qe_clk, 1); |
69018ce2 | 70 | do_fixup_by_compat_u32(blob, "fsl,qe", |
1206c184 | 71 | "brg-frequency", gd->arch.brg_clk, 1); |
3fca8037 | 72 | do_fixup_by_compat_u32(blob, "fsl,qe-gtm", |
45bae2e3 | 73 | "clock-frequency", gd->arch.qe_clk / 2, 1); |
69018ce2 | 74 | fdt_fixup_qe_firmware(blob); |
69018ce2 | 75 | } |
93d33204 | 76 | #endif |