[J-u-boot.git] / drivers / pci_auto.c

/*
 * arch/ppc/kernel/pci_auto.c
 *
 * PCI autoconfiguration library
 *
 * Author: Matt Porter <[email protected]>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>

#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */

#define	PCIAUTO_IDE_MODE_MASK		0x05

/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CFG_PCI_CACHE_LINE_SIZE
#define CFG_PCI_CACHE_LINE_SIZE	8
#endif

/*
 *
 */

void pciauto_region_init(struct pci_region* res)
{
	/*
	 * Avoid allocating PCI resources from address 0 -- this is illegal
	 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
	 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
	 */
	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}

void pciauto_region_align(struct pci_region *res, unsigned long size)
{
	res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}

int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
{
	unsigned long addr;

	if (!res) {
		DEBUGF("No resource");
		goto error;
	}

	addr = ((res->bus_lower - 1) | (size - 1)) + 1;

	if (addr - res->bus_start + size > res->size) {
		DEBUGF("No room in resource");
		goto error;
	}

	res->bus_lower = addr + size;

	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);

	*bar = addr;
	return 0;

 error:
	*bar = 0xffffffff;
	return -1;
}

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *prefetch,
			  struct pci_region *io)
{
	unsigned int bar_value, bar_response, bar_size;
	unsigned int cmdstat = 0;
	struct pci_region *bar_res;
	int bar, bar_nr = 0;
	int found_mem64 = 0;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
		/* Tickle the BAR and get the response */
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
				   & 0xffff) + 1;
			bar_res = io;

			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
		} else {
			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
			if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
				bar_res = prefetch;
			else
				bar_res = mem;

			DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
		}

		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, bar_value);

			/*
			 * If we are a 64-bit decoder then increment to the
			 * upper 32 bits of the bar and force it to locate
			 * in the lower 4GB of memory.
			 */
			if (found_mem64) {
				bar += 4;
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
			}

			cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
				PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
		}

		DEBUGF("\n");

		bar_nr++;
	}

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
		CFG_PCI_CACHE_LINE_SIZE);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;
	unsigned int cmdstat;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
				   PCI_BUS(dev) - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
				   sub_bus - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
					(pci_prefetch->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	} else {
		/* We don't support prefetchable memory for now, so disable */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}

void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
				   sub_bus - hose->first_busno);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
					(pci_mem->bus_lower-1) >> 16);
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
					(pci_prefetch->bus_lower-1) >> 16);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
					((pci_io->bus_lower-1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
					((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	}
}

/*
 *
 */

void pciauto_config_init(struct pci_controller *hose)
{
	int i;

	hose->pci_io = hose->pci_mem = NULL;

	for (i=0; i<hose->region_count; i++) {
		switch(hose->regions[i].flags) {
		case PCI_REGION_IO:
			if (!hose->pci_io ||
			    hose->pci_io->size < hose->regions[i].size)
				hose->pci_io = hose->regions + i;
			break;
		case PCI_REGION_MEM:
			if (!hose->pci_mem ||
			    hose->pci_mem->size < hose->regions[i].size)
				hose->pci_mem = hose->regions + i;
			break;
		case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
			if (!hose->pci_prefetch ||
			    hose->pci_prefetch->size < hose->regions[i].size)
				hose->pci_prefetch = hose->regions + i;
			break;
		}
	}


	if (hose->pci_mem) {
		pciauto_region_init(hose->pci_mem);

		DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_mem->bus_start,
		    hose->pci_mem->bus_start + hose->pci_mem->size - 1,
		    hose->pci_mem->phys_start,
		    hose->pci_mem->phys_start + hose->pci_mem->size - 1);
	}

	if (hose->pci_prefetch) {
		pciauto_region_init(hose->pci_prefetch);

		DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_prefetch->bus_start,
		    hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
		    hose->pci_prefetch->phys_start,
		    hose->pci_prefetch->phys_start +
				hose->pci_prefetch->size - 1);
	}

	if (hose->pci_io) {
		pciauto_region_init(hose->pci_io);

		DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
		       "\t\tPhysical Memory: [%x-%x]\n",
		    hose->pci_io->bus_start,
		    hose->pci_io->bus_start + hose->pci_io->size - 1,
		    hose->pci_io->phys_start,
		    hose->pci_io->phys_start + hose->pci_io->size - 1);

	}
}

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	unsigned char prg_iface;
	int n;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch(class) {
	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
		DEBUGF("PCI AutoConfig: Found PowerPC device\n");
		pciauto_setup_device(hose, dev, 6, hose->pci_mem,
				     hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_PCI:
		hose->current_busno++;
		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));

		/* Passing in current_busno allows for sibling P2P bridges */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/*
		 * need to figure out if this is a subordinate bridge on the bus
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* figure out the deepest we've gone for this leg */
		sub_bus = max(n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_STORAGE_IDE:
		pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
		if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
			DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
			return sub_bus;
		}

		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/* just do a minimal setup of the bridge, let the OS take care of the rest */
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));

		hose->current_busno++;
		break;

#ifdef CONFIG_MPC5200
	case PCI_CLASS_BRIDGE_OTHER:
		DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
		       PCI_DEV(dev));
		break;
#endif
#ifdef CONFIG_MPC834X
	case PCI_CLASS_BRIDGE_OTHER:
		/*
		 * The host/PCI bridge 1 seems broken in 8349 - it presents
		 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
		 * device claiming resources io/mem/irq.. we only allow for
		 * the PIMMR window to be allocated (BAR0 - 1MB size)
		 */
		DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
#endif
	default:
		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
	}

	return sub_bus;
}

#endif /* CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*
	2	* arch/ppc/kernel/pci_auto.c
	3	*
	4	* PCI autoconfiguration library
	5	*
	6	* Author: Matt Porter <[email protected]>
	7	*
	8	* Copyright 2000 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <common.h>
	17
	18	#ifdef CONFIG_PCI
	19
	20	#include <pci.h>
	21
	22	#undef DEBUG
	23	#ifdef DEBUG
	24	#define DEBUGF(x...) printf(x)
	25	#else
	26	#define DEBUGF(x...)
	27	#endif /* DEBUG */
	28
	29	#define PCIAUTO_IDE_MODE_MASK 0x05
	30
81b73dec GJ	31	/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
	32	#ifndef CFG_PCI_CACHE_LINE_SIZE
	33	#define CFG_PCI_CACHE_LINE_SIZE 8
	34	#endif
	35
c609719b WD	36	/*
	37	*
	38	*/
	39
	40	void pciauto_region_init(struct pci_region* res)
	41	{
b7598a43 SS	42	/*
	43	* Avoid allocating PCI resources from address 0 -- this is illegal
	44	* according to PCI 2.1 and moreover, this is known to cause Linux IDE
	45	* drivers to fail. Use a reasonable starting value of 0x1000 instead.
	46	*/
	47	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
c609719b WD	48	}
	49
	50	void pciauto_region_align(struct pci_region *res, unsigned long size)
	51	{
	52	res->bus_lower = ((res->bus_lower - 1) \| (size - 1)) + 1;
	53	}
	54
	55	int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
	56	{
	57	unsigned long addr;
	58
3c74e32a	59	if (!res) {
c609719b WD	60	DEBUGF("No resource");
	61	goto error;
	62	}
	63
	64	addr = ((res->bus_lower - 1) \| (size - 1)) + 1;
	65
3c74e32a	66	if (addr - res->bus_start + size > res->size) {
c609719b WD	67	DEBUGF("No room in resource");
	68	goto error;
	69	}
	70
	71	res->bus_lower = addr + size;
	72
ba5feb12	73	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);
c609719b WD	74
	75	*bar = addr;
	76	return 0;
	77
	78	error:
	79	*bar = 0xffffffff;
	80	return -1;
	81	}
	82
	83	/*
	84	*
	85	*/
	86
	87	void pciauto_setup_device(struct pci_controller *hose,
	88	pci_dev_t dev, int bars_num,
	89	struct pci_region *mem,
a179012e	90	struct pci_region *prefetch,
c609719b WD	91	struct pci_region *io)
	92	{
	93	unsigned int bar_value, bar_response, bar_size;
	94	unsigned int cmdstat = 0;
	95	struct pci_region *bar_res;
	96	int bar, bar_nr = 0;
	97	int found_mem64 = 0;
	98
	99	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	100	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
	101
936b3e69	102	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
c609719b WD	103	/* Tickle the BAR and get the response */
	104	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
	105	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
	106
	107	/* If BAR is not implemented go to the next BAR */
	108	if (!bar_response)
	109	continue;
	110
	111	found_mem64 = 0;
	112
	113	/* Check the BAR type and set our address mask */
3c74e32a	114	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bd22c2b9 JZR	115	bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
bd22c2b9 JZR	116	& 0xffff) + 1;
c609719b WD	117	bar_res = io;
	118
	119	DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
3c74e32a	120	} else {
c609719b WD	121	if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
	122	PCI_BASE_ADDRESS_MEM_TYPE_64)
	123	found_mem64 = 1;
	124
	125	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
a179012e KG	126	if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
	127	bar_res = prefetch;
	128	else
	129	bar_res = mem;
c609719b WD	130
	131	DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
	132	}
	133
3c74e32a	134	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
c609719b WD	135	/* Write it out and update our limit */
	136	pci_hose_write_config_dword(hose, dev, bar, bar_value);
	137
	138	/*
	139	* If we are a 64-bit decoder then increment to the
	140	* upper 32 bits of the bar and force it to locate
	141	* in the lower 4GB of memory.
	142	*/
3c74e32a	143	if (found_mem64) {
c609719b WD	144	bar += 4;
	145	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
	146	}
	147
	148	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
	149	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
	150	}
	151
	152	DEBUGF("\n");
	153
	154	bar_nr++;
	155	}
	156
	157	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
81b73dec GJ	158	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
81b73dec GJ	159	CFG_PCI_CACHE_LINE_SIZE);
c609719b WD	160	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	161	}
	162
ba5feb12	163	void pciauto_prescan_setup_bridge(struct pci_controller *hose,
c609719b WD	164	pci_dev_t dev, int sub_bus)
	165	{
	166	struct pci_region *pci_mem = hose->pci_mem;
a179012e	167	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	168	struct pci_region *pci_io = hose->pci_io;
	169	unsigned int cmdstat;
	170
	171	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	172
	173	/* Configure bus number registers */
e8b85f3b ES	174	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
	175	PCI_BUS(dev) - hose->first_busno);
	176	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
	177	sub_bus - hose->first_busno);
c609719b WD	178	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
c609719b WD	179
3c74e32a	180	if (pci_mem) {
c609719b WD	181	/* Round memory allocator to 1MB boundary */
	182	pciauto_region_align(pci_mem, 0x100000);
	183
	184	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	185	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	186	(pci_mem->bus_lower & 0xfff00000) >> 16);
	187
	188	cmdstat \|= PCI_COMMAND_MEMORY;
	189	}
	190
a179012e KG	191	if (pci_prefetch) {
	192	/* Round memory allocator to 1MB boundary */
	193	pciauto_region_align(pci_prefetch, 0x100000);
	194
	195	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	196	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
	197	(pci_prefetch->bus_lower & 0xfff00000) >> 16);
	198
	199	cmdstat \|= PCI_COMMAND_MEMORY;
	200	} else {
	201	/* We don't support prefetchable memory for now, so disable */
	202	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
a4e11558	203	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
a179012e KG	204	}
a179012e KG	205
3c74e32a	206	if (pci_io) {
c609719b WD	207	/* Round I/O allocator to 4KB boundary */
	208	pciauto_region_align(pci_io, 0x1000);
	209
	210	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	211	(pci_io->bus_lower & 0x0000f000) >> 8);
	212	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	213	(pci_io->bus_lower & 0xffff0000) >> 16);
	214
	215	cmdstat \|= PCI_COMMAND_IO;
	216	}
	217
c609719b WD	218	/* Enable memory and I/O accesses, enable bus master */
	219	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat \| PCI_COMMAND_MASTER);
	220	}
	221
ba5feb12	222	void pciauto_postscan_setup_bridge(struct pci_controller *hose,
c609719b WD	223	pci_dev_t dev, int sub_bus)
	224	{
	225	struct pci_region *pci_mem = hose->pci_mem;
a179012e	226	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	227	struct pci_region *pci_io = hose->pci_io;
	228
	229	/* Configure bus number registers */
e8b85f3b ES	230	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
e8b85f3b ES	231	sub_bus - hose->first_busno);
c609719b	232
3c74e32a	233	if (pci_mem) {
c609719b WD	234	/* Round memory allocator to 1MB boundary */
	235	pciauto_region_align(pci_mem, 0x100000);
	236
	237	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
	238	(pci_mem->bus_lower-1) >> 16);
	239	}
	240
a179012e KG	241	if (pci_prefetch) {
	242	/* Round memory allocator to 1MB boundary */
	243	pciauto_region_align(pci_prefetch, 0x100000);
	244
	245	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
	246	(pci_prefetch->bus_lower-1) >> 16);
	247	}
	248
3c74e32a	249	if (pci_io) {
c609719b WD	250	/* Round I/O allocator to 4KB boundary */
	251	pciauto_region_align(pci_io, 0x1000);
	252
	253	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
	254	((pci_io->bus_lower-1) & 0x0000f000) >> 8);
	255	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
	256	((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	257	}
	258	}
	259
	260	/*
	261	*
	262	*/
	263
	264	void pciauto_config_init(struct pci_controller *hose)
	265	{
	266	int i;
	267
	268	hose->pci_io = hose->pci_mem = NULL;
	269
3c74e32a WD	270	for (i=0; i<hose->region_count; i++) {
3c74e32a WD	271	switch(hose->regions[i].flags) {
c609719b WD	272	case PCI_REGION_IO:
	273	if (!hose->pci_io \|\|
	274	hose->pci_io->size < hose->regions[i].size)
	275	hose->pci_io = hose->regions + i;
	276	break;
	277	case PCI_REGION_MEM:
	278	if (!hose->pci_mem \|\|
	279	hose->pci_mem->size < hose->regions[i].size)
	280	hose->pci_mem = hose->regions + i;
	281	break;
a179012e KG	282	case (PCI_REGION_MEM \| PCI_REGION_PREFETCH):
	283	if (!hose->pci_prefetch \|\|
	284	hose->pci_prefetch->size < hose->regions[i].size)
	285	hose->pci_prefetch = hose->regions + i;
	286	break;
c609719b WD	287	}
	288	}
	289
	290
3c74e32a	291	if (hose->pci_mem) {
c609719b WD	292	pciauto_region_init(hose->pci_mem);
c609719b WD	293
ba5feb12 ES	294	DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
ba5feb12 ES	295	"\t\tPhysical Memory [%x-%x]\n",
c609719b	296	hose->pci_mem->bus_start,
ba5feb12 ES	297	hose->pci_mem->bus_start + hose->pci_mem->size - 1,
	298	hose->pci_mem->phys_start,
	299	hose->pci_mem->phys_start + hose->pci_mem->size - 1);
c609719b WD	300	}
c609719b WD	301
a179012e KG	302	if (hose->pci_prefetch) {
	303	pciauto_region_init(hose->pci_prefetch);
	304
ba5feb12 ES	305	DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
ba5feb12 ES	306	"\t\tPhysical Memory [%x-%x]\n",
a179012e	307	hose->pci_prefetch->bus_start,
ba5feb12 ES	308	hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
	309	hose->pci_prefetch->phys_start,
	310	hose->pci_prefetch->phys_start +
	311	hose->pci_prefetch->size - 1);
a179012e KG	312	}
a179012e KG	313
3c74e32a	314	if (hose->pci_io) {
c609719b WD	315	pciauto_region_init(hose->pci_io);
c609719b WD	316
ba5feb12 ES	317	DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
ba5feb12 ES	318	"\t\tPhysical Memory: [%x-%x]\n",
c609719b	319	hose->pci_io->bus_start,
ba5feb12 ES	320	hose->pci_io->bus_start + hose->pci_io->size - 1,
	321	hose->pci_io->phys_start,
	322	hose->pci_io->phys_start + hose->pci_io->size - 1);
	323
c609719b WD	324	}
	325	}
	326
c7de829c WD	327	/* HJF: Changed this to return int. I think this is required
	328	* to get the correct result when scanning bridges
	329	*/
	330	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	331	{
c7de829c	332	unsigned int sub_bus = PCI_BUS(dev);
c609719b WD	333	unsigned short class;
c609719b WD	334	unsigned char prg_iface;
5653fc33	335	int n;
c609719b WD	336
	337	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	338
3c74e32a	339	switch(class) {
5dc210de ES	340	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
	341	DEBUGF("PCI AutoConfig: Found PowerPC device\n");
	342	pciauto_setup_device(hose, dev, 6, hose->pci_mem,
	343	hose->pci_prefetch, hose->pci_io);
	344	break;
	345
c609719b	346	case PCI_CLASS_BRIDGE_PCI:
db2f721f	347	hose->current_busno++;
a179012e	348	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b	349
db2f721f	350	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
cd37d9e6	351
3c74e32a	352	/* Passing in current_busno allows for sibling P2P bridges */
5653fc33	353	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
cd37d9e6	354	/*
3c74e32a	355	* need to figure out if this is a subordinate bridge on the bus
5653fc33 WD	356	* to be able to properly set the pri/sec/sub bridge registers.
	357	*/
	358	n = pci_hose_scan_bus(hose, hose->current_busno);
	359
3c74e32a	360	/* figure out the deepest we've gone for this leg */
5653fc33	361	sub_bus = max(n, sub_bus);
db2f721f	362	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	363
db2f721f	364	sub_bus = hose->current_busno;
c609719b WD	365	break;
	366
	367	case PCI_CLASS_STORAGE_IDE:
	368	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
3c74e32a WD	369	if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
	370	DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
	371	return sub_bus;
	372	}
c609719b	373
a179012e	374	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	375	break;
c609719b WD	376
1cb8e980 WD	377	case PCI_CLASS_BRIDGE_CARDBUS:
1cb8e980 WD	378	/* just do a minimal setup of the bridge, let the OS take care of the rest */
a179012e	379	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
1cb8e980	380
3c74e32a	381	DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
1cb8e980 WD	382
	383	hose->current_busno++;
	384	break;
	385
e0ac62d7 WD	386	#ifdef CONFIG_MPC5200
	387	case PCI_CLASS_BRIDGE_OTHER:
	388	DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
	389	PCI_DEV(dev));
	390	break;
	391	#endif
6902df56 RJ	392	#ifdef CONFIG_MPC834X
	393	case PCI_CLASS_BRIDGE_OTHER:
	394	/*
	395	* The host/PCI bridge 1 seems broken in 8349 - it presents
	396	* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
	397	* device claiming resources io/mem/irq.. we only allow for
	398	* the PIMMR window to be allocated (BAR0 - 1MB size)
	399	*/
	400	DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
a179012e	401	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
6902df56 RJ	402	break;
6902df56 RJ	403	#endif
c609719b	404	default:
a179012e	405	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	406	break;
c609719b WD	407	}
c7de829c WD	408
c7de829c WD	409	return sub_bus;
c609719b WD	410	}
	411
	412	#endif /* CONFIG_PCI */