[J-u-boot.git] / drivers / block / pata_bfin.h

/*
 * Driver for Blackfin on-chip ATAPI controller.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Copyright (c) 2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef PATA_BFIN_H
#define PATA_BFIN_H

#include <asm/blackfin_local.h>

struct ata_ioports {
	unsigned long cmd_addr;
	unsigned long data_addr;
	unsigned long error_addr;
	unsigned long feature_addr;
	unsigned long nsect_addr;
	unsigned long lbal_addr;
	unsigned long lbam_addr;
	unsigned long lbah_addr;
	unsigned long device_addr;
	unsigned long status_addr;
	unsigned long command_addr;
	unsigned long altstatus_addr;
	unsigned long ctl_addr;
	unsigned long bmdma_addr;
	unsigned long scr_addr;
};

struct ata_port {
	unsigned int port_no;		/* primary=0, secondary=1       */
	struct ata_ioports ioaddr;	/* ATA cmd/ctl/dma reg blks     */
	unsigned long flag;
	unsigned int ata_mode;
	unsigned char ctl_reg;
	unsigned char last_ctl;
	unsigned char dev_mask;
};

#define DRV_NAME		"pata-bfin"
#define DRV_VERSION		"0.9"

#define ATA_REG_CTRL		0x0E
#define ATA_REG_ALTSTATUS	ATA_REG_CTRL
#define ATA_TMOUT_BOOT		30000
#define ATA_TMOUT_BOOT_QUICK	7000

#define PATA_BFIN_WAIT_TIMEOUT		10000
#define PATA_DEV_NUM_PER_PORT	2

/* These are the offset of the controller's registers */
#define ATAPI_OFFSET_CONTROL		0x00
#define ATAPI_OFFSET_STATUS		0x04
#define ATAPI_OFFSET_DEV_ADDR		0x08
#define ATAPI_OFFSET_DEV_TXBUF		0x0c
#define ATAPI_OFFSET_DEV_RXBUF		0x10
#define ATAPI_OFFSET_INT_MASK		0x14
#define ATAPI_OFFSET_INT_STATUS		0x18
#define ATAPI_OFFSET_XFER_LEN		0x1c
#define ATAPI_OFFSET_LINE_STATUS	0x20
#define ATAPI_OFFSET_SM_STATE		0x24
#define ATAPI_OFFSET_TERMINATE		0x28
#define ATAPI_OFFSET_PIO_TFRCNT		0x2c
#define ATAPI_OFFSET_DMA_TFRCNT		0x30
#define ATAPI_OFFSET_UMAIN_TFRCNT	0x34
#define ATAPI_OFFSET_UDMAOUT_TFRCNT	0x38
#define ATAPI_OFFSET_REG_TIM_0		0x40
#define ATAPI_OFFSET_PIO_TIM_0		0x44
#define ATAPI_OFFSET_PIO_TIM_1		0x48
#define ATAPI_OFFSET_MULTI_TIM_0	0x50
#define ATAPI_OFFSET_MULTI_TIM_1	0x54
#define ATAPI_OFFSET_MULTI_TIM_2	0x58
#define ATAPI_OFFSET_ULTRA_TIM_0	0x60
#define ATAPI_OFFSET_ULTRA_TIM_1	0x64
#define ATAPI_OFFSET_ULTRA_TIM_2	0x68
#define ATAPI_OFFSET_ULTRA_TIM_3	0x6c


#define ATAPI_GET_CONTROL(base)\
	bfin_read16(base + ATAPI_OFFSET_CONTROL)
#define ATAPI_SET_CONTROL(base, val)\
	bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
#define ATAPI_GET_STATUS(base)\
	bfin_read16(base + ATAPI_OFFSET_STATUS)
#define ATAPI_GET_DEV_ADDR(base)\
	bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
#define ATAPI_SET_DEV_ADDR(base, val)\
	bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
#define ATAPI_GET_DEV_TXBUF(base)\
	bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
#define ATAPI_SET_DEV_TXBUF(base, val)\
	bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
#define ATAPI_GET_DEV_RXBUF(base)\
	bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
#define ATAPI_SET_DEV_RXBUF(base, val)\
	bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
#define ATAPI_GET_INT_MASK(base)\
	bfin_read16(base + ATAPI_OFFSET_INT_MASK)
#define ATAPI_SET_INT_MASK(base, val)\
	bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
#define ATAPI_GET_INT_STATUS(base)\
	bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
#define ATAPI_SET_INT_STATUS(base, val)\
	bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
#define ATAPI_GET_XFER_LEN(base)\
	bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
#define ATAPI_SET_XFER_LEN(base, val)\
	bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
#define ATAPI_GET_LINE_STATUS(base)\
	bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
#define ATAPI_GET_SM_STATE(base)\
	bfin_read16(base + ATAPI_OFFSET_SM_STATE)
#define ATAPI_GET_TERMINATE(base)\
	bfin_read16(base + ATAPI_OFFSET_TERMINATE)
#define ATAPI_SET_TERMINATE(base, val)\
	bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
#define ATAPI_GET_PIO_TFRCNT(base)\
	bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
#define ATAPI_GET_DMA_TFRCNT(base)\
	bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
#define ATAPI_GET_UMAIN_TFRCNT(base)\
	bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
	bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
#define ATAPI_GET_REG_TIM_0(base)\
	bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
#define ATAPI_SET_REG_TIM_0(base, val)\
	bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
#define ATAPI_GET_PIO_TIM_0(base)\
	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
#define ATAPI_SET_PIO_TIM_0(base, val)\
	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
#define ATAPI_GET_PIO_TIM_1(base)\
	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
#define ATAPI_SET_PIO_TIM_1(base, val)\
	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_0(base)\
	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
#define ATAPI_SET_MULTI_TIM_0(base, val)\
	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
#define ATAPI_GET_MULTI_TIM_1(base)\
	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
#define ATAPI_SET_MULTI_TIM_1(base, val)\
	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_2(base)\
	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
#define ATAPI_SET_MULTI_TIM_2(base, val)\
	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_0(base)\
	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
#define ATAPI_SET_ULTRA_TIM_0(base, val)\
	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
#define ATAPI_GET_ULTRA_TIM_1(base)\
	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
#define ATAPI_SET_ULTRA_TIM_1(base, val)\
	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
#define ATAPI_GET_ULTRA_TIM_2(base)\
	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
#define ATAPI_SET_ULTRA_TIM_2(base, val)\
	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_3(base)\
	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
#define ATAPI_SET_ULTRA_TIM_3(base, val)\
	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)

#endif
Commit	Line	Data
8a6b2725 SZ	1	/*
	2	* Driver for Blackfin on-chip ATAPI controller.
	3	*
	4	* Enter bugs at http://blackfin.uclinux.org/
	5	*
	6	* Copyright (c) 2008 Analog Devices Inc.
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#ifndef PATA_BFIN_H
	12	#define PATA_BFIN_H
	13
	14	#include <asm/blackfin_local.h>
	15
	16	struct ata_ioports {
	17	unsigned long cmd_addr;
	18	unsigned long data_addr;
	19	unsigned long error_addr;
	20	unsigned long feature_addr;
	21	unsigned long nsect_addr;
	22	unsigned long lbal_addr;
	23	unsigned long lbam_addr;
	24	unsigned long lbah_addr;
	25	unsigned long device_addr;
	26	unsigned long status_addr;
	27	unsigned long command_addr;
	28	unsigned long altstatus_addr;
	29	unsigned long ctl_addr;
	30	unsigned long bmdma_addr;
	31	unsigned long scr_addr;
	32	};
	33
	34	struct ata_port {
	35	unsigned int port_no; /* primary=0, secondary=1 */
	36	struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
	37	unsigned long flag;
	38	unsigned int ata_mode;
	39	unsigned char ctl_reg;
	40	unsigned char last_ctl;
	41	unsigned char dev_mask;
	42	};
	43
8a6b2725 SZ	44	#define DRV_NAME "pata-bfin"
8a6b2725 SZ	45	#define DRV_VERSION "0.9"
8a6b2725 SZ	46
	47	#define ATA_REG_CTRL 0x0E
	48	#define ATA_REG_ALTSTATUS ATA_REG_CTRL
	49	#define ATA_TMOUT_BOOT 30000
	50	#define ATA_TMOUT_BOOT_QUICK 7000
	51
	52	#define PATA_BFIN_WAIT_TIMEOUT 10000
	53	#define PATA_DEV_NUM_PER_PORT 2
	54
	55	/* These are the offset of the controller's registers */
	56	#define ATAPI_OFFSET_CONTROL 0x00
	57	#define ATAPI_OFFSET_STATUS 0x04
	58	#define ATAPI_OFFSET_DEV_ADDR 0x08
	59	#define ATAPI_OFFSET_DEV_TXBUF 0x0c
	60	#define ATAPI_OFFSET_DEV_RXBUF 0x10
	61	#define ATAPI_OFFSET_INT_MASK 0x14
	62	#define ATAPI_OFFSET_INT_STATUS 0x18
	63	#define ATAPI_OFFSET_XFER_LEN 0x1c
	64	#define ATAPI_OFFSET_LINE_STATUS 0x20
	65	#define ATAPI_OFFSET_SM_STATE 0x24
	66	#define ATAPI_OFFSET_TERMINATE 0x28
	67	#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
	68	#define ATAPI_OFFSET_DMA_TFRCNT 0x30
	69	#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
	70	#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
	71	#define ATAPI_OFFSET_REG_TIM_0 0x40
	72	#define ATAPI_OFFSET_PIO_TIM_0 0x44
	73	#define ATAPI_OFFSET_PIO_TIM_1 0x48
	74	#define ATAPI_OFFSET_MULTI_TIM_0 0x50
	75	#define ATAPI_OFFSET_MULTI_TIM_1 0x54
	76	#define ATAPI_OFFSET_MULTI_TIM_2 0x58
	77	#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
	78	#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
	79	#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
	80	#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
	81
	82
	83	#define ATAPI_GET_CONTROL(base)\
	84	bfin_read16(base + ATAPI_OFFSET_CONTROL)
	85	#define ATAPI_SET_CONTROL(base, val)\
	86	bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
	87	#define ATAPI_GET_STATUS(base)\
	88	bfin_read16(base + ATAPI_OFFSET_STATUS)
	89	#define ATAPI_GET_DEV_ADDR(base)\
	90	bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
	91	#define ATAPI_SET_DEV_ADDR(base, val)\
	92	bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
	93	#define ATAPI_GET_DEV_TXBUF(base)\
	94	bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
	95	#define ATAPI_SET_DEV_TXBUF(base, val)\
	96	bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
	97	#define ATAPI_GET_DEV_RXBUF(base)\
	98	bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
	99	#define ATAPI_SET_DEV_RXBUF(base, val)\
	100	bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
	101	#define ATAPI_GET_INT_MASK(base)\
	102	bfin_read16(base + ATAPI_OFFSET_INT_MASK)
	103	#define ATAPI_SET_INT_MASK(base, val)\
	104	bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
	105	#define ATAPI_GET_INT_STATUS(base)\
	106	bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
	107	#define ATAPI_SET_INT_STATUS(base, val)\
	108	bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
	109	#define ATAPI_GET_XFER_LEN(base)\
110	bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
111	#define ATAPI_SET_XFER_LEN(base, val)\
112	bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
113	#define ATAPI_GET_LINE_STATUS(base)\
114	bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
115	#define ATAPI_GET_SM_STATE(base)\
116	bfin_read16(base + ATAPI_OFFSET_SM_STATE)
117	#define ATAPI_GET_TERMINATE(base)\
118	bfin_read16(base + ATAPI_OFFSET_TERMINATE)
119	#define ATAPI_SET_TERMINATE(base, val)\
120	bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
121	#define ATAPI_GET_PIO_TFRCNT(base)\
122	bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
123	#define ATAPI_GET_DMA_TFRCNT(base)\
124	bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
125	#define ATAPI_GET_UMAIN_TFRCNT(base)\
126	bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
127	#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
128	bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
129	#define ATAPI_GET_REG_TIM_0(base)\
130	bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
131	#define ATAPI_SET_REG_TIM_0(base, val)\
132	bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
133	#define ATAPI_GET_PIO_TIM_0(base)\
134	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
135	#define ATAPI_SET_PIO_TIM_0(base, val)\
136	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
137	#define ATAPI_GET_PIO_TIM_1(base)\
138	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
139	#define ATAPI_SET_PIO_TIM_1(base, val)\
140	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
141	#define ATAPI_GET_MULTI_TIM_0(base)\
142	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
143	#define ATAPI_SET_MULTI_TIM_0(base, val)\
144	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
145	#define ATAPI_GET_MULTI_TIM_1(base)\
146	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
147	#define ATAPI_SET_MULTI_TIM_1(base, val)\
148	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
149	#define ATAPI_GET_MULTI_TIM_2(base)\
150	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
151	#define ATAPI_SET_MULTI_TIM_2(base, val)\
152	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
153	#define ATAPI_GET_ULTRA_TIM_0(base)\
154	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
155	#define ATAPI_SET_ULTRA_TIM_0(base, val)\
156	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
157	#define ATAPI_GET_ULTRA_TIM_1(base)\
158	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
159	#define ATAPI_SET_ULTRA_TIM_1(base, val)\
160	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
161	#define ATAPI_GET_ULTRA_TIM_2(base)\
162	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
163	#define ATAPI_SET_ULTRA_TIM_2(base, val)\
164	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
165	#define ATAPI_GET_ULTRA_TIM_3(base)\
166	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
167	#define ATAPI_SET_ULTRA_TIM_3(base, val)\
168	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
169
170	#endif