[J-u-boot.git] / include / configs / MPC8568MDS.h

/*
 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8568mds board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DISPLAY_BOARDINFO

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC8568		1	/* MPC8568 specific */
#define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */

#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCI1		1	/* PCI controller */
#define CONFIG_PCIE1		1	/* PCIE controller */
#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_QE			/* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
#define CONFIG_BTB				/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1


#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */

#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */
#define CONFIG_SYS_BCSR_BASE		0xf8000000

#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */

/*Chip select 0 - Flash*/
#define CONFIG_SYS_BR0_PRELIM		0xfe001001
#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7

/*Chip slelect 1 - BCSR*/
#define CONFIG_SYS_BR1_PRELIM		0xf8000801
#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7

/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO


/*
 * SDRAM on the LocalBus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */


/*Chip select 2 - SDRAM*/
#define CONFIG_SYS_BR2_PRELIM      0xf0001861
#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The bcsr registers are connected to CS3 on MDS.
 * The new memory map places bcsr at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */
#define CONFIG_SYS_BCSR (0xf8000000)

/*Chip slelect 4 - PIB*/
#define CONFIG_SYS_BR4_PRELIM   0xf8008801
#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7

/*Chip select 5 - PIB*/
#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser*/
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52

/*
 * General PCI
 * Memory Addresses are mapped 1-1. I/O is mapped from 0
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_PCIE1_NAME		"Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_QE
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME         "UEC0"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS

#ifdef CONFIG_eTSEC_MDIO_BUS
#define CONFIG_MIIM_ADDRESS	0xE0024520
#endif

#define CONFIG_UEC_ETH1         /* GETH1 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR       7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif

#define CONFIG_UEC_ETH2         /* GETH2 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR       1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
#endif /* CONFIG_QE */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  "/nfsroot"
#define CONFIG_BOOTFILE  "your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"						\
   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs\0"			\
   "ramargs=setenv bootargs root=/dev/ram rw "				\
      "console=$consoledev,$baudrate $othbootargs\0"			\


#define CONFIG_NFSBOOTCOMMAND	                                        \
   "run nfsargs;"							\
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"


#define CONFIG_RAMBOOTCOMMAND \
   "run ramargs;"							\
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
67431059	1	/*
5f7bbd13	2	* Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
67431059	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
67431059 AF	5	*/
	6
	7	/*
	8	* mpc8568mds board configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
9ae14ca2 YS	13	#define CONFIG_DISPLAY_BOARDINFO
9ae14ca2 YS	14
67431059 AF	15	/* High Level Configuration Options */
67431059 AF	16	#define CONFIG_BOOKE 1 /* BOOKE */
da9d4610	17	#define CONFIG_E500 1 /* BOOKE e500 family */
67431059 AF	18	#define CONFIG_MPC8568 1 /* MPC8568 specific */
	19	#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
	20
2ae18241 WD	21	#define CONFIG_SYS_TEXT_BASE 0xfff80000
2ae18241 WD	22
5f7bbd13 KG	23	#define CONFIG_SYS_SRIO
	24	#define CONFIG_SRIO1 /* SRIO port 1 */
	25
1563f56e HW	26	#define CONFIG_PCI 1 /* Enable PCI/PCIE */
	27	#define CONFIG_PCI1 1 /* PCI controller */
	28	#define CONFIG_PCIE1 1 /* PCIE controller */
	29	#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
842033e6	30	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
8ff3de61	31	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac	32	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	33	#define CONFIG_TSEC_ENET /* tsec ethernet support */
b96c83d4	34	#define CONFIG_QE /* Enable QE */
67431059	35	#define CONFIG_ENV_OVERWRITE
4d3521cc	36	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
67431059	37
67431059 AF	38	#ifndef __ASSEMBLY__
	39	extern unsigned long get_clock_freq(void);
	40	#endif /Replace a call to get_clock_freq (after it is implemented)/
	41	#define CONFIG_SYS_CLK_FREQ 66000000 /TODO: restore if wanting to read from BCSR: get_clock_freq()/ /* sysclk for MPC85xx */
	42
	43	/*
	44	* These can be toggled for performance analysis, otherwise use default.
	45	*/
53677ef1	46	#define CONFIG_L2_CACHE /* toggle L2 cache */
7a1ac419	47	#define CONFIG_BTB /* toggle branch predition */
67431059 AF	48
	49	/*
	50	* Only possible on E500 Version 2 or newer cores.
	51	*/
	52	#define CONFIG_ENABLE_36BIT_PHYS 1
	53
	54
	55	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	56
6d0f6bcf JCPV	57	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	58	#define CONFIG_SYS_MEMTEST_END 0x00400000
67431059	59
e46fedfe TT	60	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	61	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
67431059	62
e6f5b35b	63	/* DDR Setup */
5614e71b	64	#define CONFIG_SYS_FSL_DDR2
e6f5b35b JL	65	#undef CONFIG_FSL_DDR_INTERACTIVE
	66	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	67	#define CONFIG_DDR_SPD
9b0ad1b1	68	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
e6f5b35b JL	69
	70	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	73	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67431059	74
e6f5b35b JL	75	#define CONFIG_NUM_DDR_CONTROLLERS 1
	76	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	77	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
67431059	78
e6f5b35b JL	79	/* I2C addresses of SPD EEPROMs */
	80	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	81
	82	/* Make sure required options are set */
67431059 AF	83	#ifndef CONFIG_SPD_EEPROM
	84	#error ("CONFIG_SPD_EEPROM is required")
	85	#endif
	86
	87	#undef CONFIG_CLOCKS_IN_MHZ
	88
67431059 AF	89	/*
	90	* Local Bus Definitions
	91	*/
	92
	93	/*
	94	* FLASH on the Local Bus
	95	* Two banks, 8M each, using the CFI driver.
	96	* Boot from BR0/OR0 bank at 0xff00_0000
	97	* Alternate BR1/OR1 bank at 0xff80_0000
	98	*
	99	* BR0, BR1:
	100	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	101	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	102	* Port Size = 16 bits = BRx[19:20] = 10
	103	* Use GPCM = BRx[24:26] = 000
	104	* Valid = BRx[31] = 1
	105	*
	106	* 0 4 8 12 16 20 24 28
	107	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	108	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	109	*
	110	* OR0, OR1:
	111	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	112	* Reserved ORx[17:18] = 11, confusion here?
	113	* CSNT = ORx[20] = 1
	114	* ACS = half cycle delay = ORx[21:22] = 11
	115	* SCY = 6 = ORx[24:27] = 0110
	116	* TRLX = use relaxed timing = ORx[29] = 1
	117	* EAD = use external address latch delay = OR[31] = 1
	118	*
	119	* 0 4 8 12 16 20 24 28
	120	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	121	*/
6d0f6bcf	122	#define CONFIG_SYS_BCSR_BASE 0xf8000000
67431059	123
6d0f6bcf	124	#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
67431059 AF	125
67431059 AF	126	/Chip select 0 - Flash/
6d0f6bcf JCPV	127	#define CONFIG_SYS_BR0_PRELIM 0xfe001001
6d0f6bcf JCPV	128	#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
67431059 AF	129
67431059 AF	130	/Chip slelect 1 - BCSR/
6d0f6bcf JCPV	131	#define CONFIG_SYS_BR1_PRELIM 0xf8000801
6d0f6bcf JCPV	132	#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
67431059	133
6d0f6bcf JCPV	134	/#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} /
	135	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	136	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	137	#undef CONFIG_SYS_FLASH_CHECKSUM
	138	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	139	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
67431059	140
14d0a02a	141	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
67431059	142
00b1883a	143	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	144	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	145	#define CONFIG_SYS_FLASH_EMPTY_INFO
67431059 AF	146
	147
	148	/*
	149	* SDRAM on the LocalBus
	150	*/
6d0f6bcf JCPV	151	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	152	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
67431059 AF	153
	154
	155	/Chip select 2 - SDRAM/
6d0f6bcf JCPV	156	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
6d0f6bcf JCPV	157	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
67431059	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	160	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	161	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	162	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
67431059	163
67431059 AF	164	/*
	165	* Common settings for all Local Bus SDRAM commands.
	166	* At run time, either BSMA1516 (for CPU 1.1)
	167	* or BSMA1617 (for CPU 1.0) (old)
	168	* is OR'ed in too.
	169	*/
b0fe93ed KG	170	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	171	\| LSDMR_PRETOACT7 \
	172	\| LSDMR_ACTTORW7 \
	173	\| LSDMR_BL8 \
	174	\| LSDMR_WRC4 \
	175	\| LSDMR_CL3 \
	176	\| LSDMR_RFEN \
67431059 AF	177	)
	178
	179	/*
	180	* The bcsr registers are connected to CS3 on MDS.
	181	* The new memory map places bcsr at 0xf8000000.
	182	*
	183	* For BR3, need:
	184	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	185	* port-size = 8-bits = BR[19:20] = 01
	186	* no parity checking = BR[21:22] = 00
	187	* GPMC for MSEL = BR[24:26] = 000
	188	* Valid = BR[31] = 1
	189	*
	190	* 0 4 8 12 16 20 24 28
	191	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	192	*
	193	* For OR3, need:
	194	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
	195	* disable buffer ctrl OR[19] = 0
	196	* CSNT OR[20] = 1
	197	* ACS OR[21:22] = 11
	198	* XACS OR[23] = 1
	199	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
	200	* SETA OR[28] = 0
	201	* TRLX OR[29] = 1
	202	* EHTR OR[30] = 1
	203	* EAD extra time OR[31] = 1
	204	*
	205	* 0 4 8 12 16 20 24 28
	206	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_BCSR (0xf8000000)
67431059 AF	209
67431059 AF	210	/Chip slelect 4 - PIB/
6d0f6bcf JCPV	211	#define CONFIG_SYS_BR4_PRELIM 0xf8008801
6d0f6bcf JCPV	212	#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
67431059 AF	213
67431059 AF	214	/Chip select 5 - PIB/
6d0f6bcf JCPV	215	#define CONFIG_SYS_BR5_PRELIM 0xf8010801
6d0f6bcf JCPV	216	#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
67431059	217
6d0f6bcf JCPV	218	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	219	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	220	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
67431059	221
25ddd1fb	222	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	223	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
67431059	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	226	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
67431059 AF	227
	228	/* Serial Port */
	229	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	230	#define CONFIG_SYS_NS16550_SERIAL
	231	#define CONFIG_SYS_NS16550_REG_SIZE 1
	232	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
67431059	233
6d0f6bcf	234	#define CONFIG_SYS_BAUDRATE_TABLE \
67431059 AF	235	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
67431059 AF	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	238	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
67431059 AF	239
67431059 AF	240	/* Use the HUSH parser*/
6d0f6bcf JCPV	241	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	242	#ifdef CONFIG_SYS_HUSH_PARSER
67431059 AF	243	#endif
	244
	245	/* pass open firmware flat tree */
c480861b KG	246	#define CONFIG_OF_BOARD_SETUP 1
c480861b KG	247	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
67431059 AF	248
	249	/*
	250	* I2C
	251	*/
00f792e0 HS	252	#define CONFIG_SYS_I2C
	253	#define CONFIG_SYS_I2C_FSL
	254	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	255	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	256	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	257	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	258	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	259	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	260	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
6d0f6bcf	261	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
67431059 AF	262
	263	/*
	264	* General PCI
	265	* Memory Addresses are mapped 1-1. I/O is mapped from 0
	266	*/
5af0fdd8	267	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	268	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	269	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	270	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	271	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	272	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	273	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	274	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
	275
3f6f9d76	276	#define CONFIG_SYS_PCIE1_NAME "Slot"
5af0fdd8	277	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42	278	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	279	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	280	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	281	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
5f91ef6a	282	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	283	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
	284	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
	285
5f7bbd13 KG	286	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
	287	#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
	288	#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
	289	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
67431059	290
da9d4610 AF	291	#ifdef CONFIG_QE
	292	/*
	293	* QE UEC ethernet configuration
	294	*/
	295	#define CONFIG_UEC_ETH
	296	#ifndef CONFIG_TSEC_ENET
78b7a8ef	297	#define CONFIG_ETHPRIME "UEC0"
da9d4610 AF	298	#endif
	299	#define CONFIG_PHY_MODE_NEED_CHANGE
	300	#define CONFIG_eTSEC_MDIO_BUS
	301
	302	#ifdef CONFIG_eTSEC_MDIO_BUS
53677ef1	303	#define CONFIG_MIIM_ADDRESS 0xE0024520
da9d4610 AF	304	#endif
	305
	306	#define CONFIG_UEC_ETH1 /* GETH1 */
	307
	308	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	309	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	310	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
	311	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
	312	#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
	313	#define CONFIG_SYS_UEC1_PHY_ADDR 7
865ff856	314	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	315	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
da9d4610 AF	316	#endif
	317
	318	#define CONFIG_UEC_ETH2 /* GETH2 */
	319
	320	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	321	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	322	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
	323	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
	324	#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
	325	#define CONFIG_SYS_UEC2_PHY_ADDR 1
865ff856	326	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	327	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
da9d4610 AF	328	#endif
	329	#endif /* CONFIG_QE */
	330
f30ad49b HW	331	#if defined(CONFIG_PCI)
f30ad49b HW	332
53677ef1	333	#define CONFIG_PCI_PNP /* do pci plug-and-play */
f30ad49b	334
67431059 AF	335	#undef CONFIG_EEPRO100
	336	#undef CONFIG_TULIP
	337
	338	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	339	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
67431059 AF	340
	341	#endif /* CONFIG_PCI */
	342
da9d4610 AF	343	#if defined(CONFIG_TSEC_ENET)
da9d4610 AF	344
67431059	345	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	346	#define CONFIG_TSEC1 1
	347	#define CONFIG_TSEC1_NAME "eTSEC0"
	348	#define CONFIG_TSEC2 1
	349	#define CONFIG_TSEC2_NAME "eTSEC1"
67431059 AF	350
	351	#define TSEC1_PHY_ADDR 2
	352	#define TSEC2_PHY_ADDR 3
	353
	354	#define TSEC1_PHYIDX 0
	355	#define TSEC2_PHYIDX 0
	356
3a79013e AF	357	#define TSEC1_FLAGS TSEC_GIGABIT
	358	#define TSEC2_FLAGS TSEC_GIGABIT
	359
b96c83d4	360	/* Options are: eTSEC[0-1] */
67431059 AF	361	#define CONFIG_ETHPRIME "eTSEC0"
	362
	363	#endif /* CONFIG_TSEC_ENET */
	364
	365	/*
	366	* Environment
	367	*/
5a1aceb0	368	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	369	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	370	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	371	#define CONFIG_ENV_SIZE 0x2000
67431059 AF	372
67431059 AF	373	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	374	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
67431059	375
2835e518	376
079a136c JL	377	/*
	378	* BOOTP options
	379	*/
	380	#define CONFIG_BOOTP_BOOTFILESIZE
	381	#define CONFIG_BOOTP_BOOTPATH
	382	#define CONFIG_BOOTP_GATEWAY
	383	#define CONFIG_BOOTP_HOSTNAME
	384
	385
2835e518 JL	386	/*
	387	* Command line configuration.
	388	*/
2835e518 JL	389	#define CONFIG_CMD_PING
	390	#define CONFIG_CMD_I2C
	391	#define CONFIG_CMD_MII
1c9aa76b	392	#define CONFIG_CMD_IRQ
199e262e	393	#define CONFIG_CMD_REGINFO
2835e518	394
67431059	395	#if defined(CONFIG_PCI)
2835e518	396	#define CONFIG_CMD_PCI
67431059	397	#endif
2835e518	398
67431059 AF	399
	400	#undef CONFIG_WATCHDOG /* watchdog disabled */
	401
	402	/*
	403	* Miscellaneous configurable options
	404	*/
6d0f6bcf	405	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	406	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	407	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	408	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
2835e518	409	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	410	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
67431059	411	#else
6d0f6bcf	412	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
67431059	413	#endif
6d0f6bcf JCPV	414	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	415	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	416	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
67431059 AF	417
	418	/*
	419	* For booting Linux, the board info and command line data
a832ac41	420	* have to be in the first 64 MB of memory, since this is
67431059 AF	421	* the maximum mapped by the Linux kernel during initialization.
67431059 AF	422	*/
a832ac41 KG	423	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	424	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
67431059	425
2835e518	426	#if defined(CONFIG_CMD_KGDB)
67431059	427	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
67431059 AF	428	#endif
	429
	430	/*
	431	* Environment Configuration
	432	*/
	433
	434	/* The mac addresses for all ethernet interface */
da9d4610 AF	435	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_UEC_ETH)
da9d4610 AF	436	#define CONFIG_HAS_ETH0
67431059	437	#define CONFIG_HAS_ETH1
67431059	438	#define CONFIG_HAS_ETH2
da9d4610	439	#define CONFIG_HAS_ETH3
67431059 AF	440	#endif
	441
	442	#define CONFIG_IPADDR 192.168.1.253
	443
	444	#define CONFIG_HOSTNAME unknown
8b3637c6	445	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	446	#define CONFIG_BOOTFILE "your.uImage"
67431059 AF	447
	448	#define CONFIG_SERVERIP 192.168.1.1
	449	#define CONFIG_GATEWAYIP 192.168.1.1
	450	#define CONFIG_NETMASK 255.255.255.0
	451
	452	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	453
	454	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	455	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	456
	457	#define CONFIG_BAUDRATE 115200
	458
	459	#define CONFIG_EXTRA_ENV_SETTINGS \
	460	"netdev=eth0\0" \
	461	"consoledev=ttyS0\0" \
	462	"ramdiskaddr=600000\0" \
	463	"ramdiskfile=your.ramdisk.u-boot\0" \
	464	"fdtaddr=400000\0" \
	465	"fdtfile=your.fdt.dtb\0" \
	466	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	467	"nfsroot=$serverip:$rootpath " \
	468	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	469	"console=$consoledev,$baudrate $othbootargs\0" \
	470	"ramargs=setenv bootargs root=/dev/ram rw " \
	471	"console=$consoledev,$baudrate $othbootargs\0" \
	472
	473
	474	#define CONFIG_NFSBOOTCOMMAND \
	475	"run nfsargs;" \
	476	"tftp $loadaddr $bootfile;" \
	477	"tftp $fdtaddr $fdtfile;" \
	478	"bootm $loadaddr - $fdtaddr"
	479
	480
	481	#define CONFIG_RAMBOOTCOMMAND \
	482	"run ramargs;" \
	483	"tftp $ramdiskaddr $ramdiskfile;" \
	484	"tftp $loadaddr $bootfile;" \
	485	"bootm $loadaddr $ramdiskaddr"
	486
	487	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	488
	489	#endif /* __CONFIG_H */