[J-u-boot.git] / drivers / timer / cadence-ttc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <asm/io.h>

#define CNT_CNTRL_RESET		BIT(4)

struct cadence_ttc_regs {
	u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
	u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
	u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
	u32 counter_cntrl1; /* 0xC - Counter Control 1 */
	u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
	u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
	u32 counter_val1; /* 0x18 - Counter Control 1 */
	u32 counter_val2; /* 0x1C - Counter Control 2 */
	u32 counter_val3; /* 0x20 - Counter Control 3 */
	u32 reserved[15];
	u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
	u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
	u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
};

struct cadence_ttc_priv {
	struct cadence_ttc_regs *regs;
};

#if CONFIG_IS_ENABLED(BOOTSTAGE)
ulong timer_get_boot_us(void)
{
	u64 ticks = 0;
	u32 rate = 1;
	u64 us;
	int ret;

	ret = dm_timer_init();
	if (!ret) {
		/* The timer is available */
		rate = timer_get_rate(gd->timer);
		timer_get_count(gd->timer, &ticks);
	} else {
		return 0;
	}

	us = (ticks * 1000) / rate;
	return us;
}
#endif

static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
{
	struct cadence_ttc_priv *priv = dev_get_priv(dev);

	*count = readl(&priv->regs->counter_val1);

	return 0;
}

static int cadence_ttc_probe(struct udevice *dev)
{
	struct cadence_ttc_priv *priv = dev_get_priv(dev);

	/* Disable interrupts for sure */
	writel(0, &priv->regs->interrupt_enable1);
	writel(0, &priv->regs->interrupt_enable2);
	writel(0, &priv->regs->interrupt_enable3);

	/* Make sure that clocks are configured properly without prescaller */
	writel(0, &priv->regs->clk_cntrl1);
	writel(0, &priv->regs->clk_cntrl2);
	writel(0, &priv->regs->clk_cntrl3);

	/* Reset and enable this counter */
	writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);

	return 0;
}

static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
{
	struct cadence_ttc_priv *priv = dev_get_priv(dev);

	priv->regs = map_physmem(dev_read_addr(dev),
				 sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
	if (IS_ERR(priv->regs))
		return PTR_ERR(priv->regs);

	return 0;
}

static const struct timer_ops cadence_ttc_ops = {
	.get_count = cadence_ttc_get_count,
};

static const struct udevice_id cadence_ttc_ids[] = {
	{ .compatible = "cdns,ttc" },
	{}
};

U_BOOT_DRIVER(cadence_ttc) = {
	.name = "cadence_ttc",
	.id = UCLASS_TIMER,
	.of_match = cadence_ttc_ids,
	.ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
	.probe = cadence_ttc_probe,
	.ops = &cadence_ttc_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
72c37d12 MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
	4	*/
	5
	6	#include <common.h>
	7	#include <dm.h>
	8	#include <errno.h>
	9	#include <timer.h>
	10	#include <asm/io.h>
	11
	12	#define CNT_CNTRL_RESET BIT(4)
	13
	14	struct cadence_ttc_regs {
	15	u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
	16	u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
	17	u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
	18	u32 counter_cntrl1; /* 0xC - Counter Control 1 */
	19	u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
	20	u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
	21	u32 counter_val1; /* 0x18 - Counter Control 1 */
	22	u32 counter_val2; /* 0x1C - Counter Control 2 */
	23	u32 counter_val3; /* 0x20 - Counter Control 3 */
	24	u32 reserved[15];
	25	u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
	26	u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
	27	u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
	28	};
	29
	30	struct cadence_ttc_priv {
	31	struct cadence_ttc_regs *regs;
	32	};
	33
56c0e646 MS	34	#if CONFIG_IS_ENABLED(BOOTSTAGE)
	35	ulong timer_get_boot_us(void)
	36	{
	37	u64 ticks = 0;
	38	u32 rate = 1;
	39	u64 us;
	40	int ret;
	41
	42	ret = dm_timer_init();
	43	if (!ret) {
	44	/* The timer is available */
	45	rate = timer_get_rate(gd->timer);
	46	timer_get_count(gd->timer, &ticks);
	47	} else {
	48	return 0;
	49	}
	50
	51	us = (ticks * 1000) / rate;
	52	return us;
	53	}
	54	#endif
	55
72c37d12 MS	56	static int cadence_ttc_get_count(struct udevice dev, u64 count)
	57	{
	58	struct cadence_ttc_priv *priv = dev_get_priv(dev);
	59
	60	*count = readl(&priv->regs->counter_val1);
	61
	62	return 0;
	63	}
	64
	65	static int cadence_ttc_probe(struct udevice *dev)
	66	{
	67	struct cadence_ttc_priv *priv = dev_get_priv(dev);
	68
	69	/* Disable interrupts for sure */
	70	writel(0, &priv->regs->interrupt_enable1);
	71	writel(0, &priv->regs->interrupt_enable2);
	72	writel(0, &priv->regs->interrupt_enable3);
	73
	74	/* Make sure that clocks are configured properly without prescaller */
	75	writel(0, &priv->regs->clk_cntrl1);
	76	writel(0, &priv->regs->clk_cntrl2);
	77	writel(0, &priv->regs->clk_cntrl3);
	78
	79	/* Reset and enable this counter */
	80	writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
	81
	82	return 0;
	83	}
	84
	85	static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
	86	{
	87	struct cadence_ttc_priv *priv = dev_get_priv(dev);
	88
72b88103	89	priv->regs = map_physmem(dev_read_addr(dev),
72c37d12	90	sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
72b88103 MS	91	if (IS_ERR(priv->regs))
72b88103 MS	92	return PTR_ERR(priv->regs);
72c37d12 MS	93
	94	return 0;
	95	}
	96
	97	static const struct timer_ops cadence_ttc_ops = {
	98	.get_count = cadence_ttc_get_count,
	99	};
	100
	101	static const struct udevice_id cadence_ttc_ids[] = {
	102	{ .compatible = "cdns,ttc" },
	103	{}
	104	};
	105
	106	U_BOOT_DRIVER(cadence_ttc) = {
	107	.name = "cadence_ttc",
	108	.id = UCLASS_TIMER,
	109	.of_match = cadence_ttc_ids,
	110	.ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
	111	.priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
	112	.probe = cadence_ttc_probe,
	113	.ops = &cadence_ttc_ops,
	114	.flags = DM_FLAG_PRE_RELOC,
	115	};