[J-u-boot.git] / include / configs / am3517_evm.h

/*
 * am3517_evm.h - Default configuration for AM3517 EVM board.
 *
 * Author: Vaibhav Hiremath <[email protected]>
 *
 * Based on omap3_evm_config.h
 *
 * Copyright (C) 2010 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
/*
 * DDR related
 */
#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_GENERIC_MMC		1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/*
 * USB configuration
 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
 * Enable CONFIG_MUSB_UDC for Device functionalities.
 */
#define CONFIG_USB_AM35X		1
#define CONFIG_MUSB_HCD			1

#ifdef CONFIG_USB_AM35X

#ifdef CONFIG_MUSB_HCD
#define CONFIG_CMD_USB

#define CONFIG_USB_STORAGE
#define CONGIG_CMD_STORAGE
#define CONFIG_CMD_FAT

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_MUSB_HCD */

#ifdef CONFIG_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"AM3517EVM"
#endif /* CONFIG_MUSB_UDC */

#endif /* CONFIG_USB_AM35X */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	10

#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define V_PROMPT			"AM3517_EVM # "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
Commit	Line	Data
ed01e45c VH	1	/*
	2	* am3517_evm.h - Default configuration for AM3517 EVM board.
	3	*
	4	* Author: Vaibhav Hiremath <[email protected]>
	5	*
	6	* Based on omap3_evm_config.h
	7	*
	8	* Copyright (C) 2010 Texas Instruments Incorporated
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
ed01e45c VH	31	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	32	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	33	#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
	34
1a5038ca	35	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
ed01e45c VH	36
	37	#include <asm/arch/cpu.h> /* get chip and board defs */
	38	#include <asm/arch/omap3.h>
	39
	40	/*
	41	* Display CPU and Board information
	42	*/
	43	#define CONFIG_DISPLAY_CPUINFO 1
	44	#define CONFIG_DISPLAY_BOARDINFO 1
	45
	46	/* Clock Defines */
	47	#define V_OSCK 26000000 /* Clock output from T2 */
	48	#define V_SCLK (V_OSCK >> 1)
	49
	50	#undef CONFIG_USE_IRQ /* no support for IRQs */
	51	#define CONFIG_MISC_INIT_R
	52
	53	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	54	#define CONFIG_SETUP_MEMORY_TAGS 1
	55	#define CONFIG_INITRD_TAG 1
	56	#define CONFIG_REVISION_TAG 1
	57
	58	/*
	59	* Size of malloc() pool
	60	*/
	61	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	62	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
ed01e45c VH	63	/*
	64	* DDR related
	65	*/
	66	#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
	67	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	68
	69	/*
	70	* Hardware drivers
	71	*/
	72
	73	/*
	74	* NS16550 Configuration
	75	*/
	76	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	77
	78	#define CONFIG_SYS_NS16550
	79	#define CONFIG_SYS_NS16550_SERIAL
	80	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	81	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	82
	83	/*
	84	* select serial console configuration
	85	*/
	86	#define CONFIG_CONS_INDEX 3
	87	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	88	#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
	89
	90	/* allow to overwrite serial and ethaddr */
	91	#define CONFIG_ENV_OVERWRITE
	92	#define CONFIG_BAUDRATE 115200
	93	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	94	115200}
	95	#define CONFIG_MMC 1
122e6e0a VH	96	#define CONFIG_GENERIC_MMC 1
122e6e0a VH	97	#define CONFIG_OMAP_HSMMC 1
ed01e45c VH	98	#define CONFIG_DOS_PARTITION 1
ed01e45c VH	99
7dc27b05 AKG	100	/*
	101	* USB configuration
	102	* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
	103	* Enable CONFIG_MUSB_UDC for Device functionalities.
	104	*/
	105	#define CONFIG_USB_AM35X 1
	106	#define CONFIG_MUSB_HCD 1
	107
	108	#ifdef CONFIG_USB_AM35X
	109
	110	#ifdef CONFIG_MUSB_HCD
	111	#define CONFIG_CMD_USB
	112
	113	#define CONFIG_USB_STORAGE
	114	#define CONGIG_CMD_STORAGE
	115	#define CONFIG_CMD_FAT
	116
	117	#ifdef CONFIG_USB_KEYBOARD
	118	#define CONFIG_SYS_USB_EVENT_POLL
	119	#define CONFIG_PREBOOT "usb start"
	120	#endif /* CONFIG_USB_KEYBOARD */
	121
	122	#endif /* CONFIG_MUSB_HCD */
	123
	124	#ifdef CONFIG_MUSB_UDC
	125	/* USB device configuration */
	126	#define CONFIG_USB_DEVICE 1
	127	#define CONFIG_USB_TTY 1
	128	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	129	/* Change these to suit your needs */
	130	#define CONFIG_USBD_VENDORID 0x0451
	131	#define CONFIG_USBD_PRODUCTID 0x5678
	132	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	133	#define CONFIG_USBD_PRODUCT_NAME "AM3517EVM"
	134	#endif /* CONFIG_MUSB_UDC */
	135
	136	#endif /* CONFIG_USB_AM35X */
	137
ed01e45c VH	138	/* commands to include */
	139	#include <config_cmd_default.h>
	140
	141	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	142	#define CONFIG_CMD_FAT /* FAT support */
	143	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	144
	145	#define CONFIG_CMD_I2C /* I2C serial bus support */
	146	#define CONFIG_CMD_MMC /* MMC support */
	147	#define CONFIG_CMD_NAND /* NAND support */
	148	#define CONFIG_CMD_DHCP
	149	#define CONFIG_CMD_PING
	150
	151	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	152	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	153	#undef CONFIG_CMD_IMI /* iminfo */
	154	#undef CONFIG_CMD_IMLS /* List all found images */
	155
	156	#define CONFIG_SYS_NO_FLASH
	157	#define CONFIG_HARD_I2C 1
	158	#define CONFIG_SYS_I2C_SPEED 100000
	159	#define CONFIG_SYS_I2C_SLAVE 1
	160	#define CONFIG_SYS_I2C_BUS 0
	161	#define CONFIG_SYS_I2C_BUS_SELECT 1
	162	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	163
	164	#undef CONFIG_CMD_NET
aa82d5f2	165	#undef CONFIG_CMD_NFS
ed01e45c VH	166	/*
	167	* Board NAND Info.
	168	*/
	169	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	170	/* to access nand */
	171	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	172	/* to access */
	173	/* nand at CS0 */
	174
	175	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	176	/* NAND devices */
	177	#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
	178
	179	#define CONFIG_JFFS2_NAND
	180	/* nand device jffs2 lives on */
	181	#define CONFIG_JFFS2_DEV "nand0"
	182	/* start of jffs2 partition */
	183	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	184	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	185
	186	/* Environment information */
	187	#define CONFIG_BOOTDELAY 10
	188
b3f44c21	189	#define CONFIG_BOOTFILE "uImage"
ed01e45c VH	190
	191	#define CONFIG_EXTRA_ENV_SETTINGS \
	192	"loadaddr=0x82000000\0" \
49473ada	193	"console=ttyO2,115200n8\0" \
122e6e0a	194	"mmcdev=0\0" \
ed01e45c VH	195	"mmcargs=setenv bootargs console=${console} " \
	196	"root=/dev/mmcblk0p2 rw " \
	197	"rootfstype=ext3 rootwait\0" \
	198	"nandargs=setenv bootargs console=${console} " \
	199	"root=/dev/mtdblock4 rw " \
	200	"rootfstype=jffs2\0" \
122e6e0a	201	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
ed01e45c VH	202	"bootscript=echo Running bootscript from mmc ...; " \
ed01e45c VH	203	"source ${loadaddr}\0" \
122e6e0a	204	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
ed01e45c VH	205	"mmcboot=echo Booting from mmc ...; " \
	206	"run mmcargs; " \
	207	"bootm ${loadaddr}\0" \
	208	"nandboot=echo Booting from nand ...; " \
	209	"run nandargs; " \
	210	"nand read ${loadaddr} 280000 400000; " \
	211	"bootm ${loadaddr}\0" \
	212
	213	#define CONFIG_BOOTCOMMAND \
122e6e0a	214	"if mmc rescan ${mmcdev}; then " \
ed01e45c VH	215	"if run loadbootscript; then " \
	216	"run bootscript; " \
	217	"else " \
	218	"if run loaduimage; then " \
	219	"run mmcboot; " \
	220	"else run nandboot; " \
	221	"fi; " \
	222	"fi; " \
	223	"else run nandboot; fi"
	224
	225	#define CONFIG_AUTO_COMPLETE 1
	226	/*
	227	* Miscellaneous configurable options
	228	*/
	229	#define V_PROMPT "AM3517_EVM # "
	230
	231	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	232	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	233	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	234	#define CONFIG_SYS_PROMPT V_PROMPT
	235	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	236	/* Print Buffer Size */
	237	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	238	sizeof(CONFIG_SYS_PROMPT) + 16)
	239	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	240	/* args */
	241	/* Boot Argument Buffer Size */
	242	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	243	/* memtest works on */
	244	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	245	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	246	0x01F00000) /* 31MB */
	247
	248	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	249	/* address */
	250
	251	/*
	252	* AM3517 has 12 GP timers, they can be driven by the system clock
	253	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	254	* This rate is divided by a local divisor.
	255	*/
	256	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	257	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	258	#define CONFIG_SYS_HZ 1000
	259
	260	/*-----------------------------------------------------------------------
	261	* Stack sizes
	262	*
	263	* The stack sizes are set up in start.S using the settings below
	264	*/
	265	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
ed01e45c VH	266
	267	/*-----------------------------------------------------------------------
	268	* Physical Memory Map
	269	*/
	270	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	271	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	272	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	273	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	274
ed01e45c VH	275	/*-----------------------------------------------------------------------
	276	* FLASH and environment organization
	277	*/
	278
	279	/* ** PISMO SUPPORT * */
	280
	281	/* Configure the PISMO */
	282	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	283	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	284
	285	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	286	/* on one chip */
	287	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	288	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	289
6cbec7b3 LC	290	#if defined(CONFIG_CMD_NAND)
	291	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	292	#endif
ed01e45c VH	293
	294	/* Monitor at start of flash */
	295	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	296
	297	#define CONFIG_NAND_OMAP_GPMC
	298	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	299	#define CONFIG_ENV_IS_IN_NAND 1
	300	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	301
6cbec7b3 LC	302	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	303	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	304	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
ed01e45c VH	305
	306	/*-----------------------------------------------------------------------
	307	* CFI FLASH driver setup
	308	*/
	309	/* timeout values are in ticks */
	310	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	311	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	312
	313	/* Flash banks JFFS2 should use */
	314	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	315	CONFIG_SYS_MAX_NAND_DEVICE)
	316	#define CONFIG_SYS_JFFS2_MEM_NAND
	317	/* use flash_info[2] */
	318	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	319	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	320
13acfc6f VH	321	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	322	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	323	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	324	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	325	CONFIG_SYS_INIT_RAM_SIZE - \
	326	GENERATED_GBL_DATA_SIZE)
ed01e45c	327	#endif /* __CONFIG_H */