projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f278a217 | 1 | CONFIG_ARM=y |
| b11dc33e | 2 | CONFIG_GIC_V3_ITS=y |
| f278a217 | 3 | CONFIG_TARGET_LS1028AQDS=y |
| f278a217 | 4 | CONFIG_TFABOOT=y |
| 21d5e964 | 5 | CONFIG_SYS_MALLOC_F_LEN=0x6000 |
| 554e5514 | 6 | CONFIG_NR_DRAM_BANKS=2 |
| 53def460 TR |
7 | CONFIG_SYS_MEMTEST_START=0x80000000 |
| 8 | CONFIG_SYS_MEMTEST_END=0x9fffffff | |
| a09fea1d TR |
9 | CONFIG_ENV_SIZE=0x2000 |
| 10 | CONFIG_ENV_OFFSET=0x500000 | |
| 556fd590 | 11 | CONFIG_ENV_SECT_SIZE=0x40000 |
| 052170c6 TR |
12 | CONFIG_DM_GPIO=y |
| 13 | CONFIG_FSPI_AHB_EN_4BYTE=y | |
| f278a217 YT |
14 | CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y |
| 15 | CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y | |
| f7d0ae9c | 16 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" |
| f278a217 YT |
17 | CONFIG_AHCI=y |
| 18 | CONFIG_DISTRO_DEFAULTS=y | |
| f278a217 YT |
19 | CONFIG_FIT_VERBOSE=y |
| 20 | CONFIG_OF_BOARD_SETUP=y | |
| 21 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
| 22 | CONFIG_BOOTDELAY=10 | |
| 23 | CONFIG_USE_BOOTARGS=y | |
| 24 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" | |
| a2a14746 | 25 | CONFIG_MISC_INIT_R=y |
| f278a217 | 26 | CONFIG_CMD_GREPENV=y |
| a389c9cd | 27 | CONFIG_CMD_MEMTEST=y |
| 873d00a3 | 28 | CONFIG_CMD_DM=y |
| dd5186c5 | 29 | CONFIG_CMD_GPIO=y |
| 6144438f | 30 | CONFIG_CMD_GPT=y |
| f278a217 YT |
31 | CONFIG_CMD_I2C=y |
| 32 | CONFIG_CMD_MMC=y | |
| 33 | CONFIG_CMD_PCI=y | |
| f278a217 | 34 | CONFIG_CMD_USB=y |
| 4ba98fa2 | 35 | CONFIG_CMD_WDT=y |
| f278a217 YT |
36 | # CONFIG_CMD_SETEXPR is not set |
| 37 | CONFIG_CMD_CACHE=y | |
| 38 | CONFIG_OF_CONTROL=y | |
| e91907a1 | 39 | CONFIG_ENV_OVERWRITE=y |
| f278a217 YT |
40 | CONFIG_ENV_IS_IN_MMC=y |
| 41 | CONFIG_ENV_IS_IN_SPI_FLASH=y | |
| a09fea1d | 42 | CONFIG_ENV_ADDR=0x20500000 |
| f278a217 YT |
43 | CONFIG_NET_RANDOM_ETHADDR=y |
| 44 | CONFIG_NETCONSOLE=y | |
| 45 | CONFIG_DM=y | |
| 46 | CONFIG_SCSI_AHCI=y | |
| 47 | CONFIG_SATA_CEVA=y | |
| 48 | CONFIG_FSL_CAAM=y | |
| 21d5e964 CH |
49 | CONFIG_DM_I2C=y |
| 50 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y | |
| 51 | CONFIG_I2C_DEFAULT_BUS_NUMBER=0 | |
| 52 | CONFIG_I2C_MUX=y | |
| 53 | CONFIG_I2C_MUX_PCA954x=y | |
| f278a217 | 54 | CONFIG_DM_MMC=y |
| 60742bfb | 55 | CONFIG_FSL_ESDHC=y |
| 63ea3172 | 56 | CONFIG_MTD=y |
| 0cfccb54 | 57 | CONFIG_DM_SPI_FLASH=y |
| 67128564 | 58 | CONFIG_SPI_FLASH_EON=y |
| f278a217 | 59 | CONFIG_SPI_FLASH_STMICRO=y |
| 67128564 | 60 | CONFIG_SPI_FLASH_SST=y |
| f278a217 YT |
61 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
| 62 | CONFIG_PHYLIB=y | |
| 9b844314 | 63 | CONFIG_PHY_AQUANTIA=y |
| f278a217 | 64 | CONFIG_PHY_ATHEROS=y |
| 9b844314 | 65 | CONFIG_PHY_VITESSE=y |
| 20ecfbe9 | 66 | CONFIG_PHY_FIXED=y |
| f278a217 | 67 | CONFIG_DM_ETH=y |
| 9b844314 | 68 | CONFIG_DM_MDIO=y |
| 66664085 | 69 | CONFIG_DM_MDIO_MUX=y |
| d0034345 | 70 | CONFIG_DM_DSA=y |
| 20ecfbe9 | 71 | CONFIG_E1000=y |
| d0034345 | 72 | CONFIG_MSCC_FELIX_SWITCH=y |
| 20ecfbe9 | 73 | CONFIG_MDIO_MUX_I2CREG=y |
| cdeb7b8f | 74 | CONFIG_NVME=y |
| f278a217 YT |
75 | CONFIG_PCI=y |
| 76 | CONFIG_DM_PCI=y | |
| 77 | CONFIG_DM_PCI_COMPAT=y | |
| 062d8148 | 78 | CONFIG_PCIE_ECAM_GENERIC=y |
| ed188aa8 | 79 | CONFIG_PCIE_LAYERSCAPE_RC=y |
| 21d5e964 CH |
80 | CONFIG_DM_RTC=y |
| 81 | CONFIG_RTC_PCF2127=y | |
| f278a217 YT |
82 | CONFIG_SCSI=y |
| 83 | CONFIG_DM_SCSI=y | |
| 84 | CONFIG_SYS_NS16550=y | |
| 85 | CONFIG_SPI=y | |
| 86 | CONFIG_DM_SPI=y | |
| 87 | CONFIG_FSL_DSPI=y | |
| 36df9c7e | 88 | CONFIG_NXP_FSPI=y |
| f278a217 YT |
89 | CONFIG_USB=y |
| 90 | CONFIG_DM_USB=y | |
| 91 | CONFIG_USB_XHCI_HCD=y | |
| 92 | CONFIG_USB_XHCI_DWC3=y | |
| 4ba98fa2 QZ |
93 | CONFIG_WDT=y |
| 94 | CONFIG_WDT_SP805=y | |
| 201d8a5c | 95 | CONFIG_OF_LIBFDT_OVERLAY=y |
| f278a217 | 96 | CONFIG_EFI_LOADER_BOUNCE_BUFFER=y |