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Commit | Line | Data |
---|---|---|
08ac386b | 1 | CONFIG_ARM=y |
08ac386b | 2 | CONFIG_ARCH_ZYNQMP=y |
59e88056 | 3 | CONFIG_SYS_MALLOC_F_LEN=0x8000 |
a4d88920 | 4 | CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4" |
08ac386b MS |
5 | CONFIG_SYS_TEXT_BASE=0x8000000 |
6 | CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" | |
7 | CONFIG_FIT=y | |
8 | CONFIG_FIT_VERBOSE=y | |
0c1b02a7 | 9 | CONFIG_SPL_LOAD_FIT=y |
19a97475 | 10 | # CONFIG_DISPLAY_CPUINFO is not set |
84351792 | 11 | # CONFIG_DISPLAY_BOARDINFO is not set |
c2ae7d82 SG |
12 | CONFIG_SPL=y |
13 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y | |
c20ae2ff | 14 | CONFIG_SPL_OS_BOOT=y |
08ac386b MS |
15 | CONFIG_HUSH_PARSER=y |
16 | CONFIG_SYS_PROMPT="ZynqMP> " | |
17 | # CONFIG_CMD_IMLS is not set | |
18 | CONFIG_CMD_MEMTEST=y | |
19 | # CONFIG_CMD_FLASH is not set | |
20 | CONFIG_CMD_MMC=y | |
21 | CONFIG_CMD_I2C=y | |
22 | CONFIG_CMD_TFTPPUT=y | |
23 | CONFIG_CMD_DHCP=y | |
24 | CONFIG_CMD_MII=y | |
25 | CONFIG_CMD_PING=y | |
26 | CONFIG_CMD_TIME=y | |
27 | CONFIG_CMD_TIMER=y | |
28 | CONFIG_CMD_EXT2=y | |
29 | CONFIG_CMD_EXT4=y | |
30 | CONFIG_CMD_EXT4_WRITE=y | |
31 | CONFIG_CMD_FAT=y | |
32 | CONFIG_CMD_FS_GENERIC=y | |
f3d1cc2f | 33 | CONFIG_SPL_OF_CONTROL=y |
08ac386b MS |
34 | CONFIG_OF_EMBED=y |
35 | CONFIG_NET_RANDOM_ETHADDR=y | |
3c70349f | 36 | CONFIG_SPL_DM=y |
f3d1cc2f | 37 | CONFIG_SPL_DM_SEQ_ALIAS=y |
6b245014 SDPP |
38 | CONFIG_FPGA_XILINX=y |
39 | CONFIG_FPGA_ZYNQMPPL=y | |
aca5cd27 | 40 | CONFIG_DM_GPIO=y |
3c70349f | 41 | CONFIG_DM_I2C=y |
08ac386b MS |
42 | CONFIG_SYS_I2C_CADENCE=y |
43 | CONFIG_DM_MMC=y | |
44 | CONFIG_ZYNQ_SDHCI=y | |
45 | CONFIG_DM_ETH=y | |
46 | CONFIG_ZYNQ_GEM=y | |
47 | CONFIG_DEBUG_UART=y | |
48 | CONFIG_DEBUG_UART_ZYNQ=y | |
49 | CONFIG_DEBUG_UART_BASE=0xff000000 | |
50 | CONFIG_DEBUG_UART_CLOCK=100000000 | |
51 | CONFIG_DEBUG_UART_ANNOUNCE=y |