projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| b20c38a9 SR |
2 | /* |
| 3 | * Copyright (C) 2015-2016 Stefan Roese <[email protected]> | |
| b20c38a9 SR |
4 | */ |
| 5 | ||
| 6 | #ifndef _CONFIG_THEADORABLE_H | |
| 7 | #define _CONFIG_THEADORABLE_H | |
| 8 | ||
| 94752f5f TR |
9 | #include <linux/sizes.h> |
| 10 | ||
| b20c38a9 SR |
11 | /* |
| 12 | * High Level Configuration Options (easy to change) | |
| 13 | */ | |
| b20c38a9 SR |
14 | |
| 15 | /* | |
| 16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
| 17 | * for DDR ECC byte filling in the SPL before loading the main | |
| 18 | * U-Boot into it. | |
| 19 | */ | |
| b20c38a9 | 20 | |
| b20c38a9 SR |
21 | /* |
| 22 | * The debugging version enables USB support via defconfig. | |
| 23 | * This version should also enable all other non-production | |
| 24 | * interfaces / features. | |
| 25 | */ | |
| b20c38a9 SR |
26 | |
| 27 | /* I2C */ | |
| 45ede979 | 28 | #define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
| 35661f86 | 29 | #define CFG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE |
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30 | |
| 31 | /* USB/EHCI configuration */ | |
| b20c38a9 | 32 | |
| b20c38a9 | 33 | /* Environment in SPI NOR flash */ |
| b20c38a9 | 34 | |
| b20c38a9 | 35 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
| 0613c36a | 36 | #define CFG_EXTRA_ENV_SETTINGS \ |
| b20c38a9 SR |
37 | "fdt_high=0x10000000\0" \ |
| 38 | "initrd_high=0x10000000\0" | |
| 39 | ||
| 28226b9a SR |
40 | /* |
| 41 | * Bootcounter | |
| 42 | */ | |
| 28226b9a SR |
43 | /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ |
| 44 | #define BOOTCOUNT_ADDR 0x1000 | |
| 45 | ||
| b20c38a9 SR |
46 | /* |
| 47 | * mv-common.h should be defined after CMD configs since it used them | |
| 48 | * to enable certain macros | |
| 49 | */ | |
| 50 | #include "mv-common.h" | |
| 51 | ||
| 52 | /* | |
| 53 | * Memory layout while starting into the bin_hdr via the | |
| 54 | * BootROM: | |
| 55 | * | |
| 56 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) | |
| 57 | * 0x4000.4030 bin_hdr start address | |
| 58 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) | |
| 59 | * 0x4007.fffc BootROM stack top | |
| 60 | * | |
| 61 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in | |
| 62 | * L2 cache thus cannot be used. | |
| 63 | */ | |
| 64 | ||
| 65 | /* SPL */ | |
| 66 | /* Defines for SPL */ | |
| b20c38a9 | 67 | |
| b20c38a9 | 68 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
| aa6e94de | 69 | #define CFG_SYS_SDRAM_SIZE SZ_2G |
| b20c38a9 SR |
70 | |
| 71 | #endif /* _CONFIG_THEADORABLE_H */ |