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Commit | Line | Data |
---|---|---|
d04aa29f JT |
1 | { |
2 | { | |
3 | { | |
4 | .rank = 0x1, | |
5 | .col = 0xC, | |
6 | .bk = 0x3, | |
7 | .bw = 0x0, | |
8 | .dbw = 0x0, | |
9 | .row_3_4 = 0x0, | |
10 | .cs0_row = 0x10, | |
11 | .cs1_row = 0x10, | |
12 | .cs0_high16bit_row = 0x10, | |
13 | .cs1_high16bit_row = 0x10, | |
14 | .ddrconfig = 0 | |
15 | }, | |
16 | { | |
17 | {0x2c0f080e}, | |
18 | {0x0d030502}, | |
19 | {0x00000002}, | |
20 | {0x00001111}, | |
21 | {0x0000000c}, | |
22 | {0x00000000}, | |
23 | 0x000000ff | |
24 | } | |
25 | }, | |
26 | { | |
27 | .ddr_freq = 528, /* clock rate(MHz) */ | |
28 | .dramtype = DDR3, | |
29 | .num_channels = 1, | |
30 | .stride = 0, | |
31 | .odt = 0 | |
32 | }, | |
33 | { | |
34 | { | |
35 | {0x00000000, 0x43042001}, /* MSTR */ | |
36 | {0x00000064, 0x0040005d}, /* RFSHTMG */ | |
37 | {0x000000d0, 0x00020082}, /* INIT0 */ | |
38 | {0x000000d4, 0x00350000}, /* INIT1 */ | |
39 | {0x000000d8, 0x00000100}, /* INIT2 */ | |
40 | {0x000000dc, 0x09400000}, /* INIT3 */ | |
41 | {0x000000e0, 0x00080000}, /* INIT4 */ | |
42 | {0x000000e4, 0x00090000}, /* INIT5 */ | |
43 | {0x000000f4, 0x000f011f}, /* RANKCTL */ | |
44 | {0x00000100, 0x090e120a}, /* DRAMTMG0 */ | |
45 | {0x00000104, 0x0007020e}, /* DRAMTMG1 */ | |
46 | {0x00000108, 0x03040407}, /* DRAMTMG2 */ | |
47 | {0x0000010c, 0x00202006}, /* DRAMTMG3 */ | |
48 | {0x00000110, 0x04020305}, /* DRAMTMG4 */ | |
49 | {0x00000114, 0x03030302}, /* DRAMTMG5 */ | |
50 | {0x00000120, 0x00000904}, /* DRAMTMG8 */ | |
51 | {0x00000180, 0x00800020}, /* ZQCTL0 */ | |
52 | {0x00000184, 0x00000000}, /* ZQCTL1 */ | |
53 | {0x00000190, 0x07020001}, /* DFITMG0 */ | |
54 | {0x00000198, 0x07000101}, /* DFILPCFG0 */ | |
55 | {0x000001a0, 0xc0400003}, /* DFIUPD0 */ | |
56 | {0x00000240, 0x06000608}, /* ODTCFG */ | |
57 | {0x00000244, 0x00000201}, /* ODTMAP */ | |
58 | {0x00000250, 0x00001f00}, /* SCHED */ | |
59 | {0x00000490, 0x00000001}, /* PCTRL_0 */ | |
60 | {0xffffffff, 0xffffffff} | |
61 | } | |
62 | }, | |
63 | { | |
64 | { | |
65 | {0x00000004, 0x0000008a}, /* PHYREG01 */ | |
66 | {0x00000014, 0x00000008}, /* PHYREG05 */ | |
67 | {0x00000018, 0x00000000}, /* PHYREG06 */ | |
68 | {0x0000001c, 0x00000006}, /* PHYREG07 */ | |
69 | {0xffffffff, 0xffffffff} | |
70 | } | |
71 | } | |
72 | }, |