[J-u-boot.git] / include / configs / DK1C20.h

/*
 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
 * Scott McNutt <[email protected]>
 * Stephan Linz <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************************
 * Include the whole NIOS CPU configuration.
 *
 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
 *
 ***********************************************************************/

#if	defined(CONFIG_NIOS_SAFE_32)
#include <configs/DK1C20_safe_32.h>
#elif	defined(CONFIG_NIOS_STANDARD_32)
#include <configs/DK1C20_standard_32.h>
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif

/*------------------------------------------------------------------------
 * BOARD/CPU -- TOP-LEVEL
 *----------------------------------------------------------------------*/
#define CONFIG_NIOS		1		/* NIOS-32 core		*/
#define	CONFIG_DK1C20		1		/* Cyclone DK-1C20 board*/
#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
#define	CFG_HZ			1000		/* 1 msec time tick	*/
#undef  CFG_CLKS_IN_HZ
#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)

#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE

#else
#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
#endif

#define CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
#define CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION - For the most part, you can put things pretty
 * much anywhere. This is pretty flexible for Nios. So here we make some
 * arbitrary choices & assume that the monitor is placed at the end of
 * a memory resource (so you must make sure TEXT_BASE is chosen
 * appropriately).
 *
 * 	-The heap is placed below the monitor.
 * 	-Global data is placed below the heap.
 * 	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/

#else
#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * ENVIRONMENT
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */

#else
#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
#endif

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_UART_NUMS != 0)

#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */

#if	(CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
#else
#undef	CFG_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE		115200
#endif

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#else
#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 * so an avalon bus timer is required.
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_TIMER_NUMS != 0)

#if	(CFG_NIOS_CPU_TICK_TIMER == 0)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ

#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */

#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
#endif

#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */

#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */

#if	(CFG_HZ <= 1000)
#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
#else
#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
#endif

#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)

#else
#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
#endif

#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ

#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */

#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
#endif

#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */

#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */

#if	(CFG_HZ <= 1000)
#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
#else
#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
#endif

#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)

#else
#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
#endif

#endif	/* CFG_NIOS_CPU_TICK_TIMER */

#else
#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * Ethernet
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_LAN_NUMS == 1)

#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/

#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)

#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
#define	CONFIG_SMC_USE_32_BIT	1
#else	/* no */
#undef	CONFIG_SMC_USE_32_BIT
#endif

#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/

	/********************************************/
	/* !!! CS8900 is __not__ tested on NIOS !!! */
	/********************************************/
#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)

#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
#undef	CS8900_BUS16
#define	CS8900_BUS32		1
#else	/* no */
#define	CS8900_BUS16		1
#undef	CS8900_BUS32
#endif

#else
#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
#endif

#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.2.21
#define CONFIG_SERVERIP		192.168.2.16

#else
#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
#endif

/*------------------------------------------------------------------------
 * STATUS LEDs
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_PIO_NUMS != 0)

#if	(CFG_NIOS_CPU_LED_PIO == 0)

#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 1)

#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 2)

#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */

#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
#define	STATUS_LED_WRONLY		1
#else
#undef	STATUS_LED_WRONLY
#endif

#elif	(CFG_NIOS_CPU_LED_PIO == 3)

#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 4)

#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 5)

#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 6)

#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 7)

#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 8)

#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 9)

#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h

#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
#endif

#define	CONFIG_STATUS_LED		1 /* enable status led driver */

#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
#define	STATUS_LED_STATE		STATUS_LED_BLINKING
#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_BOOT			0		/* boot LED */

#if	(STATUS_LED_BITS > 1)
#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
#define	STATUS_LED_STATE1		STATUS_LED_OFF
#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
#define	STATUS_LED_RED			1		/* fail LED */
#endif

#if	(STATUS_LED_BITS > 2)
#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
#define	STATUS_LED_STATE2		STATUS_LED_OFF
#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_YELLOW		2		/* info LED */
#endif

#if	(STATUS_LED_BITS > 3)
#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
#define	STATUS_LED_STATE3		STATUS_LED_OFF
#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_GREEN		3		/* info LED */
#endif

#define	STATUS_LED_PAR			1 /* makes status_led.h happy */

#endif	/* CFG_NIOS_CPU_PIO_NUMS */

/*------------------------------------------------------------------------
 * SEVEN SEGMENT LED DISPLAY
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_PIO_NUMS != 0)

#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)

#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)

#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)

#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)

#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */

#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
#define	SEVENSEG_WRONLY			1
#else
#undef	SEVENSEG_WRONLY
#endif

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)

#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)

#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)

#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)

#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)

#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)

#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h

#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
#endif

#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */

/*
 * Dual 7-Segment Display pin assignment -- read more in your
 * "Nios Development Board Reference Manual"
 *
 *
 *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
 *         ______               ______
 *        |  D14 |             |  D6  |
 *        |      |             |      |
 *      D9|      |D13        D1|      |D5
 *        |______|             |______|                  ___
 *        |  D8  |             |  D0  |                 | A |
 *        |      |             |      |                F|___|B
 *     D10|      |D12        D2|      |D4               | G |
 *        |______|             |______|                E|___|C
 *           D11  *               D3   *                  D  *
 *                D15                  D7                    DP
 *
 */
#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */

#endif	/* CFG_NIOS_CPU_PIO_NUMS */

/*------------------------------------------------------------------------
 * ASMI - Active Serial Memory Interface.
 *
 * ASMI is for Cyclone devices only and only works when the configuration
 * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
 *----------------------------------------------------------------------*/
#define CONFIG_NIOS_ASMI			   /* Enable ASMI	*/
#define CFG_NIOS_ASMIBASE	CFG_NIOS_CPU_ASMI0 /* ASMI base address	*/

/*------------------------------------------------------------------------
 * COMMANDS
 *----------------------------------------------------------------------*/
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_CMD_ASKENV | \
				 CFG_CMD_BEDBUG | \
				 CFG_CMD_BMP	| \
				 CFG_CMD_BSP	| \
				 CFG_CMD_CACHE	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_DTT	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_ELF    | \
				 CFG_CMD_FAT	| \
				 CFG_CMD_FDC	| \
				 CFG_CMD_FDOS	| \
				 CFG_CMD_HWFLOW	| \
				 CFG_CMD_IDE	| \
				 CFG_CMD_I2C	| \
				 CFG_CMD_JFFS2	| \
				 CFG_CMD_KGDB	| \
				 CFG_CMD_NAND	| \
				 CFG_CMD_MMC	| \
				 CFG_CMD_MII	| \
				 CFG_CMD_PCI	| \
				 CFG_CMD_PCMCIA | \
				 CFG_CMD_SCSI	| \
				 CFG_CMD_SPI	| \
				 CFG_CMD_VFD	| \
				 CFG_CMD_USB	) )


#include <cmd_confdefs.h>

/*------------------------------------------------------------------------
 * KGDB
 *----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	9600
#endif

/*------------------------------------------------------------------------
 * MISC
 *----------------------------------------------------------------------*/
#define	CFG_LONGHELP			    /* undef to save memory	*/
#define	CFG_PROMPT		"DK1C20 > " /* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16	    /* max number of command args*/
#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */

#if	(CFG_SRAM_SIZE != 0)
#define	CFG_LOAD_ADDR		CFG_SRAM_BASE	/* Default load address	*/
#else
#undef	CFG_LOAD_ADDR
#endif

#if	(CFG_SDRAM_SIZE != 0)
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE	/* SDRAM til stack area */
#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
#else
#undef	CFG_MEMTEST_START
#undef	CFG_MEMTEST_END
#endif


#endif	/* __CONFIG_H */
Commit	Line	Data
4a551709 WD	1	/*
	2	* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
	3	* Scott McNutt <[email protected]>
c935d3bd	4	* Stephan Linz <[email protected]>
4a551709 WD	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
ec4c544b WD	28	/***********************************************************************
ec4c544b WD	29	* Include the whole NIOS CPU configuration.
c935d3bd	30	*
ec4c544b	31	* !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
c935d3bd	32	*
ec4c544b	33	***********************************************************************/
c935d3bd WD	34
c935d3bd WD	35	#if defined(CONFIG_NIOS_SAFE_32)
ec4c544b	36	#include <configs/DK1C20_safe_32.h>
c935d3bd	37	#elif defined(CONFIG_NIOS_STANDARD_32)
ec4c544b	38	#include <configs/DK1C20_standard_32.h>
c935d3bd WD	39	#else
	40	#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
	41	#endif
	42
4a551709 WD	43	/*------------------------------------------------------------------------
	44	* BOARD/CPU -- TOP-LEVEL
	45	----------------------------------------------------------------------/
	46	#define CONFIG_NIOS 1 /* NIOS-32 core */
	47	#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
c935d3bd WD	48	#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
	49	#define CFG_HZ 1000 /* 1 msec time tick */
	50	#undef CFG_CLKS_IN_HZ
c837dcb1	51	#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
4a551709 WD	52
4a551709 WD	53	/*------------------------------------------------------------------------
c935d3bd	54	* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
4a551709	55	----------------------------------------------------------------------/
c935d3bd WD	56	#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
	57
	58	#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
	59	#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
	60
	61	#else
	62	#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
	63	#endif
	64
	65	#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
	66	#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
	67	#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
4a551709 WD	68
	69	/*------------------------------------------------------------------------
	70	* MEMORY ORGANIZATION - For the most part, you can put things pretty
	71	* much anywhere. This is pretty flexible for Nios. So here we make some
	72	* arbitrary choices & assume that the monitor is placed at the end of
	73	* a memory resource (so you must make sure TEXT_BASE is chosen
	74	* appropriately).
	75	*
	76	* -The heap is placed below the monitor.
	77	* -Global data is placed below the heap.
	78	* -The stack is placed below global data (&grows down).
	79	----------------------------------------------------------------------/
	80	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
4a551709 WD	81	#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
	82	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
	83
	84	#define CFG_MONITOR_BASE TEXT_BASE
	85	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
c935d3bd	86	#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
4a551709 WD	87	#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
	88
	89	/*------------------------------------------------------------------------
c935d3bd	90	* FLASH (AM29LV065D)
4a551709	91	----------------------------------------------------------------------/
c935d3bd WD	92	#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
	93
	94	#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
	95	#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
4a551709 WD	96	#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
	97	#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
	98	#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
	99	#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
c935d3bd WD	100	#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
	101
	102	#else
	103	#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
	104	#endif
4a551709 WD	105
	106	/*------------------------------------------------------------------------
	107	* ENVIRONMENT
	108	----------------------------------------------------------------------/
c935d3bd WD	109	#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
c935d3bd WD	110
4a551709	111	#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
c935d3bd WD	112	#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
c935d3bd WD	113	#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
4a551709 WD	114	#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
4a551709 WD	115
c935d3bd WD	116	#else
	117	#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
	118	#endif
	119
4a551709 WD	120	/*------------------------------------------------------------------------
	121	* CONSOLE
	122	----------------------------------------------------------------------/
c935d3bd WD	123	#if (CFG_NIOS_CPU_UART_NUMS != 0)
	124
	125	#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
	126
	127	#if (CFG_NIOS_CPU_UART0_BR != 0)
	128	#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
	129	#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
	130	#else
	131	#undef CFG_NIOS_FIXEDBAUD
4a551709	132	#define CONFIG_BAUDRATE 115200
c935d3bd WD	133	#endif
	134
	135	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	136
	137	#else
	138	#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
	139	#endif
4a551709 WD	140
	141	/*------------------------------------------------------------------------
	142	* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
	143	* so an avalon bus timer is required.
	144	----------------------------------------------------------------------/
c935d3bd WD	145	#if (CFG_NIOS_CPU_TIMER_NUMS != 0)
	146
	147	#if (CFG_NIOS_CPU_TICK_TIMER == 0)
	148
63e73c9a WD	149	#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
	150	#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
	151
	152	#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
	153
	154	#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
	155	#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
	156	#else
	157	#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
	158	#endif
	159
	160	#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
	161
	162	#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
	163
	164	#if (CFG_HZ <= 1000)
	165	#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
	166	#else
	167	#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
	168	#endif
	169
	170	#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
	171
	172	#else
	173	#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
	174	#endif
c935d3bd WD	175
	176	#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
	177
	178	#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
	179	#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
	180
63e73c9a WD	181	#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
63e73c9a WD	182
c935d3bd WD	183	#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
	184	#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
	185	#else
63e73c9a WD	186	#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
	187	#endif
	188
	189	#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
	190
	191	#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
	192
	193	#if (CFG_HZ <= 1000)
	194	#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
	195	#else
	196	#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
	197	#endif
	198
	199	#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
	200
	201	#else
	202	#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
c935d3bd WD	203	#endif
	204
	205	#endif /* CFG_NIOS_CPU_TICK_TIMER */
	206
	207	#else
	208	#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
	209	#endif
4a551709 WD	210
4a551709 WD	211	/*------------------------------------------------------------------------
180d3f74	212	* Ethernet
4a551709	213	----------------------------------------------------------------------/
c935d3bd WD	214	#if (CFG_NIOS_CPU_LAN_NUMS == 1)
	215
	216	#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
	217
c935d3bd WD	218	#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
	219	#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
	220	#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
	221
	222	#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
	223	#define CONFIG_SMC_USE_32_BIT 1
	224	#else /* no */
	225	#undef CONFIG_SMC_USE_32_BIT
	226	#endif
	227
	228	#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
	229
	230	/********************************************/
	231	/* !!! CS8900 is __not__ tested on NIOS !!! */
	232	/********************************************/
	233	#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
	234	#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
	235
	236	#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
	237	#undef CS8900_BUS16
	238	#define CS8900_BUS32 1
	239	#else /* no */
	240	#define CS8900_BUS16 1
	241	#undef CS8900_BUS32
	242	#endif
	243
	244	#else
	245	#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
	246	#endif
4a551709 WD	247
	248	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	249	#define CONFIG_NETMASK 255.255.255.0
	250	#define CONFIG_IPADDR 192.168.2.21
	251	#define CONFIG_SERVERIP 192.168.2.16
	252
c935d3bd WD	253	#else
	254	#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
	255	#endif
	256
	257	/*------------------------------------------------------------------------
	258	* STATUS LEDs
	259	----------------------------------------------------------------------/
	260	#if (CFG_NIOS_CPU_PIO_NUMS != 0)
	261
	262	#if (CFG_NIOS_CPU_LED_PIO == 0)
	263
	264	#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
	265
	266	#elif (CFG_NIOS_CPU_LED_PIO == 1)
	267
	268	#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
	269
	270	#elif (CFG_NIOS_CPU_LED_PIO == 2)
	271
	272	#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
	273	#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
	274	#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
	275
	276	#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
	277	#define STATUS_LED_WRONLY 1
	278	#else
	279	#undef STATUS_LED_WRONLY
	280	#endif
	281
	282	#elif (CFG_NIOS_CPU_LED_PIO == 3)
	283
	284	#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
	285
	286	#elif (CFG_NIOS_CPU_LED_PIO == 4)
	287
	288	#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
	289
	290	#elif (CFG_NIOS_CPU_LED_PIO == 5)
	291
	292	#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
	293
	294	#elif (CFG_NIOS_CPU_LED_PIO == 6)
	295
	296	#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
	297
	298	#elif (CFG_NIOS_CPU_LED_PIO == 7)
	299
	300	#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
	301
	302	#elif (CFG_NIOS_CPU_LED_PIO == 8)
	303
	304	#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
	305
	306	#elif (CFG_NIOS_CPU_LED_PIO == 9)
	307
	308	#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
	309
	310	#else
	311	#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
	312	#endif
	313
	314	#define CONFIG_STATUS_LED 1 /* enable status led driver */
	315
	316	#define STATUS_LED_BIT (1 << 0) /* LED[0] */
317	#define STATUS_LED_STATE STATUS_LED_BLINKING
318	#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
319	#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
320	#define STATUS_LED_BOOT 0 /* boot LED */
321
322	#if (STATUS_LED_BITS > 1)
323	#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
324	#define STATUS_LED_STATE1 STATUS_LED_OFF
325	#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
326	#define STATUS_LED_RED 1 /* fail LED */
327	#endif
328
329	#if (STATUS_LED_BITS > 2)
330	#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
331	#define STATUS_LED_STATE2 STATUS_LED_OFF
332	#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
333	#define STATUS_LED_YELLOW 2 /* info LED */
334	#endif
335
336	#if (STATUS_LED_BITS > 3)
337	#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
338	#define STATUS_LED_STATE3 STATUS_LED_OFF
339	#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
340	#define STATUS_LED_GREEN 3 /* info LED */
341	#endif
342
343	#define STATUS_LED_PAR 1 /* makes status_led.h happy */
344
345	#endif /* CFG_NIOS_CPU_PIO_NUMS */
346
347	/*------------------------------------------------------------------------
348	* SEVEN SEGMENT LED DISPLAY
349	----------------------------------------------------------------------/
350	#if (CFG_NIOS_CPU_PIO_NUMS != 0)
351
352	#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
353
ec4c544b	354	#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
c935d3bd WD	355
	356	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
	357
ec4c544b	358	#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
c935d3bd WD	359
	360	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
	361
ec4c544b	362	#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
c935d3bd WD	363
	364	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
	365
	366	#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
	367	#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
	368	#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
	369
	370	#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
	371	#define SEVENSEG_WRONLY 1
	372	#else
	373	#undef SEVENSEG_WRONLY
	374	#endif
	375
	376	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
	377
ec4c544b	378	#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
c935d3bd WD	379
	380	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
	381
ec4c544b	382	#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
c935d3bd WD	383
	384	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
	385
ec4c544b	386	#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
c935d3bd WD	387
	388	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
	389
ec4c544b	390	#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
c935d3bd WD	391
	392	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
	393
ec4c544b	394	#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
c935d3bd WD	395
	396	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
	397
ec4c544b	398	#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
c935d3bd WD	399
	400	#else
	401	#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
	402	#endif
	403
	404	#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
	405
	406	/*
	407	* Dual 7-Segment Display pin assignment -- read more in your
	408	* "Nios Development Board Reference Manual"
	409	*
	410	*
	411	* (U8) HI:D[15..8] (U9) LO:D[7..0]
	412	* ______ ______
	413	* \| D14 \| \| D6 \|
	414	* \| \| \| \|
	415	* D9\| \|D13 D1\| \|D5
	416	* \|______\| \|______\| ___
	417	* \| D8 \| \| D0 \| \| A \|
	418	* \| \| \| \| F\|___\|B
	419	* D10\| \|D12 D2\| \|D4 \| G \|
	420	* \|______\| \|______\| E\|___\|C
	421	* D11 * D3 * D *
	422	* D15 D7 DP
	423	*
	424	*/
	425	#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
	426	#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
	427	#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
	428	#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
	429	#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
	430	#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
	431	#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
	432	#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
	433	#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
	434
	435	#endif /* CFG_NIOS_CPU_PIO_NUMS */
	436
180d3f74 WD	437	/*------------------------------------------------------------------------
	438	* ASMI - Active Serial Memory Interface.
	439	*
	440	* ASMI is for Cyclone devices only and only works when the configuration
	441	* is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
	442	----------------------------------------------------------------------/
5653fc33 WD	443	#define CONFIG_NIOS_ASMI /* Enable ASMI */
5653fc33 WD	444	#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
180d3f74	445
4a551709 WD	446	/*------------------------------------------------------------------------
	447	* COMMANDS
	448	----------------------------------------------------------------------/
	449	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	450	CFG_CMD_ASKENV \| \
	451	CFG_CMD_BEDBUG \| \
	452	CFG_CMD_BMP \| \
	453	CFG_CMD_BSP \| \
	454	CFG_CMD_CACHE \| \
	455	CFG_CMD_DATE \| \
	456	CFG_CMD_DOC \| \
	457	CFG_CMD_DTT \| \
	458	CFG_CMD_EEPROM \| \
	459	CFG_CMD_ELF \| \
	460	CFG_CMD_FAT \| \
	461	CFG_CMD_FDC \| \
	462	CFG_CMD_FDOS \| \
	463	CFG_CMD_HWFLOW \| \
	464	CFG_CMD_IDE \| \
	465	CFG_CMD_I2C \| \
	466	CFG_CMD_JFFS2 \| \
	467	CFG_CMD_KGDB \| \
	468	CFG_CMD_NAND \| \
4a551709 WD	469	CFG_CMD_MMC \| \
	470	CFG_CMD_MII \| \
	471	CFG_CMD_PCI \| \
	472	CFG_CMD_PCMCIA \| \
	473	CFG_CMD_SCSI \| \
	474	CFG_CMD_SPI \| \
	475	CFG_CMD_VFD \| \
	476	CFG_CMD_USB ) )
	477
	478
	479	#include <cmd_confdefs.h>
	480
	481	/*------------------------------------------------------------------------
	482	* KGDB
	483	----------------------------------------------------------------------/
	484	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	485	#define CONFIG_KGDB_BAUDRATE 9600
	486	#endif
	487
	488	/*------------------------------------------------------------------------
	489	* MISC
	490	----------------------------------------------------------------------/
c935d3bd WD	491	#define CFG_LONGHELP /* undef to save memory */
	492	#define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */
	493	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
4a551709	494	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
c935d3bd WD	495	#define CFG_MAXARGS 16 /* max number of command args*/
	496	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	497
	498	#if (CFG_SRAM_SIZE != 0)
	499	#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
	500	#else
	501	#undef CFG_LOAD_ADDR
	502	#endif
4a551709	503
c935d3bd WD	504	#if (CFG_SDRAM_SIZE != 0)
	505	#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
	506	#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
	507	#else
	508	#undef CFG_MEMTEST_START
	509	#undef CFG_MEMTEST_END
	510	#endif
4a551709 WD	511
	512
	513	#endif /* __CONFIG_H */