projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2e5983d2 WD |
1 | /* |
| 2 | * | |
| 3 | * BRIEF MODULE DESCRIPTION | |
| 4 | * OMAP hardware map | |
| 5 | * | |
| 6 | * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) | |
| 7 | * Author: RidgeRun, Inc. | |
| 8 | * Greg Lonnon ([email protected]) or [email protected] | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify it | |
| 11 | * under the terms of the GNU General Public License as published by the | |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 13 | * option) any later version. | |
| 14 | * | |
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License along | |
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 29 | */ | |
| 30 | ||
| 31 | #include <asm/arch/sizes.h> | |
| 32 | ||
| 33 | /* | |
| 34 | There are 2 sets of general I/O --> | |
| 35 | 1. GPIO (shared between ARM & DSP, configured by ARM) | |
| 36 | 2. MPUIO which can be used only by the ARM. | |
| 37 | ||
| 38 | Base address FFFB:5000 is where the ARM accesses the MPUIO control registers | |
| 39 | (see 7.2.2 of the TRM for MPUIO reg definitions). | |
| 40 | ||
| 41 | Base address E101:5000 is reserved for ARM access of the same MPUIO control | |
| 42 | regs, but via the DSP I/O map. This address is unavailable on 1510. | |
| 43 | ||
| 44 | Base address FFFC:E000 is where the ARM accesses the GPIO config registers | |
| 45 | directly via its own peripheral bus. | |
| 46 | ||
| 47 | Base address E101:E000 is where the ARM can access the same GPIO config | |
| 48 | registers, but the access takes place through the ARM port interface (called | |
| 49 | API or MPUI) via the DSP's peripheral bus (DSP I/O space). | |
| 50 | ||
| 51 | Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses | |
| 52 | instead of the E101:E000 addresses. The DSP has only read access of the pin | |
| 53 | control register, so this may explain the inability to write to E101:E018. | |
| 54 | Try accessing pin control reg at FFFC:E018. | |
| 55 | */ | |
| 56 | #define OMAP1510_GPIO_BASE 0xfffce000 | |
| 57 | #define OMAP1510_GPIO_START OMAP1510_GPIO_BASE | |
| 58 | #define OMAP1510_GPIO_SIZE SZ_4K | |
| 59 | ||
| 60 | #define OMAP1510_MCBSP1_BASE 0xE1011000 | |
| 61 | #define OMAP1510_MCBSP1_SIZE SZ_4K | |
| 62 | #define OMAP1510_MCBSP1_START 0xE1011000 | |
| 63 | ||
| 64 | #define OMAP1510_MCBSP2_BASE 0xFFFB1000 | |
| 65 | ||
| 66 | #define OMAP1510_MCBSP3_BASE 0xE1017000 | |
| 67 | #define OMAP1510_MCBSP3_SIZE SZ_4K | |
| 68 | #define OMAP1510_MCBSP3_START 0xE1017000 | |
| 69 | ||
| 70 | /* | |
| 71 | * Where's the flush address (for flushing D and I cache?) | |
| 72 | */ | |
| 73 | #define FLUSH_BASE 0xdf000000 | |
| 74 | #define FLUSH_BASE_PHYS 0x00000000 | |
| 75 | ||
| 76 | #ifndef __ASSEMBLER__ | |
| 77 | ||
| 78 | #define PCIO_BASE 0 | |
| 79 | ||
| 80 | /* | |
| 81 | * RAM definitions | |
| 82 | */ | |
| 83 | #define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) | |
| 84 | #define KERNTOPHYS(a) ((unsigned long)(&a)) | |
| 85 | #define KERNEL_BASE (0x10008000) | |
| 86 | #endif | |
| 87 | ||
| 88 | /* macro to get at IO space when running virtually */ | |
| 89 | #define IO_ADDRESS(x) ((x)) | |
| 90 | ||
| 91 | /* ---------------------------------------------------------------------------- | |
| 92 | * OMAP1510 system registers | |
| 93 | * ---------------------------------------------------------------------------- | |
| 94 | */ | |
| 95 | ||
| 96 | #define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ | |
| 97 | #define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ | |
| 98 | #define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ | |
| 99 | #define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ | |
| 100 | #define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ | |
| 101 | #define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ | |
| 102 | #define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ | |
| 103 | ||
| 104 | /* | |
| 105 | * OMAP1510 UART3 Registers | |
| 106 | */ | |
| 107 | ||
| 108 | #define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ | |
| 109 | ||
| 110 | /* UART3 Registers Maping through MPU bus */ | |
| 111 | ||
| 112 | #define UART3_RHR (OMAP_MPU_UART3_BASE + 0) | |
| 113 | #define UART3_THR (OMAP_MPU_UART3_BASE + 0) | |
| 114 | #define UART3_DLL (OMAP_MPU_UART3_BASE + 0) | |
| 115 | #define UART3_IER (OMAP_MPU_UART3_BASE + 4) | |
| 116 | #define UART3_DLH (OMAP_MPU_UART3_BASE + 4) | |
| 117 | #define UART3_IIR (OMAP_MPU_UART3_BASE + 8) | |
| 118 | #define UART3_FCR (OMAP_MPU_UART3_BASE + 8) | |
| 119 | #define UART3_EFR (OMAP_MPU_UART3_BASE + 8) | |
| 120 | #define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) | |
| 121 | #define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) | |
| 122 | #define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) | |
| 123 | #define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) | |
| 124 | #define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) | |
| 125 | #define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) | |
| 126 | #define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) | |
| 127 | #define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) | |
| 128 | #define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) | |
| 129 | #define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) | |
| 130 | #define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) | |
| 131 | #define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) | |
| 132 | #define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) | |
| 133 | #define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) | |
| 134 | #define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) | |
| 135 | #define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) | |
| 136 | #define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) | |
| 137 | #define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) | |
| 138 | #define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) | |
| 139 | #define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) | |
| 140 | #define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) | |
| 141 | #define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) | |
| 142 | #define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) | |
| 143 | #define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) | |
| 144 | #define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) | |
| 145 | #define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) | |
| 146 | #define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) | |
| 147 | #define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) | |
| 148 | #define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) | |
| 149 | ||
| 150 | /* | |
| 151 | * Configuration Registers | |
| 152 | */ | |
| 153 | #define FUNC_MUX_CTRL_0 0xfffe1000 | |
| 154 | #define FUNC_MUX_CTRL_1 0xfffe1004 | |
| 155 | #define FUNC_MUX_CTRL_2 0xfffe1008 | |
| 156 | #define COMP_MODE_CTRL_0 0xfffe100c | |
| 157 | #define FUNC_MUX_CTRL_3 0xfffe1010 | |
| 158 | #define FUNC_MUX_CTRL_4 0xfffe1014 | |
| 159 | #define FUNC_MUX_CTRL_5 0xfffe1018 | |
| 160 | #define FUNC_MUX_CTRL_6 0xfffe101C | |
| 161 | #define FUNC_MUX_CTRL_7 0xfffe1020 | |
| 162 | #define FUNC_MUX_CTRL_8 0xfffe1024 | |
| 163 | #define FUNC_MUX_CTRL_9 0xfffe1028 | |
| 164 | #define FUNC_MUX_CTRL_A 0xfffe102C | |
| 165 | #define FUNC_MUX_CTRL_B 0xfffe1030 | |
| 166 | #define FUNC_MUX_CTRL_C 0xfffe1034 | |
| 167 | #define FUNC_MUX_CTRL_D 0xfffe1038 | |
| 168 | #define PULL_DWN_CTRL_0 0xfffe1040 | |
| 169 | #define PULL_DWN_CTRL_1 0xfffe1044 | |
| 170 | #define PULL_DWN_CTRL_2 0xfffe1048 | |
| 171 | #define PULL_DWN_CTRL_3 0xfffe104c | |
| 172 | #define GATE_INH_CTRL_0 0xfffe1050 | |
| 173 | #define VOLTAGE_CTRL_0 0xfffe1060 | |
| 174 | #define TEST_DBG_CTRL_0 0xfffe1070 | |
| 175 | ||
| 176 | #define MOD_CONF_CTRL_0 0xfffe1080 | |
| 177 | ||
| 6f21347d WD |
178 | #ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ |
| 179 | ||
| 180 | #define USB_OTG_CTRL 0xFFFB040C | |
| 181 | #define USB_TRANSCEIVER_CTRL 0xFFFE1064 | |
| 232c150a | 182 | #define PULL_DWN_CTRL_4 0xFFFE10AC |
| 6f21347d WD |
183 | #define PU_PD_SEL_0 0xFFFE10B4 |
| 184 | #define PU_PD_SEL_1 0xFFFE10B8 | |
| 185 | #define PU_PD_SEL_2 0xFFFE10BC | |
| 186 | #define PU_PD_SEL_3 0xFFFE10C0 | |
| 187 | #define PU_PD_SEL_4 0xFFFE10C4 | |
| 188 | ||
| 189 | #endif | |
| 2e5983d2 WD |
190 | /* |
| 191 | * Traffic Controller Memory Interface Registers | |
| 192 | */ | |
| 193 | #define TCMIF_BASE 0xfffecc00 | |
| 194 | #define IMIF_PRIO (TCMIF_BASE + 0x00) | |
| 195 | #define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) | |
| 196 | #define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) | |
| 197 | #define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) | |
| 198 | #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) | |
| 199 | #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) | |
| 200 | #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) | |
| 201 | #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) | |
| 202 | #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) | |
| 203 | #define EMIFF_MRS (TCMIF_BASE + 0x24) | |
| 204 | #define TC_TIMEOUT1 (TCMIF_BASE + 0x28) | |
| 205 | #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) | |
| 206 | #define TC_TIMEOUT3 (TCMIF_BASE + 0x30) | |
| 207 | #define TC_ENDIANISM (TCMIF_BASE + 0x34) | |
| 208 | #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) | |
| 209 | #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) | |
| 210 | ||
| 211 | /* | |
| 212 | * LCD Panel | |
| 213 | */ | |
| 214 | #define TI925_LCD_BASE 0xFFFEC000 | |
| 215 | #define TI925_LCD_CONTROL (TI925_LCD_BASE) | |
| 216 | #define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) | |
| 217 | #define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) | |
| 218 | #define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) | |
| 219 | #define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) | |
| 220 | #define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) | |
| 221 | ||
| 222 | #define OMAP_LCD_CONTROL TI925_LCD_CONTROL | |
| 223 | ||
| 232c150a WD |
224 | /* I2C Registers */ |
| 225 | ||
| 226 | #define I2C_BASE 0xfffb3800 | |
| 227 | ||
| 228 | #define I2C_REV (I2C_BASE + 0x00) | |
| 229 | #define I2C_IE (I2C_BASE + 0x04) | |
| 230 | #define I2C_STAT (I2C_BASE + 0x08) | |
| 231 | #define I2C_IV (I2C_BASE + 0x0c) | |
| 232 | #define I2C_BUF (I2C_BASE + 0x14) | |
| 233 | #define I2C_CNT (I2C_BASE + 0x18) | |
| 234 | #define I2C_DATA (I2C_BASE + 0x1c) | |
| 235 | #define I2C_CON (I2C_BASE + 0x24) | |
| 236 | #define I2C_OA (I2C_BASE + 0x28) | |
| 237 | #define I2C_SA (I2C_BASE + 0x2c) | |
| 238 | #define I2C_PSC (I2C_BASE + 0x30) | |
| 239 | #define I2C_SCLL (I2C_BASE + 0x34) | |
| 240 | #define I2C_SCLH (I2C_BASE + 0x38) | |
| 241 | #define I2C_SYSTEST (I2C_BASE + 0x3c) | |
| 242 | ||
| 243 | /* I2C masks */ | |
| 244 | ||
| 245 | /* I2C Interrupt Enable Register (I2C_IE): */ | |
| 246 | ||
| 247 | #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ | |
| 248 | #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ | |
| 249 | #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ | |
| 250 | #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ | |
| 251 | #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ | |
| 252 | ||
| 253 | /* I2C Status Register (I2C_STAT): */ | |
| 254 | ||
| 255 | #define I2C_STAT_SBD (1 << 15) /* Single byte data */ | |
| 256 | #define I2C_STAT_BB (1 << 12) /* Bus busy */ | |
| 257 | #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
| 258 | #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
| 259 | #define I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
| 260 | #define I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
| 261 | #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
| 262 | #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
| 263 | #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
| 264 | #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ | |
| 265 | #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ | |
| 266 | ||
| 267 | /* I2C Interrupt Vector Register (I2C_IV): */ | |
| 268 | ||
| 269 | /* I2C Interrupt Code Register (I2C_INTCODE): */ | |
| 270 | ||
| 271 | #define I2C_INTCODE_MASK 7 | |
| 272 | #define I2C_INTCODE_NONE 0 | |
| 273 | #define I2C_INTCODE_AL 1 /* Arbitration lost */ | |
| 274 | #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ | |
| 275 | #define I2C_INTCODE_ARDY 3 /* Register access ready */ | |
| 276 | #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ | |
| 277 | #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ | |
| 278 | ||
| 279 | /* I2C Buffer Configuration Register (I2C_BUF): */ | |
| 280 | ||
| 281 | #define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ | |
| 282 | #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ | |
| 283 | ||
| 284 | /* I2C Configuration Register (I2C_CON): */ | |
| 285 | ||
| 286 | #define I2C_CON_EN (1 << 15) /* I2C module enable */ | |
| 287 | #define I2C_CON_BE (1 << 14) /* Big endian mode */ | |
| 288 | #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ | |
| 289 | #define I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
| 290 | #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ | |
| 291 | #define I2C_CON_XA (1 << 8) /* Expand address */ | |
| 292 | #define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ | |
| 293 | #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ | |
| 294 | #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ | |
| 295 | ||
| 296 | /* I2C System Test Register (I2C_SYSTEST): */ | |
| 297 | ||
| 298 | #define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
| 299 | #define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ | |
| 300 | #define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
| 301 | #define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
| 302 | #define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ | |
| 303 | #define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ | |
| 304 | #define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ | |
| 305 | #define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ | |
| 306 | ||
| 2e5983d2 WD |
307 | /* |
| 308 | * MMC/SD Host Controller Registers | |
| 309 | */ | |
| 310 | ||
| 311 | #define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ | |
| 312 | #define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ | |
| 313 | #define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ | |
| 314 | #define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ | |
| 315 | #define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ | |
| 316 | #define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ | |
| 317 | #define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ | |
| 318 | #define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ | |
| 319 | #define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ | |
| 320 | #define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ | |
| 321 | #define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ | |
| 322 | #define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ | |
| 323 | #define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ | |
| 324 | #define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ | |
| 325 | #define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ | |
| 326 | #define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ | |
| 327 | #define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ | |
| 328 | #define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ | |
| 329 | #define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ | |
| 330 | #define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ | |
| 331 | #define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ | |
| 332 | #define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ | |
| 333 | #define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ | |
| 334 | #define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ | |
| 335 | ||
| 336 | /* MMC masks */ | |
| 337 | ||
| 338 | #define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ | |
| 339 | #define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ | |
| 340 | #define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ | |
| 341 | #define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ | |
| 342 | #define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ | |
| 343 | #define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ | |
| 344 | #define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ | |
| 345 | #define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ | |
| 346 | #define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ | |
| 347 | #define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ | |
| 348 | #define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ | |
| 349 | #define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ | |
| 350 | #define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ | |
| 351 | ||
| 352 | /* 2.9.2 MPUI Interface Registers FFFE:C900 */ | |
| 353 | ||
| 354 | #define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) | |
| 355 | #define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) | |
| 356 | #define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) | |
| 357 | #define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) | |
| 358 | #define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) | |
| 359 | #define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) | |
| 360 | #define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) | |
| 361 | #define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) | |
| 362 | ||
| 363 | /* 2.9.6 Traffic Controller Memory Interface Registers: */ | |
| 364 | #define OMAP_IMIF_PRIO_REG 0xfffecc00 | |
| 365 | #define OMAP_EMIFS_PRIO_REG 0xfffecc04 | |
| 366 | #define OMAP_EMIFF_PRIO_REG 0xfffecc08 | |
| 367 | #define OMAP_EMIFS_CONFIG_REG 0xfffecc0c | |
| 368 | #define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 | |
| 369 | #define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 | |
| 370 | #define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 | |
| 371 | #define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c | |
| 372 | #define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 | |
| 373 | #define OMAP_EMIFF_MRS 0xfffecc24 | |
| 374 | #define OMAP_TIMEOUT1 0xfffecc28 | |
| 375 | #define OMAP_TIMEOUT2 0xfffecc2c | |
| 376 | #define OMAP_TIMEOUT3 0xfffecc30 | |
| 377 | #define OMAP_ENDIANISM 0xfffecc34 | |
| 378 | ||
| 379 | /* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ | |
| 380 | #define OMAP_EMIFS_CONFIG_FR (1 << 4) | |
| 381 | #define OMAP_EMIFS_CONFIG_PDE (1 << 3) | |
| 382 | #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) | |
| 383 | #define OMAP_EMIFS_CONFIG_BM (1 << 1) | |
| 384 | #define OMAP_EMIFS_CONFIG_WP (1 << 0) | |
| 385 | ||
| 386 | /* | |
| 387 | * Memory chunk set aside for the Framebuffer in SRAM | |
| 388 | */ | |
| 389 | #define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE | |
| 390 | ||
| 391 | ||
| 392 | /* | |
| 393 | * DMA | |
| 394 | */ | |
| 395 | ||
| 396 | #define OMAP1510_DMA_BASE 0xFFFED800 | |
| 397 | #define OMAP_DMA_BASE OMAP1510_DMA_BASE | |
| 398 | ||
| 399 | /* Global Register selection */ | |
| 400 | #define NO_GLOBAL_DMA_ACCESS 0 | |
| 401 | ||
| 402 | /* Channel select field | |
| 403 | * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... | |
| 404 | */ | |
| 405 | #define LCD_CHANNEL 0xc | |
| 406 | ||
| 407 | /* Register Select Field (LCD) */ | |
| 408 | #define DMA_LCD_CTRL 0 | |
| 409 | #define DMA_LCD_TOP_F1_L 1 | |
| 410 | #define DMA_LCD_TOP_F1_U 2 | |
| 411 | #define DMA_LCD_BOT_F1_L 3 | |
| 412 | #define DMA_LCD_BOT_F1_U 4 | |
| 413 | ||
| 414 | #define LCD_FRAME_MODE (1<<0) | |
| 415 | #define LCD_FRAME_IT_IE (1<<1) | |
| 416 | #define LCD_BUS_ERROR_IT_IE (1<<2) | |
| 417 | #define LCD_FRAME_1_IT_COND (1<<3) | |
| 418 | #define LCD_FRAME_2_IT_COND (1<<4) | |
| 419 | #define LCD_BUS_ERROR_IT_COND (1<<5) | |
| 420 | #define LCD_SOURCE_IMIF (1<<6) | |
| 421 | ||
| 422 | /* | |
| 423 | * Real-Time Clock | |
| 424 | */ | |
| 425 | ||
| 426 | #define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) | |
| 427 | #define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) | |
| 428 | #define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) | |
| 429 | #define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) | |
| 430 | #define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) | |
| 431 | #define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) | |
| 432 | #define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) | |
| 433 | ||
| 434 | ||
| 435 | /* --------------------------------------------------------------------------- | |
| 436 | * OMAP1510 Interrupt Handlers | |
| 437 | * --------------------------------------------------------------------------- | |
| 438 | * | |
| 439 | */ | |
| 440 | #define OMAP_IH1_BASE 0xfffecb00 | |
| 441 | #define OMAP_IH2_BASE 0xfffe0000 | |
| 442 | #define OMAP1510_ITR 0x0 | |
| 443 | #define OMAP1510_MASK 0x4 | |
| 444 | ||
| 445 | #define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE | |
| 446 | #define INTERRUPT_INPUT_REGISTER OMAP1510_ITR | |
| 447 | #define INTERRUPT_MASK_REGISTER OMAP1510_MASK | |
| 448 | ||
| 449 | ||
| 450 | /* --------------------------------------------------------------------------- | |
| 451 | * OMAP1510 TIMERS | |
| 452 | * --------------------------------------------------------------------------- | |
| 453 | * | |
| 454 | */ | |
| 455 | ||
| 456 | #define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 | |
| 457 | ||
| 458 | /* 32k Timer Registers */ | |
| 459 | #define TIMER32k_CR 0x08 | |
| 460 | #define TIMER32k_TVR 0x00 | |
| 461 | #define TIMER32k_TCR 0x04 | |
| 462 | ||
| 463 | /* 32k Timer Control Register definition */ | |
| 464 | #define TIMER32k_TSS (1<<0) | |
| 465 | #define TIMER32k_TRB (1<<1) | |
| 466 | #define TIMER32k_INT (1<<2) | |
| 467 | #define TIMER32k_ARL (1<<3) | |
| 468 | ||
| 469 | /* MPU Timer base addresses */ | |
| 470 | #define OMAP1510_MPUTIMER_BASE 0xfffec500 | |
| 471 | #define OMAP1510_MPUTIMER_OFF 0x00000100 | |
| 472 | ||
| 473 | #define OMAP1510_TIMER1_BASE 0xfffec500 | |
| 474 | #define OMAP1510_TIMER2_BASE 0xfffec600 | |
| 475 | #define OMAP1510_TIMER3_BASE 0xfffec700 | |
| 476 | ||
| 477 | /* MPU Timer Registers */ | |
| 478 | #define CNTL_TIMER 0 | |
| 479 | #define LOAD_TIM 4 | |
| 480 | #define READ_TIM 8 | |
| 481 | ||
| 482 | /* CNTL_TIMER register bits */ | |
| 483 | #define MPUTIM_FREE (1<<6) | |
| 484 | #define MPUTIM_CLOCK_ENABLE (1<<5) | |
| 485 | #define MPUTIM_PTV_MASK (0x7<<PTV_BIT) | |
| 486 | #define MPUTIM_PTV_BIT 2 | |
| 487 | #define MPUTIM_AR (1<<1) | |
| 488 | #define MPUTIM_ST (1<<0) | |
| 489 | ||
| 490 | /* --------------------------------------------------------------------------- | |
| 491 | * OMAP1510 GPIO (SHARED) | |
| 492 | * --------------------------------------------------------------------------- | |
| 493 | * | |
| 494 | */ | |
| 495 | #define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) | |
| 496 | #define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) | |
| 497 | #define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) | |
| 498 | #define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) | |
| 499 | #define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) | |
| 500 | #define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) | |
| 501 | #define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) | |
| 502 | ||
| 503 | ||
| 504 | /* --------------------------- | |
| 505 | * OMAP1510 MPUIO (ARM only) | |
| 506 | *---------------------------- | |
| 507 | */ | |
| 508 | #define OMAP1510_MPUIO_BASE 0xFFFB5000 | |
| 509 | #define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) | |
| 510 | #define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) | |
| 511 | #define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) | |
| 512 | ||
| 513 | /* --------------------------------------------------------------------------- | |
| 514 | * OMAP1510 TIPB (only) | |
| 515 | * --------------------------------------------------------------------------- | |
| 516 | * | |
| 517 | */ | |
| 518 | #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 | |
| 519 | #define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) | |
| 520 | #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 | |
| 521 | #define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) | |
| 522 | ||
| 523 | /* | |
| 524 | * --------------------------------------------------------------------------- | |
| 525 | * OMAP1510 Camera Interface | |
| 526 | * --------------------------------------------------------------------------- | |
| 527 | */ | |
| 528 | #define CAMERA_BASE (IO_BASE + 0x6800) | |
| 529 | #define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) | |
| 530 | #define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) | |
| 531 | #define CAM_MODE_REG (CAMERA_BASE + 0x08) | |
| 532 | #define CAM_STATUS_REG (CAMERA_BASE + 0x0C) | |
| 533 | #define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) | |
| 534 | #define CAM_GPIO_REG (CAMERA_BASE + 0x14) | |
| 535 | #define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) | |
| 536 | ||
| 537 | #if 0 | |
| 538 | #ifndef __ASSEMBLY__ | |
| 539 | typedef struct { | |
| 540 | __u32 ctrlclock; | |
| 541 | __u32 it_status; | |
| 542 | __u32 mode; | |
| 543 | __u32 status; | |
| 544 | __u32 camdata; | |
| 545 | __u32 gpio; | |
| 546 | __u32 peak_counter; | |
| 547 | } camera_regs_t; | |
| 548 | #endif | |
| 549 | #endif | |
| 550 | ||
| 551 | /* CTRLCLOCK bit shifts */ | |
| 552 | #define FOSCMOD_BIT 0 | |
| 553 | #define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) | |
| 554 | #define FOSCMOD_12MHz 0x0 | |
| 555 | #define FOSCMOD_6MHz 0x2 | |
| 556 | #define FOSCMOD_9_6MHz 0x4 | |
| 557 | #define FOSCMOD_24MHz 0x5 | |
| 558 | #define FOSCMOD_8MHz 0x6 | |
| 559 | #define POLCLK (1<<3) | |
| 560 | #define CAMEXCLK_EN (1<<4) | |
| 561 | #define MCLK_EN (1<<5) | |
| 562 | #define DPLL_EN (1<<6) | |
| 563 | #define LCLK_EN (1<<7) | |
| 564 | ||
| 565 | /* IT_STATUS bit shifts */ | |
| 566 | #define V_UP (1<<0) | |
| 567 | #define V_DOWN (1<<1) | |
| 568 | #define H_UP (1<<2) | |
| 569 | #define H_DOWN (1<<3) | |
| 570 | #define FIFO_FULL (1<<4) | |
| 571 | #define DATA_XFER (1<<5) | |
| 572 | ||
| 573 | /* MODE bit shifts */ | |
| 574 | #define CAMOSC (1<<0) | |
| 575 | #define IMGSIZE_BIT 1 | |
| 576 | #define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) | |
| 577 | #define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ | |
| 578 | #define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ | |
| 579 | #define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ | |
| 580 | #define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ | |
| 581 | #define ORDERCAMD (1<<3) | |
| 582 | #define EN_V_UP (1<<4) | |
| 583 | #define EN_V_DOWN (1<<5) | |
| 584 | #define EN_H_UP (1<<6) | |
| 585 | #define EN_H_DOWN (1<<7) | |
| 586 | #define EN_DMA (1<<8) | |
| 587 | #define THRESHOLD (1<<9) | |
| 588 | #define THRESHOLD_BIT 9 | |
| 589 | #define THRESHOLD_MASK (0x7f<<9) | |
| 590 | #define EN_NIRQ (1<<16) | |
| 591 | #define EN_FIFO_FULL (1<<17) | |
| 592 | #define RAZ_FIFO (1<<18) | |
| 593 | ||
| 594 | /* STATUS bit shifts */ | |
| 595 | #define VSTATUS (1<<0) | |
| 596 | #define HSTATUS (1<<1) | |
| 597 | ||
| 598 | /* GPIO bit shifts */ | |
| 599 | #define CAM_RST (1<<0) | |
| 600 | ||
| 601 | ||
| 602 | /********************* | |
| 603 | * Watchdog timer. | |
| 604 | *********************/ | |
| 605 | #define WDTIM_BASE 0xfffec800 | |
| 606 | #define WDTIM_CONTROL (WDTIM_BASE+0x00) | |
| 607 | #define WDTIM_LOAD (WDTIM_BASE+0x04) | |
| 608 | #define WDTIM_READ (WDTIM_BASE+0x04) | |
| 609 | #define WDTIM_MODE (WDTIM_BASE+0x08) | |
| 610 | ||
| 611 | /* Values to write to mode register to disable the watchdog function. */ | |
| 612 | #define DISABLE_SEQ1 0xF5 | |
| 613 | #define DISABLE_SEQ2 0xA0 | |
| 614 | ||
| 615 | /* WDTIM_CONTROL bit definitions. */ | |
| 616 | #define WDTIM_CONTROL_ST BIT7 | |
| 617 | ||
| 618 | ||
| 2e5983d2 WD |
619 | /* --------------------------------------------------------------------------- |
| 620 | * Differentiating processor versions for those who care. | |
| 621 | * --------------------------------------------------------------------------- | |
| 622 | * | |
| 623 | */ | |
| 624 | #define OMAP1509 0 | |
| 625 | #define OMAP1510 1 | |
| 626 | ||
| 627 | #define OMAP1510_ID_CODE_REG 0xfffed404 | |
| 628 | ||
| 629 | #ifndef __ASSEMBLY__ | |
| 630 | int cpu_type(void); | |
| 631 | #endif | |
| 632 | ||
| 633 | /* | |
| 634 | * EVM Implementation Specifics. | |
| 635 | * | |
| 636 | * *** NOTE *** | |
| 637 | * Any definitions in these files should be prefixed by an identifier - | |
| 638 | * eg. OMAP1510P1_FLASH0_BASE . | |
| 639 | * | |
| 640 | */ | |
| 641 | #ifdef CONFIG_OMAP_INNOVATOR | |
| 642 | #include "innovator.h" | |
| 643 | #endif | |
| 644 | ||
| 645 | #ifdef CONFIG_OMAP_1510P1 | |
| 646 | #include "omap1510p1.h" | |
| 647 | #endif | |
| 648 | ||
| 649 | /*****************************************************************************/ | |
| 650 | ||
| 651 | #define CLKGEN_RESET_BASE (0xfffece00) | |
| 652 | #define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) | |
| 653 | #define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) | |
| 654 | #define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) | |
| 655 | #define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) | |
| 656 | #define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) | |
| 657 | #define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) | |
| 658 | #define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) | |
| 659 | ||
| 660 | ||
| 661 | #define CK_CLKIN 12 /* MHz */ | |
| 662 | #define CK_RATEF 1 | |
| 663 | #define CK_IDLEF 2 | |
| 664 | #define CK_ENABLEF 4 | |
| 665 | #define CK_SELECTF 8 | |
| 666 | #ifndef __ASSEMBLER__ | |
| 667 | #define CK_DPLL1 ((volatile __u16 *)0xfffecf00) | |
| 668 | #else | |
| 669 | #define CK_DPLL1 (0xfffecf00) | |
| 670 | #endif | |
| 671 | #define SETARM_IDLE_SHIFT | |
| 672 | ||
| 673 | /* ARM_CKCTL bit shifts */ | |
| 674 | #define PERDIV 0 | |
| 675 | #define LCDDIV 2 | |
| 676 | #define ARMDIV 4 | |
| 677 | #define DSPDIV 6 | |
| 678 | #define TCDIV 8 | |
| 679 | #define DSPMMUDIV 10 | |
| 680 | #define ARM_TIMXO 12 | |
| 681 | #define EN_DSPCK 13 | |
| 682 | #define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ | |
| 683 | ||
| 684 | #define ARM_CKCTL_RSRVD_BIT15 (1 << 15) | |
| 685 | #define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) | |
| 686 | #define ARM_CKCTL_EN_DSPCK (1 << 13) | |
| 687 | #define ARM_CKCTL_ARM_TIMXO (1 << 12) | |
| 688 | #define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) | |
| 689 | #define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) | |
| 690 | #define ARM_CKCTL_TCDIV1 (1 << 9) | |
| 691 | #define ARM_CKCTL_TCDIV2 (1 << 8) | |
| 692 | #define ARM_CKCTL_DSPDIV1 (1 << 7) | |
| 693 | #define ARM_CKCTL_DSPDIV0 (1 << 6) | |
| 694 | #define ARM_CKCTL_ARMDIV1 (1 << 5) | |
| 695 | #define ARM_CKCTL_ARMDIV0 (1 << 4) | |
| 696 | #define ARM_CKCTL_LCDDIV1 (1 << 3) | |
| 697 | #define ARM_CKCTL_LCDDIV0 (1 << 2) | |
| 698 | #define ARM_CKCTL_PERDIV1 (1 << 1) | |
| 699 | #define ARM_CKCTL_PERDIV0 (1 << 0) | |
| 700 | ||
| 701 | /* ARM_IDLECT1 bit shifts */ | |
| 702 | #define IDLWDT_ARM 0 | |
| 703 | #define IDLXORP_ARM 1 | |
| 704 | #define IDLPER_ARM 2 | |
| 705 | #define IDLLCD_ARM 3 | |
| 706 | #define IDLLB_ARM 4 | |
| 707 | #define IDLHSAB_ARM 5 | |
| 708 | #define IDLIF_ARM 6 | |
| 709 | #define IDLDPLL_ARM 7 | |
| 710 | #define IDLAPI_ARM 8 | |
| 711 | #define IDLTIM_ARM 9 | |
| 712 | #define SETARM_IDLE 11 | |
| 713 | ||
| 714 | /* ARM_IDLECT2 bit shifts */ | |
| 715 | #define EN_WDTCK 0 | |
| 716 | #define EN_XORPCK 1 | |
| 717 | #define EN_PERCK 2 | |
| 718 | #define EN_LCDCK 3 | |
| 719 | #define EN_LBCK 4 | |
| 720 | #define EN_HSABCK 5 | |
| 721 | #define EN_APICK 6 | |
| 722 | #define EN_TIMCK 7 | |
| 723 | #define DMACK_REQ 8 | |
| 724 | #define EN_GPIOCK 9 | |
| 725 | #define EN_LBFREECK 10 | |
| 726 | ||
| 727 | #define ARM_RSTCT1_SW_RST (1 << 3) | |
| 728 | #define ARM_RSTCT1_DSP_RST (1 << 2) | |
| 729 | #define ARM_RSTCT1_DSP_EN (1 << 1) | |
| 730 | #define ARM_RSTCT1_ARM_RST (1 << 0) | |
| 731 | ||
| 732 | /* ARM_RSTCT2 bit shifts */ | |
| 733 | #define EN_PER 0 | |
| 734 | ||
| 735 | #define ARM_SYSST_RSRVD_BIT15 (1 << 15) | |
| 736 | #define ARM_SYSST_RSRVD_BIT14 (1 << 14) | |
| 737 | #define ARM_SYSST_CLOCK_SELECT2 (1 << 13) | |
| 738 | #define ARM_SYSST_CLOCK_SELECT1 (1 << 12) | |
| 739 | #define ARM_SYSST_CLOCK_SELECT0 (1 << 11) | |
| 740 | #define ARM_SYSST_RSRVD_BIT10 (1 << 10) | |
| 741 | #define ARM_SYSST_RSRVD_BIT9 (1 << 9) | |
| 742 | #define ARM_SYSST_RSRVD_BIT8 (1 << 8) | |
| 743 | #define ARM_SYSST_RSRVD_BIT7 (1 << 7) | |
| 744 | #define ARM_SYSST_IDLE_DSP (1 << 6) | |
| 745 | #define ARM_SYSST_POR (1 << 5) | |
| 746 | #define ARM_SYSST_EXT_RST (1 << 4) | |
| 747 | #define ARM_SYSST_ARM_MCRST (1 << 3) | |
| 748 | #define ARM_SYSST_ARM_WDRST (1 << 2) | |
| 749 | #define ARM_SYSST_GLOB_SWRST (1 << 1) | |
| 750 | #define ARM_SYSST_DSP_WDRST (1 << 0) | |
| 751 | ||
| 752 | /* Table 15-23. DPLL Control Registers: */ | |
| 753 | #define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) | |
| 754 | ||
| 755 | /* Table 15-24. Control Register (CTL_REG): */ | |
| 756 | ||
| 757 | #define DPLL_CTL_REG_IOB (1 << 13) | |
| 758 | #define DPLL_CTL_REG_PLL_MULT Fld(5,0) | |
| 759 | ||
| 760 | /*****************************************************************************/ | |
| 761 | ||
| 762 | /* OMAP INTERRUPT REGISTERS */ | |
| 763 | #define IRQ_ITR 0x00 | |
| 764 | #define IRQ_MIR 0x04 | |
| 765 | #define IRQ_SIR_IRQ 0x10 | |
| 766 | #define IRQ_SIR_FIQ 0x14 | |
| 767 | #define IRQ_CONTROL_REG 0x18 | |
| 768 | #define IRQ_ISR 0x9c | |
| 769 | #define IRQ_ILR0 0x1c | |
| 770 | ||
| 771 | #define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) | |
| 772 | #define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) | |
| 773 | ||
| 774 | /* INTERRUPT LEVEL REGISTER BITS */ | |
| 775 | #define ILR_PRIORITY_MASK (0x3c) | |
| 776 | #define ILR_PRIORITY_SHIFT (2) | |
| 777 | #define ILR_LEVEL_TRIGGER (1<<1) | |
| 778 | #define ILR_FIQ (1<<0) | |
| 779 | ||
| 780 | #define IRQ_LEVEL_INT 1 | |
| 781 | #define IRQ_EDGE_INT 0 | |
| 232c150a WD |
782 | |
| 783 | /* Macros to access registers */ | |
| 784 | #define outb(v,p) *(volatile u8 *) (p) = v | |
| 785 | #define outw(v,p) *(volatile u16 *) (p) = v | |
| 786 | #define outl(v,p) *(volatile u32 *) (p) = v | |
| 787 | ||
| 788 | #define inb(p) *(volatile u8 *) (p) | |
| 789 | #define inw(p) *(volatile u16 *) (p) | |
| 790 | #define inl(p) *(volatile u32 *) (p) |