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Commit | Line | Data |
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af2cbfd6 A |
1 | |
2 | config BITBANGMII | |
3 | bool "Bit-banged ethernet MII management channel support" | |
4 | ||
448dfb40 TR |
5 | config BITBANGMII_MULTI |
6 | bool "Enable the multi bus support" | |
7 | depends on BITBANGMII | |
8 | ||
af2cbfd6 A |
9 | config MV88E6352_SWITCH |
10 | bool "Marvell 88E6352 switch support" | |
11 | ||
12 | menuconfig PHYLIB | |
13 | bool "Ethernet PHY (physical media interface) support" | |
c946b0e9 | 14 | depends on NET |
af2cbfd6 A |
15 | help |
16 | Enable Ethernet PHY (physical media interface) support. | |
17 | ||
18 | if PHYLIB | |
19 | ||
16879cd2 JH |
20 | config PHY_ADDR_ENABLE |
21 | bool "Limit phy address" | |
22 | default y if ARCH_SUNXI | |
23 | help | |
24 | Select this if you want to control which phy address is used | |
25 | ||
26 | if PHY_ADDR_ENABLE | |
b30c4190 SM |
27 | config PHY_ADDR |
28 | int "PHY address" | |
29 | default 1 if ARCH_SUNXI | |
30 | default 0 | |
31 | help | |
32 | The address of PHY on MII bus. Usually in range of 0 to 31. | |
16879cd2 | 33 | endif |
b30c4190 | 34 | |
137963d7 FF |
35 | config B53_SWITCH |
36 | bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support." | |
37 | help | |
38 | Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches. | |
39 | This currently supports BCM53125 and similar models. | |
40 | ||
41 | if B53_SWITCH | |
42 | ||
43 | config B53_CPU_PORT | |
44 | int "CPU port" | |
45 | default 8 | |
46 | ||
47 | config B53_PHY_PORTS | |
48 | hex "Bitmask of PHY ports" | |
49 | ||
50 | endif # B53_SWITCH | |
51 | ||
af2cbfd6 | 52 | config MV88E61XX_SWITCH |
389488df | 53 | bool "Marvell MV88E61xx Ethernet switch PHY support." |
af2cbfd6 | 54 | |
b4f4b0f5 TH |
55 | if MV88E61XX_SWITCH |
56 | ||
57 | config MV88E61XX_CPU_PORT | |
58 | int "CPU Port" | |
59 | ||
60 | config MV88E61XX_PHY_PORTS | |
61 | hex "Bitmask of PHY Ports" | |
62 | ||
63 | config MV88E61XX_FIXED_PORTS | |
64 | hex "Bitmask of PHYless serdes Ports" | |
65 | ||
66 | endif # MV88E61XX_SWITCH | |
67 | ||
af2cbfd6 A |
68 | config PHYLIB_10G |
69 | bool "Generic 10G PHY support" | |
70 | ||
d79f1a85 ND |
71 | config PHY_ADIN |
72 | bool "Analog Devices Industrial Ethernet PHYs" | |
73 | help | |
74 | Add support for configuring RGMII on Analog Devices ADIN PHYs. | |
75 | ||
4506423a | 76 | menuconfig PHY_AQUANTIA |
af2cbfd6 | 77 | bool "Aquantia Ethernet PHYs support" |
1c650108 JG |
78 | select PHY_GIGE |
79 | select PHYLIB_10G | |
af2cbfd6 | 80 | |
4506423a JG |
81 | config PHY_AQUANTIA_UPLOAD_FW |
82 | bool "Aquantia firmware loading support" | |
4506423a JG |
83 | depends on PHY_AQUANTIA |
84 | help | |
85 | Aquantia PHYs use firmware which can be either loaded automatically | |
86 | from storage directly attached to the phy or loaded by the boot loader | |
87 | via MDIO commands. The firmware is loaded from a file, specified by | |
88 | the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options. | |
89 | ||
90 | config PHY_AQUANTIA_FW_PART | |
91 | string "Aquantia firmware partition" | |
92 | depends on PHY_AQUANTIA_UPLOAD_FW | |
93 | help | |
94 | Partition containing the firmware file. | |
95 | ||
96 | config PHY_AQUANTIA_FW_NAME | |
97 | string "Aquantia firmware filename" | |
98 | depends on PHY_AQUANTIA_UPLOAD_FW | |
99 | help | |
100 | Firmware filename. | |
101 | ||
af2cbfd6 A |
102 | config PHY_ATHEROS |
103 | bool "Atheros Ethernet PHYs support" | |
104 | ||
105 | config PHY_BROADCOM | |
106 | bool "Broadcom Ethernet PHYs support" | |
107 | ||
108 | config PHY_CORTINA | |
109 | bool "Cortina Ethernet PHYs support" | |
110 | ||
2a29a9a1 MA |
111 | config SYS_CORTINA_NO_FW_UPLOAD |
112 | bool "Cortina firmware loading support" | |
2a29a9a1 MA |
113 | depends on PHY_CORTINA |
114 | help | |
115 | Cortina phy has provision to store phy firmware in attached dedicated | |
116 | EEPROM. And boards designed with such EEPROM does not require firmware | |
117 | upload. | |
118 | ||
e78f16b7 TR |
119 | choice |
120 | prompt "Location of the Cortina firmware" | |
121 | default SYS_CORTINA_FW_IN_NOR | |
122 | depends on PHY_CORTINA | |
123 | ||
124 | config SYS_CORTINA_FW_IN_MMC | |
125 | bool "Cortina firmware in MMC" | |
126 | ||
127 | config SYS_CORTINA_FW_IN_NAND | |
128 | bool "Cortina firmware in NAND flash" | |
129 | ||
130 | config SYS_CORTINA_FW_IN_NOR | |
131 | bool "Cortina firmware in NOR flash" | |
132 | ||
133 | config SYS_CORTINA_FW_IN_REMOTE | |
134 | bool "Cortina firmware in remote device" | |
135 | ||
136 | config SYS_CORTINA_FW_IN_SPIFLASH | |
137 | bool "Cortina firmware in SPI flash" | |
138 | ||
139 | endchoice | |
140 | ||
e99b1dfc KS |
141 | config CORTINA_FW_ADDR |
142 | hex "Cortina Firmware Address" | |
143 | depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD | |
144 | default 0x0 | |
145 | ||
146 | config CORTINA_FW_LENGTH | |
147 | hex "Cortina Firmware Length" | |
148 | depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD | |
149 | default 0x40000 | |
150 | ||
a70d7b01 AC |
151 | config PHY_CORTINA_ACCESS |
152 | bool "Cortina Access Ethernet PHYs support" | |
153 | default y | |
154 | depends on CORTINA_NI_ENET | |
155 | help | |
156 | Cortina Access Ethernet PHYs init process | |
157 | ||
af2cbfd6 A |
158 | config PHY_DAVICOM |
159 | bool "Davicom Ethernet PHYs support" | |
160 | ||
161 | config PHY_ET1011C | |
162 | bool "LSI TruePHY ET1011C support" | |
163 | ||
164 | config PHY_LXT | |
165 | bool "LXT971 Ethernet PHY support" | |
166 | ||
167 | config PHY_MARVELL | |
168 | bool "Marvell Ethernet PHYs support" | |
169 | ||
8995a96d NA |
170 | config PHY_MESON_GXL |
171 | bool "Amlogic Meson GXL Internal PHY support" | |
172 | ||
af2cbfd6 A |
173 | config PHY_MICREL |
174 | bool "Micrel Ethernet PHYs support" | |
449ea2cd PT |
175 | help |
176 | Enable support for the GbE PHYs manufactured by Micrel (now | |
77b508d3 JB |
177 | a part of Microchip). This includes drivers for the KSZ804, KSZ8031, |
178 | KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx | |
179 | family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel | |
180 | KSZ90x1 family support" is selected). | |
449ea2cd PT |
181 | |
182 | if PHY_MICREL | |
183 | ||
184 | config PHY_MICREL_KSZ9021 | |
9a31c739 | 185 | bool |
d397f7c4 | 186 | select PHY_MICREL_KSZ90X1 |
d397f7c4 | 187 | |
449ea2cd | 188 | config PHY_MICREL_KSZ9031 |
9a31c739 | 189 | bool |
d397f7c4 | 190 | select PHY_MICREL_KSZ90X1 |
d397f7c4 AG |
191 | |
192 | config PHY_MICREL_KSZ90X1 | |
193 | bool "Micrel KSZ90x1 family support" | |
194 | select PHY_GIGE | |
195 | help | |
196 | Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If | |
197 | enabled, the extended register read/write for KSZ90x1 PHYs | |
198 | is supported through the 'mdio' command and any RGMII signal | |
199 | delays configured in the device tree will be applied to the | |
200 | PHY during initialization. | |
201 | ||
d397f7c4 AG |
202 | config PHY_MICREL_KSZ8XXX |
203 | bool "Micrel KSZ8xxx family support" | |
d397f7c4 | 204 | help |
77b508d3 | 205 | Enable support for the 8000 series 10/100 PHYs manufactured by Micrel |
d397f7c4 AG |
206 | (now a part of Microchip). This includes drivers for the KSZ804, |
207 | KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721. | |
208 | ||
449ea2cd | 209 | endif # PHY_MICREL |
af2cbfd6 | 210 | |
a5fd13ad JH |
211 | config PHY_MSCC |
212 | bool "Microsemi Corp Ethernet PHYs support" | |
213 | ||
af2cbfd6 A |
214 | config PHY_NATSEMI |
215 | bool "National Semiconductor Ethernet PHYs support" | |
216 | ||
3ef2050a RPNO |
217 | config PHY_NXP_C45_TJA11XX |
218 | tristate "NXP C45 TJA11XX PHYs" | |
219 | help | |
220 | Enable support for NXP C45 TJA11XX PHYs. | |
221 | Currently supports only the TJA1103 PHY. | |
222 | ||
a2f5c936 MT |
223 | config PHY_NXP_TJA11XX |
224 | bool "NXP TJA11XX Ethernet PHYs support" | |
225 | help | |
226 | Currently supports the NXP TJA1100 and TJA1101 PHY. | |
227 | ||
af2cbfd6 A |
228 | config PHY_REALTEK |
229 | bool "Realtek Ethernet PHYs support" | |
230 | ||
231 | config RTL8211X_PHY_FORCE_MASTER | |
232 | bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode" | |
233 | depends on PHY_REALTEK | |
234 | help | |
235 | Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F). | |
236 | This can work around link stability and data corruption issues on gigabit | |
237 | links which can occur in slave mode on certain PHYs, e.g. on the | |
238 | RTL8211C(L). | |
239 | ||
240 | Please note that two directly connected devices (i.e. via crossover cable) | |
241 | will not be able to establish a link between each other if they both force | |
242 | master mode. Multiple devices forcing master mode when connected by a | |
243 | network switch do not pose a problem as the switch configures its affected | |
244 | ports into slave mode. | |
245 | ||
246 | This option only affects gigabit links. If you must establish a direct | |
247 | connection between two devices which both force master mode, try forcing | |
248 | the link speed to 100MBit/s. | |
249 | ||
250 | If unsure, say N. | |
251 | ||
d47cfdbd CC |
252 | config RTL8211F_PHY_FORCE_EEE_RXC_ON |
253 | bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" | |
254 | depends on PHY_REALTEK | |
d47cfdbd CC |
255 | help |
256 | The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate | |
257 | transitions to/from a lower power consumption level (Low Power Idle | |
258 | mode) based on link utilization. When no packets are being | |
259 | transmitted, the system goes to Low Power Idle mode to save power. | |
260 | ||
261 | Under particular circumstances this setting can cause issues where | |
262 | the PHY is unable to transmit or receive any packet when in LPI mode. | |
263 | The problem is caused when the PHY is configured to stop receiving | |
264 | the xMII clock while it is signaling LPI. For some PHYs the bit | |
265 | configuring this behavior is set by the Linux kernel, causing the | |
266 | issue in U-Boot on reboot if the PHY retains the register value. | |
267 | ||
268 | Default n, which means that the PHY state is not changed. To work | |
269 | around the issues, change this setting to y. | |
270 | ||
fa6539a3 AST |
271 | config RTL8201F_PHY_S700_RMII_TIMINGS |
272 | bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings" | |
273 | depends on PHY_REALTEK | |
274 | help | |
275 | This provides an option to configure specific timing requirements (needed | |
276 | for proper PHY operations) for the PHY module present on ACTION SEMI S700 | |
277 | based cubieboard7. Exact timing requiremnets seems to be SoC specific | |
278 | (and it's undocumented) that comes from vendor code itself. | |
279 | ||
af2cbfd6 A |
280 | config PHY_SMSC |
281 | bool "Microchip(SMSC) Ethernet PHYs support" | |
282 | ||
283 | config PHY_TERANETICS | |
284 | bool "Teranetics Ethernet PHYs support" | |
285 | ||
286 | config PHY_TI | |
287 | bool "Texas Instruments Ethernet PHYs support" | |
bc0e578f DM |
288 | ---help--- |
289 | Adds PHY registration support for TI PHYs. | |
290 | ||
291 | config PHY_TI_DP83867 | |
292 | select PHY_TI | |
293 | bool "Texas Instruments Ethernet DP83867 PHY support" | |
294 | ---help--- | |
295 | Adds support for the TI DP83867 1Gbit PHY. | |
af2cbfd6 | 296 | |
f3e22eea DR |
297 | config PHY_TI_DP83869 |
298 | select PHY_TI | |
299 | bool "Texas Instruments Ethernet DP83869 PHY support" | |
300 | ---help--- | |
301 | Adds support for the TI DP83869 1Gbit PHY. | |
302 | ||
8882238c DM |
303 | config PHY_TI_GENERIC |
304 | select PHY_TI | |
305 | bool "Texas Instruments Generic Ethernet PHYs support" | |
306 | ---help--- | |
307 | Adds support for Generic TI PHYs that don't need special handling but | |
308 | the PHY name is associated with a PHY ID. | |
309 | ||
af2cbfd6 A |
310 | config PHY_VITESSE |
311 | bool "Vitesse Ethernet PHYs support" | |
312 | ||
313 | config PHY_XILINX | |
314 | bool "Xilinx Ethernet PHYs support" | |
315 | ||
f41e588c SDPP |
316 | config PHY_XILINX_GMII2RGMII |
317 | bool "Xilinx GMII to RGMII Ethernet PHYs support" | |
188ff18f | 318 | depends on DM_ETH |
f41e588c SDPP |
319 | help |
320 | This adds support for Xilinx GMII to RGMII IP core. This IP acts | |
321 | as bridge between MAC connected over GMII and external phy that | |
322 | is connected over RGMII interface. | |
323 | ||
a744a284 MS |
324 | config PHY_ETHERNET_ID |
325 | bool "Read ethernet PHY id" | |
326 | depends on DM_GPIO | |
327 | default y if ZYNQ_GEM | |
328 | help | |
329 | Enable this config to read ethernet phy id from the phy node of DT | |
330 | and create a phy device using id. | |
331 | ||
db40c1aa HS |
332 | config PHY_FIXED |
333 | bool "Fixed-Link PHY" | |
334 | depends on DM_ETH | |
335 | help | |
336 | Fixed PHY is used for having a 'fixed-link' to another MAC with a direct | |
337 | connection (MII, RGMII, ...). | |
338 | There is nothing like autoneogation and so | |
339 | on, the link is always up with fixed speed and fixed duplex-setting. | |
340 | More information: doc/device-tree-bindings/net/fixed-link.txt | |
341 | ||
f641a8ac SMJ |
342 | config PHY_NCSI |
343 | bool "NC-SI based PHY" | |
344 | depends on DM_ETH | |
345 | ||
af2cbfd6 | 346 | endif #PHYLIB |
16199a8b | 347 | |
612f7a61 TR |
348 | config FSL_MEMAC |
349 | bool "NXP mEMAC PHY support" | |
350 | ||
351 | config SYS_MEMAC_LITTLE_ENDIAN | |
352 | bool "mEMAC is access in little endian mode" | |
353 | depends on FSL_MEMAC || FSL_LS_MDIO | |
354 | ||
16199a8b TR |
355 | config PHY_RESET_DELAY |
356 | int "Extra delay after reset before MII register access" | |
357 | default 0 | |
358 | help | |
359 | Some PHYs need extra delay after reset before any MII register access | |
360 | is possible. For such PHY, set this option to the usec delay | |
361 | required. |