]> Git Repo - J-u-boot.git/blame - drivers/net/phy/Kconfig
Convert CONFIG_FSL_MEMAC et al to Kconfig
[J-u-boot.git] / drivers / net / phy / Kconfig
CommitLineData
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1
2config BITBANGMII
3 bool "Bit-banged ethernet MII management channel support"
4
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5config BITBANGMII_MULTI
6 bool "Enable the multi bus support"
7 depends on BITBANGMII
8
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9config MV88E6352_SWITCH
10 bool "Marvell 88E6352 switch support"
11
12menuconfig PHYLIB
13 bool "Ethernet PHY (physical media interface) support"
c946b0e9 14 depends on NET
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15 help
16 Enable Ethernet PHY (physical media interface) support.
17
18if PHYLIB
19
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20config PHY_ADDR_ENABLE
21 bool "Limit phy address"
22 default y if ARCH_SUNXI
23 help
24 Select this if you want to control which phy address is used
25
26if PHY_ADDR_ENABLE
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27config PHY_ADDR
28 int "PHY address"
29 default 1 if ARCH_SUNXI
30 default 0
31 help
32 The address of PHY on MII bus. Usually in range of 0 to 31.
16879cd2 33endif
b30c4190 34
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35config B53_SWITCH
36 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
37 help
38 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
39 This currently supports BCM53125 and similar models.
40
41if B53_SWITCH
42
43config B53_CPU_PORT
44 int "CPU port"
45 default 8
46
47config B53_PHY_PORTS
48 hex "Bitmask of PHY ports"
49
50endif # B53_SWITCH
51
af2cbfd6 52config MV88E61XX_SWITCH
389488df 53 bool "Marvell MV88E61xx Ethernet switch PHY support."
af2cbfd6 54
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55if MV88E61XX_SWITCH
56
57config MV88E61XX_CPU_PORT
58 int "CPU Port"
59
60config MV88E61XX_PHY_PORTS
61 hex "Bitmask of PHY Ports"
62
63config MV88E61XX_FIXED_PORTS
64 hex "Bitmask of PHYless serdes Ports"
65
66endif # MV88E61XX_SWITCH
67
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68config PHYLIB_10G
69 bool "Generic 10G PHY support"
70
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ND
71config PHY_ADIN
72 bool "Analog Devices Industrial Ethernet PHYs"
73 help
74 Add support for configuring RGMII on Analog Devices ADIN PHYs.
75
4506423a 76menuconfig PHY_AQUANTIA
af2cbfd6 77 bool "Aquantia Ethernet PHYs support"
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78 select PHY_GIGE
79 select PHYLIB_10G
af2cbfd6 80
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81config PHY_AQUANTIA_UPLOAD_FW
82 bool "Aquantia firmware loading support"
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83 depends on PHY_AQUANTIA
84 help
85 Aquantia PHYs use firmware which can be either loaded automatically
86 from storage directly attached to the phy or loaded by the boot loader
87 via MDIO commands. The firmware is loaded from a file, specified by
88 the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
89
90config PHY_AQUANTIA_FW_PART
91 string "Aquantia firmware partition"
92 depends on PHY_AQUANTIA_UPLOAD_FW
93 help
94 Partition containing the firmware file.
95
96config PHY_AQUANTIA_FW_NAME
97 string "Aquantia firmware filename"
98 depends on PHY_AQUANTIA_UPLOAD_FW
99 help
100 Firmware filename.
101
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102config PHY_ATHEROS
103 bool "Atheros Ethernet PHYs support"
104
105config PHY_BROADCOM
106 bool "Broadcom Ethernet PHYs support"
107
108config PHY_CORTINA
109 bool "Cortina Ethernet PHYs support"
110
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111config SYS_CORTINA_NO_FW_UPLOAD
112 bool "Cortina firmware loading support"
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113 depends on PHY_CORTINA
114 help
115 Cortina phy has provision to store phy firmware in attached dedicated
116 EEPROM. And boards designed with such EEPROM does not require firmware
117 upload.
118
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119choice
120 prompt "Location of the Cortina firmware"
121 default SYS_CORTINA_FW_IN_NOR
122 depends on PHY_CORTINA
123
124config SYS_CORTINA_FW_IN_MMC
125 bool "Cortina firmware in MMC"
126
127config SYS_CORTINA_FW_IN_NAND
128 bool "Cortina firmware in NAND flash"
129
130config SYS_CORTINA_FW_IN_NOR
131 bool "Cortina firmware in NOR flash"
132
133config SYS_CORTINA_FW_IN_REMOTE
134 bool "Cortina firmware in remote device"
135
136config SYS_CORTINA_FW_IN_SPIFLASH
137 bool "Cortina firmware in SPI flash"
138
139endchoice
140
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141config CORTINA_FW_ADDR
142 hex "Cortina Firmware Address"
143 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
144 default 0x0
145
146config CORTINA_FW_LENGTH
147 hex "Cortina Firmware Length"
148 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
149 default 0x40000
150
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151config PHY_CORTINA_ACCESS
152 bool "Cortina Access Ethernet PHYs support"
153 default y
154 depends on CORTINA_NI_ENET
155 help
156 Cortina Access Ethernet PHYs init process
157
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158config PHY_DAVICOM
159 bool "Davicom Ethernet PHYs support"
160
161config PHY_ET1011C
162 bool "LSI TruePHY ET1011C support"
163
164config PHY_LXT
165 bool "LXT971 Ethernet PHY support"
166
167config PHY_MARVELL
168 bool "Marvell Ethernet PHYs support"
169
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NA
170config PHY_MESON_GXL
171 bool "Amlogic Meson GXL Internal PHY support"
172
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173config PHY_MICREL
174 bool "Micrel Ethernet PHYs support"
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175 help
176 Enable support for the GbE PHYs manufactured by Micrel (now
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177 a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
178 KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
179 family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
180 KSZ90x1 family support" is selected).
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PT
181
182if PHY_MICREL
183
184config PHY_MICREL_KSZ9021
9a31c739 185 bool
d397f7c4 186 select PHY_MICREL_KSZ90X1
d397f7c4 187
449ea2cd 188config PHY_MICREL_KSZ9031
9a31c739 189 bool
d397f7c4 190 select PHY_MICREL_KSZ90X1
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191
192config PHY_MICREL_KSZ90X1
193 bool "Micrel KSZ90x1 family support"
194 select PHY_GIGE
195 help
196 Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
197 enabled, the extended register read/write for KSZ90x1 PHYs
198 is supported through the 'mdio' command and any RGMII signal
199 delays configured in the device tree will be applied to the
200 PHY during initialization.
201
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202config PHY_MICREL_KSZ8XXX
203 bool "Micrel KSZ8xxx family support"
d397f7c4 204 help
77b508d3 205 Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
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AG
206 (now a part of Microchip). This includes drivers for the KSZ804,
207 KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
208
449ea2cd 209endif # PHY_MICREL
af2cbfd6 210
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211config PHY_MSCC
212 bool "Microsemi Corp Ethernet PHYs support"
213
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214config PHY_NATSEMI
215 bool "National Semiconductor Ethernet PHYs support"
216
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217config PHY_NXP_C45_TJA11XX
218 tristate "NXP C45 TJA11XX PHYs"
219 help
220 Enable support for NXP C45 TJA11XX PHYs.
221 Currently supports only the TJA1103 PHY.
222
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223config PHY_NXP_TJA11XX
224 bool "NXP TJA11XX Ethernet PHYs support"
225 help
226 Currently supports the NXP TJA1100 and TJA1101 PHY.
227
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228config PHY_REALTEK
229 bool "Realtek Ethernet PHYs support"
230
231config RTL8211X_PHY_FORCE_MASTER
232 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
233 depends on PHY_REALTEK
234 help
235 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
236 This can work around link stability and data corruption issues on gigabit
237 links which can occur in slave mode on certain PHYs, e.g. on the
238 RTL8211C(L).
239
240 Please note that two directly connected devices (i.e. via crossover cable)
241 will not be able to establish a link between each other if they both force
242 master mode. Multiple devices forcing master mode when connected by a
243 network switch do not pose a problem as the switch configures its affected
244 ports into slave mode.
245
246 This option only affects gigabit links. If you must establish a direct
247 connection between two devices which both force master mode, try forcing
248 the link speed to 100MBit/s.
249
250 If unsure, say N.
251
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252config RTL8211F_PHY_FORCE_EEE_RXC_ON
253 bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
254 depends on PHY_REALTEK
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255 help
256 The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
257 transitions to/from a lower power consumption level (Low Power Idle
258 mode) based on link utilization. When no packets are being
259 transmitted, the system goes to Low Power Idle mode to save power.
260
261 Under particular circumstances this setting can cause issues where
262 the PHY is unable to transmit or receive any packet when in LPI mode.
263 The problem is caused when the PHY is configured to stop receiving
264 the xMII clock while it is signaling LPI. For some PHYs the bit
265 configuring this behavior is set by the Linux kernel, causing the
266 issue in U-Boot on reboot if the PHY retains the register value.
267
268 Default n, which means that the PHY state is not changed. To work
269 around the issues, change this setting to y.
270
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271config RTL8201F_PHY_S700_RMII_TIMINGS
272 bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
273 depends on PHY_REALTEK
274 help
275 This provides an option to configure specific timing requirements (needed
276 for proper PHY operations) for the PHY module present on ACTION SEMI S700
277 based cubieboard7. Exact timing requiremnets seems to be SoC specific
278 (and it's undocumented) that comes from vendor code itself.
279
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280config PHY_SMSC
281 bool "Microchip(SMSC) Ethernet PHYs support"
282
283config PHY_TERANETICS
284 bool "Teranetics Ethernet PHYs support"
285
286config PHY_TI
287 bool "Texas Instruments Ethernet PHYs support"
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288 ---help---
289 Adds PHY registration support for TI PHYs.
290
291config PHY_TI_DP83867
292 select PHY_TI
293 bool "Texas Instruments Ethernet DP83867 PHY support"
294 ---help---
295 Adds support for the TI DP83867 1Gbit PHY.
af2cbfd6 296
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297config PHY_TI_DP83869
298 select PHY_TI
299 bool "Texas Instruments Ethernet DP83869 PHY support"
300 ---help---
301 Adds support for the TI DP83869 1Gbit PHY.
302
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DM
303config PHY_TI_GENERIC
304 select PHY_TI
305 bool "Texas Instruments Generic Ethernet PHYs support"
306 ---help---
307 Adds support for Generic TI PHYs that don't need special handling but
308 the PHY name is associated with a PHY ID.
309
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310config PHY_VITESSE
311 bool "Vitesse Ethernet PHYs support"
312
313config PHY_XILINX
314 bool "Xilinx Ethernet PHYs support"
315
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316config PHY_XILINX_GMII2RGMII
317 bool "Xilinx GMII to RGMII Ethernet PHYs support"
188ff18f 318 depends on DM_ETH
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319 help
320 This adds support for Xilinx GMII to RGMII IP core. This IP acts
321 as bridge between MAC connected over GMII and external phy that
322 is connected over RGMII interface.
323
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MS
324config PHY_ETHERNET_ID
325 bool "Read ethernet PHY id"
326 depends on DM_GPIO
327 default y if ZYNQ_GEM
328 help
329 Enable this config to read ethernet phy id from the phy node of DT
330 and create a phy device using id.
331
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332config PHY_FIXED
333 bool "Fixed-Link PHY"
334 depends on DM_ETH
335 help
336 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
337 connection (MII, RGMII, ...).
338 There is nothing like autoneogation and so
339 on, the link is always up with fixed speed and fixed duplex-setting.
340 More information: doc/device-tree-bindings/net/fixed-link.txt
341
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342config PHY_NCSI
343 bool "NC-SI based PHY"
344 depends on DM_ETH
345
af2cbfd6 346endif #PHYLIB
16199a8b 347
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348config FSL_MEMAC
349 bool "NXP mEMAC PHY support"
350
351config SYS_MEMAC_LITTLE_ENDIAN
352 bool "mEMAC is access in little endian mode"
353 depends on FSL_MEMAC || FSL_LS_MDIO
354
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355config PHY_RESET_DELAY
356 int "Extra delay after reset before MII register access"
357 default 0
358 help
359 Some PHYs need extra delay after reset before any MII register access
360 is possible. For such PHY, set this option to the usec delay
361 required.
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